avr.md (zero_extendqihi2, [...]): Change to define_insn_and_split.
* config/avr/avr.md (zero_extendqihi2, zero_extendqisi2, zero_extendhisi2): Change to define_insn_and_split. (zero_extendqidi2, zero_extendhidi2, zero_extendsidi2): New. From-SVN: r126387
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Anatoly Sokolov
Anatoly Sokolov
parent
ec162f0dca
commit
2d0c44e63f
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@ -1,3 +1,9 @@
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2007-07-05 Anatoly Sokolov <aesok@post.ru>
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* config/avr/avr.md (zero_extendqihi2, zero_extendqisi2,
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zero_extendhisi2): Change to define_insn_and_split.
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(zero_extendqidi2, zero_extendhidi2, zero_extendsidi2): New.
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2007-07-05 Paolo Bonzini <bonzini@gnu.org>
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* function.c (match_asm_constraints_1, rest_of_match_asm_constraints,
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@ -1685,39 +1685,95 @@
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;; xx<---x xx<---x xx<---x xx<---x xx<---x xx<---x xx<---x xx<---x xx<---x
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;; zero extend
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(define_insn "zero_extendqihi2"
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[(set (match_operand:HI 0 "register_operand" "=r,r")
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(zero_extend:HI (match_operand:QI 1 "register_operand" "0,*r")))]
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(define_insn_and_split "zero_extendqihi2"
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[(set (match_operand:HI 0 "register_operand" "=r")
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(zero_extend:HI (match_operand:QI 1 "register_operand" "r")))]
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""
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"@
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clr %B0
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mov %A0,%A1\;clr %B0"
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[(set_attr "length" "1,2")
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(set_attr "cc" "set_n,set_n")])
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"#"
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"reload_completed"
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[(set (match_dup 2) (match_dup 1))
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(set (match_dup 3) (const_int 0))]
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"unsigned int low_off = subreg_lowpart_offset (QImode, HImode);
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unsigned int high_off = subreg_highpart_offset (QImode, HImode);
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operands[2] = simplify_gen_subreg (QImode, operands[0], HImode, low_off);
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operands[3] = simplify_gen_subreg (QImode, operands[0], HImode, high_off);
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")
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(define_insn "zero_extendqisi2"
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[(set (match_operand:SI 0 "register_operand" "=r,r")
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(zero_extend:SI (match_operand:QI 1 "register_operand" "0,*r")))]
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(define_insn_and_split "zero_extendqisi2"
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[(set (match_operand:SI 0 "register_operand" "=r")
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(zero_extend:SI (match_operand:QI 1 "register_operand" "r")))]
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""
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"@
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clr %B0\;clr %C0\;clr %D0
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mov %A0,%A1\;clr %B0\;clr %C0\;clr %D0"
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[(set_attr "length" "3,4")
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(set_attr "cc" "set_n,set_n")])
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"#"
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"reload_completed"
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[(set (match_dup 2) (zero_extend:HI (match_dup 1)))
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(set (match_dup 3) (const_int 0))]
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"unsigned int low_off = subreg_lowpart_offset (HImode, SImode);
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unsigned int high_off = subreg_highpart_offset (HImode, SImode);
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operands[2] = simplify_gen_subreg (HImode, operands[0], SImode, low_off);
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operands[3] = simplify_gen_subreg (HImode, operands[0], SImode, high_off);
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")
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(define_insn "zero_extendhisi2"
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[(set (match_operand:SI 0 "register_operand" "=r,&r")
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(zero_extend:SI (match_operand:HI 1 "register_operand" "0,*r")))]
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(define_insn_and_split "zero_extendhisi2"
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[(set (match_operand:SI 0 "register_operand" "=r")
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(zero_extend:SI (match_operand:HI 1 "register_operand" "r")))]
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""
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"@
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clr %C0\;clr %D0
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{mov %A0,%A1\;mov %B0,%B1|movw %A0,%A1}\;clr %C0\;clr %D0"
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[(set_attr_alternative "length"
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[(const_int 2)
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(if_then_else (eq_attr "mcu_have_movw" "yes")
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(const_int 3)
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(const_int 4))])
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(set_attr "cc" "set_n,set_n")])
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"#"
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"reload_completed"
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[(set (match_dup 2) (match_dup 1))
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(set (match_dup 3) (const_int 0))]
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"unsigned int low_off = subreg_lowpart_offset (HImode, SImode);
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unsigned int high_off = subreg_highpart_offset (HImode, SImode);
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operands[2] = simplify_gen_subreg (HImode, operands[0], SImode, low_off);
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operands[3] = simplify_gen_subreg (HImode, operands[0], SImode, high_off);
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")
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(define_insn_and_split "zero_extendqidi2"
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[(set (match_operand:DI 0 "register_operand" "=r")
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(zero_extend:DI (match_operand:QI 1 "register_operand" "r")))]
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""
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"#"
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"reload_completed"
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[(set (match_dup 2) (zero_extend:SI (match_dup 1)))
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(set (match_dup 3) (const_int 0))]
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"unsigned int low_off = subreg_lowpart_offset (SImode, DImode);
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unsigned int high_off = subreg_highpart_offset (SImode, DImode);
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operands[2] = simplify_gen_subreg (SImode, operands[0], DImode, low_off);
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operands[3] = simplify_gen_subreg (SImode, operands[0], DImode, high_off);
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")
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(define_insn_and_split "zero_extendhidi2"
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[(set (match_operand:DI 0 "register_operand" "=r")
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(zero_extend:DI (match_operand:HI 1 "register_operand" "r")))]
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""
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"#"
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"reload_completed"
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[(set (match_dup 2) (zero_extend:SI (match_dup 1)))
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(set (match_dup 3) (const_int 0))]
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"unsigned int low_off = subreg_lowpart_offset (SImode, DImode);
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unsigned int high_off = subreg_highpart_offset (SImode, DImode);
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operands[2] = simplify_gen_subreg (SImode, operands[0], DImode, low_off);
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operands[3] = simplify_gen_subreg (SImode, operands[0], DImode, high_off);
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")
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(define_insn_and_split "zero_extendsidi2"
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[(set (match_operand:DI 0 "register_operand" "=r")
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(zero_extend:DI (match_operand:SI 1 "register_operand" "r")))]
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""
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"#"
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"reload_completed"
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[(set (match_dup 2) (match_dup 1))
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(set (match_dup 3) (const_int 0))]
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"unsigned int low_off = subreg_lowpart_offset (SImode, DImode);
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unsigned int high_off = subreg_highpart_offset (SImode, DImode);
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operands[2] = simplify_gen_subreg (SImode, operands[0], DImode, low_off);
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operands[3] = simplify_gen_subreg (SImode, operands[0], DImode, high_off);
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")
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;;<=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=>
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;; compare
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