pa-protos.h (prefetch_operand): Delete.
* pa-protos.h (prefetch_operand): Delete. (prefetch_cc_operand, prefetch_nocc_operand): New declations. * pa.c (prefetch_operand): Delete. (prefetch_cc_operand, prefetch_nocc_operand): New functions. * pa.h (EXTRA_CONSTRAINT): Add `W' constraint. (PREDICATE_CODES): Delete prefetch_operand. Add prefetch_cc_operand and prefetch_nocc_operand. * pa.md (prefetch): Rework to avoid reload problems handling short displacements when a cache control completer needs to be provided. (prefetch_32, prefetch_64): Delete. (prefetch_cc, prefetch_nocc): New patterns. From-SVN: r93702
This commit is contained in:
John David Anglin
John David Anglin
parent
6a9836b1cd
commit
2d5ca9a017
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@ -1,3 +1,17 @@
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2005-01-15 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
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* pa-protos.h (prefetch_operand): Delete.
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(prefetch_cc_operand, prefetch_nocc_operand): New declations.
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* pa.c (prefetch_operand): Delete.
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(prefetch_cc_operand, prefetch_nocc_operand): New functions.
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* pa.h (EXTRA_CONSTRAINT): Add `W' constraint.
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(PREDICATE_CODES): Delete prefetch_operand. Add prefetch_cc_operand
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and prefetch_nocc_operand.
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* pa.md (prefetch): Rework to avoid reload problems handling short
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displacements when a cache control completer needs to be provided.
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(prefetch_32, prefetch_64): Delete.
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(prefetch_cc, prefetch_nocc): New patterns.
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2005-01-15 David Edelsohn <edelsohn@gnu.org>
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* config/rs6000/aix52.h (CPLUSPLUS_CPP_SPEC): Revert previous change.
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@ -79,7 +79,8 @@ extern int arith_operand (rtx, enum machine_mode);
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extern int read_only_operand (rtx, enum machine_mode);
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extern int move_dest_operand (rtx, enum machine_mode);
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extern int move_src_operand (rtx, enum machine_mode);
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extern int prefetch_operand (rtx, enum machine_mode);
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extern int prefetch_cc_operand (rtx, enum machine_mode);
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extern int prefetch_nocc_operand (rtx, enum machine_mode);
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extern int and_operand (rtx, enum machine_mode);
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extern int ior_operand (rtx, enum machine_mode);
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extern int arith32_operand (rtx, enum machine_mode);
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@ -752,24 +752,59 @@ move_src_operand (rtx op, enum machine_mode mode)
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}
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/* Accept anything that can be used as the source operand for a prefetch
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instruction. */
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instruction with a cache-control completer. */
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int
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prefetch_operand (rtx op, enum machine_mode mode)
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prefetch_cc_operand (rtx op, enum machine_mode mode)
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{
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if (GET_CODE (op) != MEM)
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return 0;
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op = XEXP (op, 0);
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/* We must reject virtual registers as we don't allow REG+D. */
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if (op == virtual_incoming_args_rtx
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|| op == virtual_stack_vars_rtx
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|| op == virtual_stack_dynamic_rtx
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|| op == virtual_outgoing_args_rtx
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|| op == virtual_cfa_rtx)
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return 0;
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if (!REG_P (op) && !IS_INDEX_ADDR_P (op))
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return 0;
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/* Until problems with management of the REG_POINTER flag are resolved,
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we need to delay creating prefetch insns with unscaled indexed addresses
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until CSE is not expected. */
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if (!TARGET_NO_SPACE_REGS
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&& !cse_not_expected
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&& GET_CODE (XEXP (op, 0)) == PLUS
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&& REG_P (XEXP (XEXP (op, 0), 0))
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&& REG_P (XEXP (XEXP (op, 0), 1)))
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&& GET_CODE (op) == PLUS
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&& REG_P (XEXP (op, 0)))
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return 0;
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return memory_address_p (mode, XEXP (op, 0));
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return memory_address_p (mode, op);
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}
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/* Accept anything that can be used as the source operand for a prefetch
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instruction with no cache-control completer. */
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int
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prefetch_nocc_operand (rtx op, enum machine_mode mode)
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{
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if (GET_CODE (op) != MEM)
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return 0;
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op = XEXP (op, 0);
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/* Until problems with management of the REG_POINTER flag are resolved,
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we need to delay creating prefetch insns with unscaled indexed addresses
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until CSE is not expected. */
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if (!TARGET_NO_SPACE_REGS
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&& !cse_not_expected
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&& GET_CODE (op) == PLUS
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&& REG_P (XEXP (op, 0))
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&& REG_P (XEXP (op, 1)))
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return 0;
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return memory_address_p (mode, op);
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}
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/* Accept REG and any CONST_INT that can be moved in one instruction into a
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@ -1296,7 +1296,12 @@ extern int may_call_alloca;
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`T' is for floating-point loads and stores.
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`U' is the constant 63. */
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`U' is the constant 63.
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`W' is a register indirect memory operand. We could allow short
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displacements but GO_IF_LEGITIMATE_ADDRESS can't tell when a
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long displacement is valid. This is only used for prefetch
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instructions with the `sl' completer. */
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#define EXTRA_CONSTRAINT(OP, C) \
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((C) == 'Q' ? \
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@ -1307,6 +1312,10 @@ extern int may_call_alloca;
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&& !symbolic_memory_operand (OP, VOIDmode) \
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&& !IS_LO_SUM_DLT_ADDR_P (XEXP (OP, 0)) \
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&& !IS_INDEX_ADDR_P (XEXP (OP, 0)))) \
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: ((C) == 'W' ? \
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(GET_CODE (OP) == MEM \
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&& REG_P (XEXP (OP, 0)) \
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&& REG_OK_FOR_BASE_P (XEXP (OP, 0))) \
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: ((C) == 'A' ? \
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(GET_CODE (OP) == MEM \
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&& IS_LO_SUM_DLT_ADDR_P (XEXP (OP, 0))) \
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@ -1336,7 +1345,7 @@ extern int may_call_alloca;
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: ((C) == 'S' ? \
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(GET_CODE (OP) == CONST_INT && INTVAL (OP) == 31) \
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: ((C) == 'U' ? \
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(GET_CODE (OP) == CONST_INT && INTVAL (OP) == 63) : 0))))))
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(GET_CODE (OP) == CONST_INT && INTVAL (OP) == 63) : 0)))))))
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/* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
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@ -2102,7 +2111,8 @@ forget_section (void) \
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CONST_DOUBLE}}, \
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{"move_dest_operand", {SUBREG, REG, MEM}}, \
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{"move_src_operand", {SUBREG, REG, CONST_INT, MEM}}, \
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{"prefetch_operand", {MEM}}, \
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{"prefetch_cc_operand", {MEM}}, \
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{"prefetch_nocc_operand", {MEM}}, \
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{"reg_or_cint_move_operand", {SUBREG, REG, CONST_INT}}, \
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{"pic_label_operand", {LABEL_REF, CONST}}, \
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{"fp_reg_operand", {REG}}, \
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@ -9283,134 +9283,88 @@ add,l %2,%3,%3\;bv,n %%r0(%3)"
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(match_operand 2 "const_int_operand" "")]
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"TARGET_PA_20"
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{
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/* The PA 2.0 prefetch instructions only support short displacements
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when a cache control completer needs to be supplied. Thus, we
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can't use LO_SUM DLT addresses with the spatial locality completer. */
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if (operands[2] == const0_rtx && IS_LO_SUM_DLT_ADDR_P (operands[0]))
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FAIL;
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int locality = INTVAL (operands[2]);
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/* We change operand0 to a MEM as we don't have the infrastructure to
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output all the supported address modes for ldw/ldd but we do have
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it for MEMs. */
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operands[0] = gen_rtx_MEM (Pmode, operands[0]);
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if (locality < 0 || locality > 3)
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abort ();
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if (!TARGET_NO_SPACE_REGS
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&& !cse_not_expected
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&& GET_CODE (XEXP (operands[0], 0)) == PLUS
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&& REG_P (XEXP (XEXP (operands[0], 0), 0))
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&& REG_P (XEXP (XEXP (operands[0], 0), 1)))
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operands[0]
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= replace_equiv_address (operands[0],
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copy_to_mode_reg (Pmode,
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XEXP (operands[0], 0)));
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/* Change operand[0] to a MEM as we don't have the infrastructure
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to output all the supported address modes for ldw/ldd when we use
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the address directly. However, we do have it for MEMs. */
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operands[0] = gen_rtx_MEM (QImode, operands[0]);
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if (TARGET_64BIT)
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emit_insn (gen_prefetch_64 (operands[0], operands[1], operands[2]));
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/* If the address isn't valid for the prefetch, replace it. */
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if (locality)
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{
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if (!prefetch_nocc_operand (operands[0], QImode))
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operands[0]
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= replace_equiv_address (operands[0],
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copy_to_mode_reg (Pmode,
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XEXP (operands[0], 0)));
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emit_insn (gen_prefetch_nocc (operands[0], operands[1], operands[2]));
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}
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else
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emit_insn (gen_prefetch_32 (operands[0], operands[1], operands[2]));
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{
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if (!prefetch_cc_operand (operands[0], QImode))
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operands[0]
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= replace_equiv_address (operands[0],
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copy_to_mode_reg (Pmode,
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XEXP (operands[0], 0)));
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emit_insn (gen_prefetch_cc (operands[0], operands[1], operands[2]));
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}
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DONE;
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})
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(define_insn "prefetch_64"
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[(prefetch (match_operand:DI 0 "prefetch_operand" "A,RQ")
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(match_operand:DI 1 "const_int_operand" "n,n")
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(match_operand:DI 2 "const_int_operand" "n,n"))]
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"TARGET_64BIT
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&& (operands[2] != const0_rtx
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|| GET_CODE (XEXP (operands[0], 0)) != PLUS
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|| GET_CODE (XEXP (XEXP (operands[0], 0), 1)) != CONST_INT
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|| INT_5_BITS (XEXP (XEXP (operands[0], 0), 1)))"
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(define_insn "prefetch_cc"
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[(prefetch (match_operand:QI 0 "prefetch_cc_operand" "RW")
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(match_operand:SI 1 "const_int_operand" "n")
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(match_operand:SI 2 "const_int_operand" "n"))]
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"TARGET_PA_20 && operands[2] == const0_rtx"
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{
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/* The SL completor indicates good spatial locality but poor temporal
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locality. The ldw instruction with a target of general register 0
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prefetches a cache line for a read. The ldd instruction prefetches
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a cache line for a write. */
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static const char * const instr[2][2][2] = {
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{
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{
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"",
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"ldw RT'%A0,%%r0",
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},
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{
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"",
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"ldd RT'%A0,%%r0",
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},
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},
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{
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{
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"ldw%M0,sl %0,%%r0",
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"ldw%M0 %0,%%r0",
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},
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{
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"ldd%M0,sl %0,%%r0",
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"ldd%M0 %0,%%r0",
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}
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}
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/* The SL cache-control completor indicates good spatial locality but
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poor temporal locality. The ldw instruction with a target of general
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register 0 prefetches a cache line for a read. The ldd instruction
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prefetches a cache line for a write. */
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static const char * const instr[2] = {
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"ldw%M0,sl %0,%%r0",
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"ldd%M0,sl %0,%%r0"
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};
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int read_or_write = INTVAL (operands[1]);
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int locality = INTVAL (operands[2]);
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if ((which_alternative != 0 && which_alternative != 1)
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|| (read_or_write != 0 && read_or_write != 1)
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|| (locality < 0 || locality > 3))
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if (read_or_write < 0 || read_or_write > 1)
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abort ();
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if (which_alternative == 0 && locality == 0)
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abort ();
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return instr [which_alternative][read_or_write][locality == 0 ? 0 : 1];
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return instr [read_or_write];
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}
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[(set_attr "type" "load")
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(set_attr "length" "4")])
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(define_insn "prefetch_32"
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[(prefetch (match_operand:SI 0 "prefetch_operand" "A,RQ")
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(define_insn "prefetch_nocc"
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[(prefetch (match_operand:QI 0 "prefetch_nocc_operand" "A,RQ")
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(match_operand:SI 1 "const_int_operand" "n,n")
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(match_operand:SI 2 "const_int_operand" "n,n"))]
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"TARGET_PA_20
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&& (operands[2] != const0_rtx
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|| GET_CODE (XEXP (operands[0], 0)) != PLUS
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|| GET_CODE (XEXP (XEXP (operands[0], 0), 1)) != CONST_INT
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|| INT_5_BITS (XEXP (XEXP (operands[0], 0), 1)))"
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"TARGET_PA_20 && operands[2] != const0_rtx"
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{
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/* The SL completor indicates good spatial locality but poor temporal
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locality. The ldw instruction with a target of general register 0
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prefetches a cache line for a read. The ldd instruction prefetches
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a cache line for a write. */
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static const char * const instr[2][2][2] = {
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/* The ldw instruction with a target of general register 0 prefetches
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a cache line for a read. The ldd instruction prefetches a cache line
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for a write. */
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static const char * const instr[2][2] = {
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{
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{
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"",
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"ldw RT'%A0,%%r0",
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},
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{
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"",
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"ldd RT'%A0,%%r0",
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},
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"ldw RT'%A0,%%r0",
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"ldd RT'%A0,%%r0",
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},
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{
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{
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"ldw%M0,sl %0,%%r0",
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"ldw%M0 %0,%%r0",
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},
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{
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"ldd%M0,sl %0,%%r0",
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"ldd%M0 %0,%%r0",
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}
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"ldw%M0 %0,%%r0",
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"ldd%M0 %0,%%r0",
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}
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};
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int read_or_write = INTVAL (operands[1]);
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int locality = INTVAL (operands[2]);
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if ((which_alternative != 0 && which_alternative != 1)
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|| (read_or_write != 0 && read_or_write != 1)
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|| (locality < 0 || locality > 3))
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|| (read_or_write < 0 || read_or_write > 1))
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abort ();
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if (which_alternative == 0 && locality == 0)
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abort ();
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return instr [which_alternative][read_or_write][locality == 0 ? 0 : 1];
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return instr [which_alternative][read_or_write];
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}
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[(set_attr "type" "load")
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(set_attr "length" "4")])
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