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pa.md: Disparage copies between general and floating-point registers in 32-bit move...

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* pa.md: Disparage copies between general and floating-point registers
	in 32-bit move patterns.

From-SVN: r109788
This commit is contained in:
John David Anglin 2006-01-17 00:24:11 +00:00 committed by John David Anglin
parent ee62fc6e35
commit 2d6ae5d626
2 changed files with 15 additions and 10 deletions
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5
gcc/ChangeLog
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@ -1,3 +1,8 @@
2006-01-16 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
* pa.md: Disparage copies between general and floating-point registers
in 32-bit move patterns.
2006-01-16 H.J. Lu <hongjiu.lu@intel.com>
PR testsuite/25741

20
gcc/config/pa/pa.md
View File

@ -2307,9 +2307,9 @@
(define_insn ""
[(set (match_operand:SI 0 "move_dest_operand"
"=r,r,r,r,r,r,Q,!*q,!r,!*f,*f,T,r,f")
"=r,r,r,r,r,r,Q,!*q,!r,!*f,*f,T,!r,!f")
(match_operand:SI 1 "move_src_operand"
"A,r,J,N,K,RQ,rM,!rM,!*q,!*fM,RT,*f,f,r"))]
"A,r,J,N,K,RQ,rM,!rM,!*q,!*fM,RT,*f,!f,!r"))]
"(register_operand (operands[0], SImode)
|| reg_or_0_operand (operands[1], SImode))
&& !TARGET_SOFT_FLOAT
@ -3869,9 +3869,9 @@
(define_insn ""
[(set (match_operand:DF 0 "move_dest_operand"
"=f,*r,Q,?o,?Q,f,*r,*r,r,f")
"=f,*r,Q,?o,?Q,f,*r,*r,!r,!f")
(match_operand:DF 1 "reg_or_0_or_nonsymb_mem_operand"
"fG,*rG,f,*r,*r,RQ,o,RQ,f,r"))]
"fG,*rG,f,*r,*r,RQ,o,RQ,!f,!r"))]
"(register_operand (operands[0], DFmode)
|| reg_or_0_operand (operands[1], DFmode))
&& !(GET_CODE (operands[1]) == CONST_DOUBLE
@ -4043,9 +4043,9 @@
(define_insn ""
[(set (match_operand:DF 0 "move_dest_operand"
"=r,?o,?Q,r,r,r,f")
"=r,?o,?Q,r,r,!r,!f")
(match_operand:DF 1 "reg_or_0_or_nonsymb_mem_operand"
"rG,r,r,o,RQ,f,r"))]
"rG,r,r,o,RQ,!f,!r"))]
"(register_operand (operands[0], DFmode)
|| reg_or_0_operand (operands[1], DFmode))
&& !TARGET_64BIT
@ -4185,9 +4185,9 @@
(define_insn ""
[(set (match_operand:DI 0 "move_dest_operand"
"=r,o,Q,r,r,r,*f,*f,T,r,f")
"=r,o,Q,r,r,r,*f,*f,T,!r,!f")
(match_operand:DI 1 "general_operand"
"rM,r,r,o*R,Q,i,*fM,RT,*f,f,r"))]
"rM,r,r,o*R,Q,i,*fM,RT,*f,!f,!r"))]
"(register_operand (operands[0], DImode)
|| reg_or_0_operand (operands[1], DImode))
&& !TARGET_64BIT
@ -4414,9 +4414,9 @@
(define_insn ""
[(set (match_operand:SF 0 "move_dest_operand"
"=f,!*r,f,*r,Q,Q,r,f")
"=f,!*r,f,*r,Q,Q,!r,!f")
(match_operand:SF 1 "reg_or_0_or_nonsymb_mem_operand"
"fG,!*rG,RQ,RQ,f,*rG,f,r"))]
"fG,!*rG,RQ,RQ,f,*rG,!f,!r"))]
"(register_operand (operands[0], SFmode)
|| reg_or_0_operand (operands[1], SFmode))
&& !TARGET_SOFT_FLOAT