From 2d6d0eb56cf88ed6845bb8b6e15ea030cec74b7c Mon Sep 17 00:00:00 2001 From: Michael Hayes Date: Mon, 26 Jan 2004 03:36:07 +0000 Subject: [PATCH] c4x.md (addqi3_noclobber): Move up pecking order. * config/c4x/c4x.md (addqi3_noclobber): Move up pecking order. (floatunsqihf2): Remove operand 6. (fixhfqi_set, fix_trunchfqi2, fixuns_trunchfqi2): Group with other fix patterns. (ldi_conditional, ldf_conditional): Validate operands. From-SVN: r76618 --- gcc/ChangeLog | 8 ++ gcc/config/c4x/c4x.md | 230 +++++++++++++++++++++--------------------- 2 files changed, 125 insertions(+), 113 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index a4f3b43c322..feb30c86f6b 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,11 @@ +2004-01-26 Michael Hayes + + * config/c4x/c4x.md (addqi3_noclobber): Move up pecking order. + (floatunsqihf2): Remove operand 6. + (fixhfqi_set, fix_trunchfqi2, fixuns_trunchfqi2): Group with other + fix patterns. + (ldi_conditional, ldf_conditional): Validate operands. + 2004-01-26 Michael Hayes * config/c4x/c4x.h (BCT_CHECK_LOOP_ITERATIONS): Remove. diff --git a/gcc/config/c4x/c4x.md b/gcc/config/c4x/c4x.md index cf3cf7a0341..c15ded3526a 100644 --- a/gcc/config/c4x/c4x.md +++ b/gcc/config/c4x/c4x.md @@ -185,7 +185,7 @@ ; copied about, then we could store the CC in a pseudo register and ; use constructs such as (clobber (match_scratch:CC N "&y,X")) to ; indicate that the 'y' class (ST register) is clobbered for the -; first combination of operands, but not with the second. +; first combination of operands but not with the second. ; I tried this approach for a while but reload got unhappy since I ; didn't allow it to move the CC around. @@ -872,7 +872,7 @@ (const_int 1) (const_int 0))] (const_int 0))) -; With the C3x, things are simpler, but slower, i.e. more pipeline conflicts :( +; With the C3x, things are simpler but slower, i.e. more pipeline conflicts :( ; There are three functional groups: ; (1) AR0-AR7, IR0-IR1, BK ; (2) DP @@ -1787,6 +1787,23 @@ DONE; }") +; This pattern is required primarily for manipulating the stack pointer +; where GCC doesn't expect CC to be clobbered or for calculating +; addresses during reload. Since this is a more specific pattern +; it needs to go first (otherwise we get into problems trying to decide +; to add clobbers). +(define_insn "addqi3_noclobber" + [(set (match_operand:QI 0 "std_reg_operand" "=c,c,c") + (plus:QI (match_operand:QI 1 "src_operand" "%0,rR,rS<>") + (match_operand:QI 2 "src_operand" "rIm,JR,rS<>")))] + "valid_operands (PLUS, operands, QImode)" + "@ + addi\\t%2,%0 + addi3\\t%2,%1,%0 + addi3\\t%2,%1,%0" + [(set_attr "type" "binary,binary,binary")]) +; Default to int16 data attr. + (define_insn "*addqi3_clobber" [(set (match_operand:QI 0 "reg_operand" "=d,d,?d,c,c,?c") (plus:QI (match_operand:QI 1 "src_operand" "%0,rR,rS<>,0,rR,rS<>") @@ -1870,21 +1887,6 @@ [(set_attr "type" "binarycc,binarycc,binarycc")]) ; Default to int16 data attr. -; This pattern is required primarily for manipulating the stack pointer -; where GCC doesn't expect CC to be clobbered or for calculating -; addresses during reload. -(define_insn "addqi3_noclobber" - [(set (match_operand:QI 0 "std_reg_operand" "=c,c,c") - (plus:QI (match_operand:QI 1 "src_operand" "%0,rR,rS<>") - (match_operand:QI 2 "src_operand" "rIm,JR,rS<>")))] - "valid_operands (PLUS, operands, QImode)" - "@ - addi\\t%2,%0 - addi3\\t%2,%1,%0 - addi3\\t%2,%1,%0" - [(set_attr "type" "binary,binary,binary")]) -; Default to int16 data attr. - ; This pattern is required during reload when eliminate_regs_in_insn ; effectively converts a move insn into an add insn when the src @@ -3708,19 +3710,18 @@ (match_dup 3))) (set (match_dup 4) (float:QF (match_dup 1)))]) - (set (match_dup 6) + (set (match_dup 2) (if_then_else:QF (lt (reg:CC 21) (const_int 0)) (match_dup 5) (match_dup 2))) (parallel [(set (match_operand:QF 0 "reg_operand" "") - (plus:QF (match_dup 6) (match_dup 4))) + (plus:QF (match_dup 2) (match_dup 4))) (clobber (reg:CC_NOOV 21))])] "" "operands[2] = gen_reg_rtx (QFmode); operands[3] = CONST0_RTX (QFmode); operands[4] = gen_reg_rtx (QFmode); operands[5] = gen_reg_rtx (QFmode); - operands[6] = gen_reg_rtx (QFmode); emit_move_insn (operands[5], CONST_DOUBLE_ATOF (\"4294967296.0\", QFmode));") (define_expand "floatunsqihf2" @@ -3730,19 +3731,18 @@ (match_dup 3))) (set (match_dup 4) (float:HF (match_dup 1)))]) - (set (match_dup 6) + (set (match_dup 2) (if_then_else:HF (lt (reg:CC 21) (const_int 0)) (match_dup 5) (match_dup 2))) (parallel [(set (match_operand:HF 0 "reg_operand" "") - (plus:HF (match_dup 6) (match_dup 4))) + (plus:HF (match_dup 2) (match_dup 4))) (clobber (reg:CC_NOOV 21))])] "" "operands[2] = gen_reg_rtx (HFmode); operands[3] = CONST0_RTX (HFmode); operands[4] = gen_reg_rtx (HFmode); operands[5] = gen_reg_rtx (HFmode); - operands[6] = gen_reg_rtx (HFmode); emit_move_insn (operands[5], CONST_DOUBLE_ATOF (\"4294967296.0\", HFmode));") (define_insn "floatqihf2" @@ -3784,16 +3784,6 @@ "fix\\t%1,%0" [(set_attr "type" "unarycc")]) -(define_insn "*fixhfqi_set" - [(set (reg:CC 21) - (compare:CC (fix:QI (match_operand:HF 1 "src_operand" "fH")) - (const_int 0))) - (set (match_operand:QI 0 "ext_reg_operand" "=d") - (fix:QI (match_dup 1)))] - "" - "fix\\t%1,%0" - [(set_attr "type" "unarycc")]) - ; ; The C[34]x fix instruction implements a floor, not a straight trunc, ; so we have to invert the number, fix it, and reinvert it if negative @@ -3826,34 +3816,6 @@ operands[5] = gen_reg_rtx (QImode); ") -(define_expand "fix_trunchfqi2" - [(parallel [(set (match_dup 2) - (fix:QI (match_operand:HF 1 "src_operand" ""))) - (clobber (reg:CC 21))]) - (parallel [(set (match_dup 3) (neg:HF (match_dup 1))) - (clobber (reg:CC_NOOV 21))]) - (parallel [(set (match_dup 4) (fix:QI (match_dup 3))) - (clobber (reg:CC 21))]) - (parallel [(set (reg:CC_NOOV 21) - (compare:CC_NOOV (neg:QI (match_dup 4)) (const_int 0))) - (set (match_dup 5) (neg:QI (match_dup 4)))]) - (set (match_dup 2) - (if_then_else:QI (le (reg:CC 21) (const_int 0)) - (match_dup 5) - (match_dup 2))) - (set (match_operand:QI 0 "reg_operand" "=r") (match_dup 2))] - "" - "if (TARGET_FAST_FIX) - { - emit_insn (gen_fixhfqi_clobber (operands[0], operands[1])); - DONE; - } - operands[2] = gen_reg_rtx (QImode); - operands[3] = gen_reg_rtx (HFmode); - operands[4] = gen_reg_rtx (QImode); - operands[5] = gen_reg_rtx (QImode); - ") - (define_expand "fix_truncqfhi2" [(parallel [(set (match_operand:HI 0 "reg_operand" "") (fix:HI (match_operand:QF 1 "src_operand" ""))) @@ -3884,28 +3846,6 @@ operands[5] = gen_reg_rtx (QFmode); emit_move_insn (operands[5], CONST_DOUBLE_ATOF (\"4294967296.0\", QFmode));") -(define_expand "fixuns_trunchfqi2" - [(parallel [(set (match_dup 2) - (fix:QI (match_operand:HF 1 "src_operand" "hH"))) - (clobber (reg:CC 21))]) - (parallel [(set (match_dup 3) - (minus:HF (match_dup 1) (match_dup 5))) - (clobber (reg:CC_NOOV 21))]) - (parallel [(set (reg:CC 21) - (compare:CC (fix:QI (match_dup 3)) - (const_int 0))) - (set (match_dup 4) - (fix:QI (match_dup 3)))]) - (parallel [(set (match_dup 4) (unspec:QI [(match_dup 2)] UNSPEC_LDIV)) - (use (reg:CC 21))]) - (set (match_operand:QI 0 "reg_operand" "=r") (match_dup 4))] - "" - "operands[2] = gen_reg_rtx (QImode); - operands[3] = gen_reg_rtx (HFmode); - operands[4] = gen_reg_rtx (QImode); - operands[5] = gen_reg_rtx (HFmode); - emit_move_insn (operands[5], CONST_DOUBLE_ATOF (\"4294967296.0\", HFmode));") - (define_expand "fixuns_truncqfhi2" [(parallel [(set (match_operand:HI 0 "reg_operand" "") (unsigned_fix:HI (match_operand:QF 1 "src_operand" ""))) @@ -4262,7 +4202,7 @@ [(reg:CC 21) (const_int 0)]) (match_operand:QI 2 "src_operand" "rIm,0") (match_operand:QI 3 "src_operand" "0,rIm")))] - "" + "valid_operands (IF_THEN_ELSE, operands, QImode)" "@ ldi%1\\t%2,%0 ldi%I1\\t%3,%0" @@ -4277,7 +4217,8 @@ "GET_CODE (operands[1]) != LE && GET_CODE (operands[1]) != GE && GET_CODE (operands[1]) != LT - && GET_CODE (operands[1]) != GT" + && GET_CODE (operands[1]) != GT + && valid_operands (IF_THEN_ELSE, operands, QImode)" "@ ldi%1\\t%2,%0 ldi%I1\\t%3,%0" @@ -4318,7 +4259,7 @@ [(reg:CC 21) (const_int 0)]) (match_operand:QF 2 "src_operand" "fHm,0") (match_operand:QF 3 "src_operand" "0,fHm")))] - "" + "valid_operands (IF_THEN_ELSE, operands, QFmode)" "@ ldf%1\\t%2,%0 ldf%I1\\t%3,%0" @@ -4333,7 +4274,8 @@ "GET_CODE (operands[1]) != LE && GET_CODE (operands[1]) != GE && GET_CODE (operands[1]) != LT - && GET_CODE (operands[1]) != GT" + && GET_CODE (operands[1]) != GT + && valid_operands (IF_THEN_ELSE, operands, QFmode)" "@ ldf%1\\t%2,%0 ldf%I1\\t%3,%0" @@ -5634,10 +5576,6 @@ DONE; ") -; The current low overhead looping code is naff and is not failsafe -; If you want RTPB instructions to be generated, apply the patches -; from www.elec.canterbury.ac.nz/c4x. This will utilize the -; doloop_begin and doloop_end patterns in this MD. (define_expand "decrement_and_branch_on_count" [(parallel [(set (pc) (if_then_else (ge (match_operand:QI 0 "register_operand" "") @@ -5734,7 +5672,7 @@ if (len < 8) { for (i = 1; i < len; i++) - { + { output_asm_insn (\"sti\\t%4,*%0++\", operands); output_asm_insn (\"|| ldi\\t*%1++,%4\", operands); } @@ -5753,7 +5691,7 @@ output_asm_insn (\"rptb\\t$+1\", operands); output_asm_insn (\"sti\\t%4,*%0++\", operands); output_asm_insn (\"|| ldi\\t*%1++,%4\", operands); - } + } } return \"sti\\t%4,*%0++\"; }" @@ -5779,8 +5717,15 @@ operands[0] = copy_to_mode_reg (Pmode, XEXP (operands[0], 0)); operands[1] = copy_to_mode_reg (Pmode, XEXP (operands[1], 0)); tmp = gen_reg_rtx (QImode); - emit_insn (gen_movstrqi_large (operands[0], operands[1], operands[2], - operands[3], tmp)); + /* Disabled because of reload problems. */ + if (0 && INTVAL (operands[2]) < 8) + emit_insn (gen_movstrqi_small (operands[0], operands[1], operands[2], + operands[3], tmp)); + else + { + emit_insn (gen_movstrqi_large (operands[0], operands[1], operands[2], + operands[3], tmp)); + } DONE; }") @@ -6024,6 +5969,66 @@ ; ; FIX ; +(define_expand "fixuns_trunchfqi2" + [(parallel [(set (match_dup 2) + (fix:QI (match_operand:HF 1 "reg_or_const_operand" "hH"))) + (clobber (reg:CC 21))]) + (parallel [(set (match_dup 3) + (minus:HF (match_dup 1) (match_dup 5))) + (clobber (reg:CC_NOOV 21))]) + (parallel [(set (reg:CC 21) + (compare:CC (fix:QI (match_dup 3)) + (const_int 0))) + (set (match_dup 4) + (fix:QI (match_dup 3)))]) + (parallel [(set (match_dup 4) (unspec:QI [(match_dup 2)] UNSPEC_LDIV)) + (use (reg:CC 21))]) + (set (match_operand:QI 0 "reg_operand" "=r") (match_dup 4))] + "" + "operands[2] = gen_reg_rtx (QImode); + operands[3] = gen_reg_rtx (HFmode); + operands[4] = gen_reg_rtx (QImode); + operands[5] = gen_reg_rtx (HFmode); + emit_move_insn (operands[5], CONST_DOUBLE_ATOF (\"4294967296.0\", HFmode));") + +(define_expand "fix_trunchfqi2" + [(parallel [(set (match_dup 2) + (fix:QI (match_operand:HF 1 "reg_or_const_operand" ""))) + (clobber (reg:CC 21))]) + (parallel [(set (match_dup 3) (neg:HF (match_dup 1))) + (clobber (reg:CC_NOOV 21))]) + (parallel [(set (match_dup 4) (fix:QI (match_dup 3))) + (clobber (reg:CC 21))]) + (parallel [(set (reg:CC_NOOV 21) + (compare:CC_NOOV (neg:QI (match_dup 4)) (const_int 0))) + (set (match_dup 5) (neg:QI (match_dup 4)))]) + (set (match_dup 2) + (if_then_else:QI (le (reg:CC 21) (const_int 0)) + (match_dup 5) + (match_dup 2))) + (set (match_operand:QI 0 "reg_operand" "=r") (match_dup 2))] + "" + "if (TARGET_FAST_FIX) + { + emit_insn (gen_fixhfqi_clobber (operands[0], operands[1])); + DONE; + } + operands[2] = gen_reg_rtx (QImode); + operands[3] = gen_reg_rtx (HFmode); + operands[4] = gen_reg_rtx (QImode); + operands[5] = gen_reg_rtx (QImode); + ") + +(define_insn "*fixhfqi_set" + [(set (reg:CC 21) + (compare:CC (fix:QI (match_operand:HF 1 "reg_or_const_operand" "hH")) + (const_int 0))) + (set (match_operand:QI 0 "ext_reg_operand" "=d") + (fix:QI (match_dup 1)))] + "" + "fix\\t%1,%0" + [(set_attr "type" "unarycc")]) + (define_insn "fixhfqi_clobber" [(set (match_operand:QI 0 "reg_operand" "=dc") (fix:QI (match_operand:HF 1 "reg_or_const_operand" "hH"))) @@ -6032,6 +6037,23 @@ "fix\\t%1,%0" [(set_attr "type" "unarycc")]) +(define_expand "fix_trunchfhi2" + [(parallel [(set (match_operand:HI 0 "reg_operand" "") + (fix:HI (match_operand:HF 1 "reg_operand" ""))) + (clobber (reg:CC 21))])] + "" + "c4x_emit_libcall (fix_trunchfhi2_libfunc, FIX, HImode, HFmode, 2, operands); + DONE;") + +(define_expand "fixuns_trunchfhi2" + [(parallel [(set (match_operand:HI 0 "reg_operand" "") + (unsigned_fix:HI (match_operand:HF 1 "reg_operand" ""))) + (clobber (reg:CC 21))])] + "" + "c4x_emit_libcall (fixuns_trunchfhi2_libfunc, UNSIGNED_FIX, + HImode, HFmode, 2, operands); + DONE;") + ; ; ABSF ; @@ -6185,24 +6207,6 @@ "emit_insn (gen_sqrthf2_inline (operands[0], operands[1])); DONE;") - -(define_expand "fix_trunchfhi2" - [(parallel [(set (match_operand:HI 0 "reg_operand" "") - (fix:HI (match_operand:HF 1 "reg_operand" ""))) - (clobber (reg:CC 21))])] - "" - "c4x_emit_libcall (fix_trunchfhi2_libfunc, FIX, HImode, HFmode, 2, operands); - DONE;") - -(define_expand "fixuns_trunchfhi2" - [(parallel [(set (match_operand:HI 0 "reg_operand" "") - (unsigned_fix:HI (match_operand:HF 1 "reg_operand" ""))) - (clobber (reg:CC 21))])] - "" - "c4x_emit_libcall (fixuns_trunchfhi2_libfunc, UNSIGNED_FIX, - HImode, HFmode, 2, operands); - DONE;") - ; ; THREE OPERAND LONG DOUBLE INSTRUCTIONS ;