rl78.c (register_sizes): Make the "upper half" of %fp 2 to keep registers after it properly word-aligned.
* config/rl78/rl78.c (register_sizes): Make the "upper half" of %fp 2 to keep registers after it properly word-aligned. (rl78_alloc_physical_registers_umul): Handle the case where both input operands are the same. Co-Authored-By: DJ Delorie <dj@redhat.com> From-SVN: r207308
This commit is contained in:
Nick Clifton
Nick Clifton
parent
c972624e48
commit
2d70f6d435
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@ -1,3 +1,11 @@
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2014-01-30 Nick Clifton <nickc@redhat.com>
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DJ Delorie <dj@redhat.com>
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* config/rl78/rl78.c (register_sizes): Make the "upper half" of
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%fp 2 to keep registers after it properly word-aligned.
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(rl78_alloc_physical_registers_umul): Handle the case where both
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input operands are the same.
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2014-01-30 Richard Biener <rguenther@suse.de>
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PR tree-optimization/59903
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@ -327,13 +327,15 @@ rl78_option_override (void)
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}
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/* Most registers are 8 bits. Some are 16 bits because, for example,
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gcc doesn't like dealing with $FP as a register pair. This table
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maps register numbers to size in bytes. */
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gcc doesn't like dealing with $FP as a register pair (the second
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half of $fp is also 2 to keep reload happy wrt register pairs, but
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no register class includes it). This table maps register numbers
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to size in bytes. */
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static const int register_sizes[] =
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{
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1, 1, 1, 1, 1, 1, 1, 1,
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1, 1, 1, 1, 1, 1, 1, 1,
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1, 1, 1, 1, 1, 1, 2, 1,
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1, 1, 1, 1, 1, 1, 2, 2,
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1, 1, 1, 1, 1, 1, 1, 1,
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2, 2, 1, 1, 1
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};
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@ -381,7 +383,7 @@ rl78_hard_regno_mode_ok (int regno, enum machine_mode mode)
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/* These are not to be used by gcc. */
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if (regno == 23 || regno == ES_REG || regno == CS_REG)
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return 0;
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/* $fp can alway sbe accessed as a 16-bit value. */
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/* $fp can always be accessed as a 16-bit value. */
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if (regno == FP_REG && s == 2)
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return 1;
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if (regno < SP_REG)
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@ -659,10 +661,10 @@ is_brk_interrupt_func (const_tree decl)
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/* Check "interrupt" attributes. */
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static tree
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rl78_handle_func_attribute (tree * node,
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tree name,
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tree args,
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int flags ATTRIBUTE_UNUSED,
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bool * no_add_attrs)
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tree name,
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tree args,
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int flags ATTRIBUTE_UNUSED,
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bool * no_add_attrs)
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{
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gcc_assert (DECL_P (* node));
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gcc_assert (args == NULL_TREE);
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@ -820,14 +822,14 @@ rl78_far_p (rtx x)
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if (! MEM_P (x))
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return 0;
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#if DEBUG0
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fprintf (stderr, "\033[35mrl78_far_p: "); debug_rtx(x);
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fprintf (stderr, "\033[35mrl78_far_p: "); debug_rtx (x);
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fprintf (stderr, " = %d\033[0m\n", MEM_ADDR_SPACE (x) == ADDR_SPACE_FAR);
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#endif
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return MEM_ADDR_SPACE (x) == ADDR_SPACE_FAR;
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}
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/* Return the appropriate mode for a named address pointer. */
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#undef TARGET_ADDR_SPACE_POINTER_MODE
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#undef TARGET_ADDR_SPACE_POINTER_MODE
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#define TARGET_ADDR_SPACE_POINTER_MODE rl78_addr_space_pointer_mode
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static enum machine_mode
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rl78_addr_space_pointer_mode (addr_space_t addrspace)
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@ -844,7 +846,7 @@ rl78_addr_space_pointer_mode (addr_space_t addrspace)
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}
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/* Returns TRUE for valid addresses. */
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#undef TARGET_VALID_POINTER_MODE
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#undef TARGET_VALID_POINTER_MODE
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#define TARGET_VALID_POINTER_MODE rl78_valid_pointer_mode
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static bool
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rl78_valid_pointer_mode (enum machine_mode m)
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@ -853,7 +855,7 @@ rl78_valid_pointer_mode (enum machine_mode m)
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}
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/* Return the appropriate mode for a named address address. */
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#undef TARGET_ADDR_SPACE_ADDRESS_MODE
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#undef TARGET_ADDR_SPACE_ADDRESS_MODE
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#define TARGET_ADDR_SPACE_ADDRESS_MODE rl78_addr_space_address_mode
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static enum machine_mode
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rl78_addr_space_address_mode (addr_space_t addrspace)
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@ -1796,7 +1798,7 @@ rl78_peep_movhi_p (rtx *operands)
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{
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#if DEBUG_PEEP
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fprintf (stderr, "no peep: wrong mem %d\n", i);
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debug_rtx(m);
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debug_rtx (m);
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debug_rtx (operands[i+2]);
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#endif
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return false;
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@ -1832,7 +1834,7 @@ rl78_setup_peep_movhi (rtx *operands)
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break;
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case CONST_INT:
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operands[i+4] = GEN_INT ((INTVAL (operands[i]) & 0xff) + ((char)INTVAL (operands[i+2])) * 256);
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operands[i+4] = GEN_INT ((INTVAL (operands[i]) & 0xff) + ((char) INTVAL (operands[i+2])) * 256);
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break;
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case MEM:
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@ -2031,7 +2033,7 @@ update_content (unsigned char index, unsigned char val, enum machine_mode mode)
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else
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fprintf (dump_file, "%s and vice versa\n", get_content_name (val, mode));
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}
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if (mode == HImode)
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{
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val = val == NOT_KNOWN ? val : val + 1;
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@ -2054,7 +2056,7 @@ update_content (unsigned char index, unsigned char val, enum machine_mode mode)
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++ i;
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continue;
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}
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if (content_memory[i] == index
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|| (val != NOT_KNOWN && content_memory[i] == val))
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{
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@ -2269,7 +2271,7 @@ EM2 (int line ATTRIBUTE_UNUSED, rtx r)
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{
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#if DEBUG_ALLOC
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fprintf (stderr, "\033[36m%d: ", line);
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debug_rtx(r);
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debug_rtx (r);
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fprintf (stderr, "\033[0m");
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#endif
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/*SCHED_GROUP_P (r) = 1;*/
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@ -2363,7 +2365,7 @@ gen_and_emit_move (rtx to, rtx from, rtx where, bool before)
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else
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{
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rtx move = mode == QImode ? gen_movqi (to, from) : gen_movhi (to, from);
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EM (move);
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if (where == NULL_RTX)
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@ -2521,7 +2523,7 @@ force_into_acc (rtx src, rtx before)
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return;
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move = mode == QImode ? gen_movqi (A, src) : gen_movhi (AX, src);
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EM (move);
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emit_insn_before (move, before);
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@ -2683,7 +2685,7 @@ has_constraint (unsigned int opnum, enum constraint_num constraint)
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/* No constraints means anything is accepted. */
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if (p == NULL || *p == 0 || *p == ',')
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return true;
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do
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{
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char c;
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@ -2750,7 +2752,7 @@ rl78_alloc_physical_registers_op2 (rtx insn)
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}
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/* Make a note of whether (H)L is being used. It matters
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because if OP (2) alsoneeds reloading, then we must take
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because if OP (2) also needs reloading, then we must take
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care not to corrupt HL. */
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hl_used = reg_mentioned_p (L, OP (0)) || reg_mentioned_p (L, OP (1));
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@ -2764,7 +2766,7 @@ rl78_alloc_physical_registers_op2 (rtx insn)
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/* If op0 is a Ws1 type memory address then switching the base
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address register to HL might allow us to perform an in-memory
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operation. (eg for the INCW instruction).
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FIXME: Adding the move into HL is costly if this optimization is not
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going to work, so for now, make sure that we know that the new insn will
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match the requirements of the addhi3_real pattern. Really we ought to
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@ -2786,7 +2788,7 @@ rl78_alloc_physical_registers_op2 (rtx insn)
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newbase = gen_and_emit_move (HL, base, insn, true);
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record_content (newbase, NULL_RTX);
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newbase = gen_rtx_PLUS (HImode, newbase, addend);
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OP (0) = OP (1) = change_address (OP (0), VOIDmode, newbase);
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/* We do not want to fail here as this means that
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@ -2817,7 +2819,7 @@ rl78_alloc_physical_registers_op2 (rtx insn)
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record_content (HL, NULL_RTX);
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newbase = gen_rtx_PLUS (HImode, HL, addend);
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OP (2) = change_address (OP (2), VOIDmode, newbase);
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/* We do not want to fail here as this means that
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@ -2857,7 +2859,7 @@ rl78_alloc_physical_registers_op2 (rtx insn)
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;
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OP (2) = hl_used ? move_to_de (2, first) : move_to_hl (2, first);
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MUST_BE_OK (insn);
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}
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@ -2923,7 +2925,7 @@ rl78_alloc_physical_registers_cmp (rtx insn)
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default:
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gcc_unreachable ();
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}
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if (GET_CODE (cmp) == EQ || GET_CODE (cmp) == NE)
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PATTERN (insn) = gen_cbranchhi4_real (cmp, OP (2), OP (1), OP (3));
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else
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@ -2939,7 +2941,7 @@ rl78_alloc_physical_registers_cmp (rtx insn)
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OP (1) = OP (2) = BC;
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MUST_BE_OK (insn);
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}
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tmp_id = get_max_insn_count ();
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saved_op1 = OP (1);
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@ -2967,7 +2969,7 @@ rl78_alloc_physical_registers_cmp (rtx insn)
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MUST_BE_OK (insn);
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}
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/* Like op2, but AX = A op X. */
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/* Like op2, but AX = A * X. */
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static void
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rl78_alloc_physical_registers_umul (rtx insn)
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{
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@ -2996,8 +2998,18 @@ rl78_alloc_physical_registers_umul (rtx insn)
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tmp_id = get_max_insn_count ();
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saved_op1 = OP (1);
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OP (1) = move_to_acc (1, insn);
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if (rtx_equal_p (OP (1), OP (2)))
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{
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gcc_assert (GET_MODE (OP (2)) == QImode);
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/* The MULU instruction does not support duplicate arguments
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but we know that if we copy OP (2) to X it will do so via
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A and thus OP (1) will already be loaded into A. */
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OP (2) = move_to_x (2, insn);
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OP (1) = A;
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}
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else
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OP (1) = move_to_acc (1, insn);
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MAYBE_OK (insn);
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@ -3129,7 +3141,7 @@ rl78_alloc_physical_registers (void)
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{
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if (LABEL_P (insn))
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clear_content_memory ();
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continue;
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}
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