Removed unused functions.
Changed call_address_operand() to only accept symbolic addresses. From-SVN: r19070
This commit is contained in:
Nick Clifton
Nick Clifton
parent
5a5732cf8c
commit
2e076ddffc
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@ -1,3 +1,12 @@
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Thu Apr 9 16:53:59 1998 Nick Clifton <nickc@cygnus.com>
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* config/m32r/m32r.c: call_address_operand(): Only accept symbolic
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addresses.
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symbolic_memort_operand(), call32_operand(), int8_operand(),
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int16_operand(), uint24_operand(), reg_or_int8_operand(): Removed.
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Not used.
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uint16_operand(): Made static.
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Thu Apr 9 01:43:04 1998 Jeffrey A Law (law@cygnus.com)
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* calls.c (expand_call): Fix typo.
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@ -1,4 +1,4 @@
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/* Subroutines used for code generation on the M32R/D cpu.
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/* Subroutines used for code generation on the Mitsubishi M32R cpu.
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Copyright (C) 1996, 1997 Free Software Foundation, Inc.
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This file is part of GNU CC.
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@ -18,8 +18,8 @@ along with GNU CC; see the file COPYING. If not, write to
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the Free Software Foundation, 59 Temple Place - Suite 330,
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Boston, MA 02111-1307, USA. */
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#include <stdio.h>
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#include "config.h"
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#include <stdio.h>
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#include "tree.h"
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#include "rtl.h"
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#include "regs.h"
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@ -416,9 +416,10 @@ call_address_operand (op, mode)
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rtx op;
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enum machine_mode mode;
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{
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return (symbolic_operand (op, mode)
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|| (GET_CODE (op) == CONST_INT && LEGITIMATE_CONSTANT_P (op))
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|| (GET_CODE (op) == REG));
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return symbolic_operand (op, mode);
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/* Constants and values in registers are not OK, because
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the m32r BL instruction can only support PC relative branching. */
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}
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int
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@ -450,23 +451,6 @@ symbolic_operand (op, mode)
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}
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}
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/* Return truth value of statement that OP is a symbolic memory
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operand of mode MODE. */
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int
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symbolic_memory_operand (op, mode)
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rtx op;
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enum machine_mode mode;
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{
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if (GET_CODE (op) == SUBREG)
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op = SUBREG_REG (op);
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if (GET_CODE (op) != MEM)
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return 0;
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op = XEXP (op, 0);
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return (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == CONST
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|| GET_CODE (op) == LABEL_REF);
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}
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/* Return 1 if OP is a reference to an object in .sdata/.sbss. */
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int
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@ -561,16 +545,6 @@ call26_operand (op, mode)
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return TARGET_CALL26;
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}
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/* Return 1 if OP is a function that must be called with 32 bit addressing. */
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int
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call32_operand (op, mode)
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rtx op;
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enum machine_mode mode;
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{
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return ! call26_operand (op, mode);
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}
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/* Returns 1 if OP is an acceptable operand for seth/add3. */
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int
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@ -592,30 +566,6 @@ seth_add3_operand (op, mode)
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return 0;
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}
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/* Return true if OP is a signed 8 bit immediate value. */
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int
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int8_operand (op, mode)
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rtx op;
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enum machine_mode mode;
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{
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if (GET_CODE (op) != CONST_INT)
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return 0;
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return INT8_P (INTVAL (op));
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}
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/* Return true if OP is a signed 16 bit immediate value. */
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int
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int16_operand (op, mode)
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rtx op;
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enum machine_mode mode;
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{
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if (GET_CODE (op) != CONST_INT)
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return 0;
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return INT16_P (INTVAL (op));
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}
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/* Return true if OP is a signed 16 bit immediate value
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useful in comparisons. */
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@ -631,7 +581,7 @@ cmp_int16_operand (op, mode)
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/* Return true if OP is an unsigned 16 bit immediate value. */
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int
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static int
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uint16_operand (op, mode)
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rtx op;
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enum machine_mode mode;
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@ -641,32 +591,6 @@ uint16_operand (op, mode)
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return UINT16_P (INTVAL (op));
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}
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/* Return true if OP is an unsigned 24 bit immediate value. */
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int
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uint24_operand (op, mode)
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rtx op;
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enum machine_mode mode;
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{
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if (GET_CODE (op) != CONST_INT)
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return 0;
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return UINT24_P (INTVAL (op));
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}
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/* Return true if OP is a register or signed 8 bit value. */
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int
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reg_or_int8_operand (op, mode)
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rtx op;
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enum machine_mode mode;
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{
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if (GET_CODE (op) == REG || GET_CODE (op) == SUBREG)
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return register_operand (op, mode);
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if (GET_CODE (op) != CONST_INT)
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return 0;
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return INT8_P (INTVAL (op));
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}
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/* Return true if OP is a register or signed 8 bit value. */
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int
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@ -681,7 +605,7 @@ reg_or_int16_operand (op, mode)
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return INT16_P (INTVAL (op));
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}
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/* Return true if OP is a register or signed 8 bit value. */
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/* Return true if OP is a register or an unsigned 16 bit value. */
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int
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reg_or_uint16_operand (op, mode)
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@ -937,24 +861,26 @@ m32r_select_cc_mode (op, x, y)
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rtx
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gen_compare (code, x, y)
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enum rtx_code code;
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rtx x, y;
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rtx x;
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rtx y;
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{
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enum machine_mode mode = SELECT_CC_MODE (code, x, y);
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enum rtx_code compare_code, branch_code;
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rtx cc_reg = gen_rtx (REG, mode, CARRY_REGNUM);
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int swap_p = 0;
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enum rtx_code compare_code;
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enum rtx_code branch_code;
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enum machine_mode mode = SELECT_CC_MODE (code, x, y);
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rtx cc_reg = gen_rtx (REG, mode, CARRY_REGNUM);
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int must_swap = 0;
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switch (code)
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{
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case EQ: compare_code = EQ; branch_code = NE; break;
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case NE: compare_code = EQ; branch_code = EQ; break;
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case LT: compare_code = LT; branch_code = NE; break;
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case LE: compare_code = LT; branch_code = EQ; swap_p = 1; break;
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case GT: compare_code = LT; branch_code = NE; swap_p = 1; break;
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case GE: compare_code = LT; branch_code = EQ; break;
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case EQ: compare_code = EQ; branch_code = NE; break;
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case NE: compare_code = EQ; branch_code = EQ; break;
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case LT: compare_code = LT; branch_code = NE; break;
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case LE: compare_code = LT; branch_code = EQ; must_swap = 1; break;
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case GT: compare_code = LT; branch_code = NE; must_swap = 1; break;
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case GE: compare_code = LT; branch_code = EQ; break;
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case LTU: compare_code = LTU; branch_code = NE; break;
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case LEU: compare_code = LTU; branch_code = EQ; swap_p = 1; break;
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case GTU: compare_code = LTU; branch_code = NE; swap_p = 1; break;
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case LEU: compare_code = LTU; branch_code = EQ; must_swap = 1; break;
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case GTU: compare_code = LTU; branch_code = NE; must_swap = 1; break;
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case GEU: compare_code = LTU; branch_code = EQ; break;
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}
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@ -964,10 +890,12 @@ gen_compare (code, x, y)
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if (compare_code == EQ
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&& register_operand (y, SImode))
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return gen_rtx (code, mode, x, y);
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/* reg/zero signed comparison */
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if ((compare_code == EQ || compare_code == LT)
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&& y == const0_rtx)
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return gen_rtx (code, mode, x, y);
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/* reg/smallconst equal comparison */
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if (compare_code == EQ
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&& GET_CODE (y) == CONST_INT
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@ -977,6 +905,7 @@ gen_compare (code, x, y)
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emit_insn (gen_cmp_ne_small_const_insn (tmp, x, y));
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return gen_rtx (code, mode, tmp, const0_rtx);
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}
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/* reg/const equal comparison */
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if (compare_code == EQ
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&& CONSTANT_P (y))
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@ -986,28 +915,32 @@ gen_compare (code, x, y)
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}
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}
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if (swap_p && CONSTANT_P (y))
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y = force_reg (GET_MODE (x), y);
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else if (CONSTANT_P (y))
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if (CONSTANT_P (y))
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{
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int ok_const_p =
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(code == LTU || code == LEU || code == GTU || code == GEU)
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? uint16_operand (y, GET_MODE (y))
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: reg_or_cmp_int16_operand (y, GET_MODE (y));
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if (! ok_const_p)
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if (must_swap)
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y = force_reg (GET_MODE (x), y);
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else
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{
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int ok_const =
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(code == LTU || code == LEU || code == GTU || code == GEU)
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? uint16_operand (y, GET_MODE (y))
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: reg_or_cmp_int16_operand (y, GET_MODE (y));
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if (! ok_const)
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y = force_reg (GET_MODE (x), y);
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}
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}
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switch (compare_code)
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{
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case EQ :
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emit_insn (gen_cmp_eqsi_insn (swap_p ? y : x, swap_p ? x : y));
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emit_insn (gen_cmp_eqsi_insn (must_swap ? y : x, must_swap ? x : y));
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break;
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case LT :
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emit_insn (gen_cmp_ltsi_insn (swap_p ? y : x, swap_p ? x : y));
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emit_insn (gen_cmp_ltsi_insn (must_swap ? y : x, must_swap ? x : y));
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break;
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case LTU :
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emit_insn (gen_cmp_ltusi_insn (swap_p ? y : x, swap_p ? x : y));
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emit_insn (gen_cmp_ltusi_insn (must_swap ? y : x, must_swap ? x : y));
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break;
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}
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@ -1289,8 +1222,8 @@ m32r_compute_frame_size (size)
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void
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m32r_output_function_prologue (file, size)
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FILE *file;
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int size;
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FILE * file;
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int size;
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{
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int regno;
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int total_size, frame_size;
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@ -1388,8 +1321,8 @@ m32r_output_function_prologue (file, size)
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void
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m32r_output_function_epilogue (file, size)
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FILE *file;
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int size;
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FILE * file;
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int size;
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{
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int regno;
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int noepilogue = FALSE;
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@ -1423,8 +1356,8 @@ m32r_output_function_epilogue (file, size)
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unsigned int args_size = current_frame_info.args_size;
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unsigned int gmask = current_frame_info.gmask;
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int can_trust_sp_p = !current_function_calls_alloca;
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char *sp_str = reg_names[STACK_POINTER_REGNUM];
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char *fp_str = reg_names[FRAME_POINTER_REGNUM];
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char * sp_str = reg_names[STACK_POINTER_REGNUM];
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char * fp_str = reg_names[FRAME_POINTER_REGNUM];
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/* The first thing to do is point the sp at the bottom of the register
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save area. */
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@ -1525,7 +1458,7 @@ m32r_initialize_trampoline (tramp, fnaddr, cxt)
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void
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m32r_asm_file_start (file)
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FILE *file;
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FILE * file;
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{
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if (flag_verbose_asm)
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fprintf (file, "%s M32R/D special options: -G %d\n",
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@ -1538,9 +1471,9 @@ m32r_asm_file_start (file)
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void
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m32r_print_operand (file, x, code)
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FILE *file;
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rtx x;
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int code;
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FILE * file;
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rtx x;
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int code;
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{
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switch (code)
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{
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@ -1655,7 +1588,7 @@ m32r_print_operand (file, x, code)
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break;
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case 'U' :
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/* FIXME: wip */
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/* ??? wip */
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/* Output a load/store with update indicator if appropriate. */
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if (GET_CODE (x) == MEM)
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{
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@ -1750,11 +1683,12 @@ m32r_print_operand (file, x, code)
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void
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m32r_print_operand_address (file, addr)
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FILE *file;
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rtx addr;
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FILE * file;
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rtx addr;
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{
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register rtx base, index = 0;
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int offset = 0;
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register rtx base;
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register rtx index = 0;
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int offset = 0;
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switch (GET_CODE (addr))
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{
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