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or1k: Fix code quality for volatile memory loads 

Volatile memory does not match the memory_operand predicate.  This
causes extra extend/mask instructions instructions when reading
from volatile memory.  On OpenRISC loading volatile memory can be
treated the same as regular memory loads which supports combined
sign/zero extends.  Fixing this eliminates the need for extra
extend/mask instructions.

This also adds a test provided by Richard Selvaggi which uncovered the
issue while we were looking into another issue.

gcc/ChangeLog:

	PR target/90363
	* config/or1k/or1k.md (zero_extend<mode>si2): Update predicate.
	(extend<mode>si2): Update predicate.
	* gcc/config/or1k/predicates.md (volatile_mem_operand): New.
	(reg_or_mem_operand): New.

gcc/testsuite/ChangeLog:

	PR target/90363
	* gcc.target/or1k/swap-1.c: New test.
	* gcc.target/or1k/swap-2.c: New test.

From-SVN: r273647
This commit is contained in:
Stafford Horne 2019-07-21 20:58:54 +00:00 committed by Stafford Horne
parent 48df93911a
commit 2e92185a03
4 changed files with 35 additions and 3 deletions
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8
gcc/ChangeLog
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@ -1,3 +1,11 @@
2019-07-22 Stafford Horne <shorne@gmail.com>
PR target/90363
* config/or1k/or1k.md (zero_extend<mode>si2): Update predicate.
(extend<mode>si2): Update predicate.
* gcc/config/or1k/predicates.md (volatile_mem_operand): New.
(reg_or_mem_operand): New.
2019-07-21 Iain Sandoe <iain@sandoe.co.uk>
* config/rs6000/rs6000.c (TARGET_NO_PROTOTYPE): Move from here...

6
gcc/config/or1k/or1k.md
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@ -328,11 +328,11 @@
;; Sign Extending
;; -------------------------------------------------------------------------
;; Zero extension can always be done with AND and an extending load.
;; Zero extension can always be done with AND or an extending load.
(define_insn "zero_extend<mode>si2"
[(set (match_operand:SI 0 "register_operand" "=r,r")
(zero_extend:SI (match_operand:I12 1 "nonimmediate_operand" "r,m")))]
(zero_extend:SI (match_operand:I12 1 "reg_or_mem_operand" "r,m")))]
""
"@
l.andi\t%0, %1, <zext_andi>
@ -344,7 +344,7 @@
(define_insn "extend<mode>si2"
[(set (match_operand:SI 0 "register_operand" "=r,r")
(sign_extend:SI (match_operand:I12 1 "nonimmediate_operand" "r,m")))]
(sign_extend:SI (match_operand:I12 1 "reg_or_mem_operand" "r,m")))]
"TARGET_SEXT"
"@
l.ext<ldst>s\t%0, %1

18
gcc/config/or1k/predicates.md
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@ -82,3 +82,21 @@
(define_predicate "equality_comparison_operator"
(match_code "ne,eq"))
;; Borrowed from rs6000
;; Return true if the operand is in volatile memory. Note that during the
;; RTL generation phase, memory_operand does not return TRUE for volatile
;; memory references. So this function allows us to recognize volatile
;; references where it's safe.
(define_predicate "volatile_mem_operand"
(and (match_code "mem")
(match_test "MEM_VOLATILE_P (op)")
(if_then_else (match_test "reload_completed")
(match_operand 0 "memory_operand")
(match_test "memory_address_p (mode, XEXP (op, 0))"))))
;; Return true if the operand is a register or memory; including volatile
;; memory.
(define_predicate "reg_or_mem_operand"
(ior (match_operand 0 "nonimmediate_operand")
(match_operand 0 "volatile_mem_operand")))

6
gcc/testsuite/ChangeLog
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@ -1,3 +1,9 @@
2019-07-22 Stafford Horne <shorne@gmail.com>
PR target/90363
* gcc.target/or1k/swap-1.c: New test.
* gcc.target/or1k/swap-2.c: New test.
2019-07-20 Segher Boessenkool <segher@kernel.crashing.org>
* gcc.target/powerpc/volatile-mem.c: New testcase.