i386.md (*movti_internal): Merge from *movti_internal_rex64 and *movti_internal_sse.
* config/i386/i386.md (*movti_internal): Merge from *movti_internal_rex64 and *movti_internal_sse. Use x64 isa attribute. (*movdi_internal): Merge with *movdi_internal_rex64. Use x64 and nox64 isa attributes. From-SVN: r196784
This commit is contained in:
Uros Bizjak
Uros Bizjak
parent
6e55eda727
commit
2eac0476ce
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@ -1,3 +1,10 @@
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2013-03-19 Uros Bizjak <ubizjak@gmail.com>
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* config/i386/i386.md (*movti_internal): Merge from
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*movti_internal_rex64 and *movti_internal_sse. Use x64 isa attribute.
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(*movdi_internal): Merge with *movdi_internal_rex64. Use x64 and
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nox64 isa attributes.
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2013-03-18 Richard Biener <rguenther@suse.de>
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* tree-ssa-structalias.c (find): Use gcc_checking_assert.
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@ -1656,6 +1656,40 @@
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;; Move instructions.
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;; Reload patterns to support multi-word load/store
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;; with non-offsetable address.
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(define_expand "reload_noff_store"
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[(parallel [(match_operand 0 "memory_operand" "=m")
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(match_operand 1 "register_operand" "r")
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(match_operand:DI 2 "register_operand" "=&r")])]
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"TARGET_64BIT"
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{
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rtx mem = operands[0];
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rtx addr = XEXP (mem, 0);
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emit_move_insn (operands[2], addr);
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mem = replace_equiv_address_nv (mem, operands[2]);
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emit_insn (gen_rtx_SET (VOIDmode, mem, operands[1]));
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DONE;
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})
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(define_expand "reload_noff_load"
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[(parallel [(match_operand 0 "register_operand" "=r")
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(match_operand 1 "memory_operand" "m")
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(match_operand:DI 2 "register_operand" "=r")])]
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"TARGET_64BIT"
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{
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rtx mem = operands[1];
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rtx addr = XEXP (mem, 0);
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emit_move_insn (operands[2], addr);
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mem = replace_equiv_address_nv (mem, operands[2]);
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emit_insn (gen_rtx_SET (VOIDmode, operands[0], mem));
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DONE;
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})
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(define_expand "movoi"
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[(set (match_operand:OI 0 "nonimmediate_operand")
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(match_operand:OI 1 "general_operand"))]
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@ -1760,10 +1794,11 @@
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]
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(const_string "OI")))])
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(define_insn "*movti_internal_rex64"
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(define_insn "*movti_internal"
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[(set (match_operand:TI 0 "nonimmediate_operand" "=!r ,o ,x,x ,m")
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(match_operand:TI 1 "general_operand" "riFo,re,C,xm,x"))]
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"TARGET_64BIT && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
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"(TARGET_64BIT || TARGET_SSE)
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&& !(MEM_P (operands[0]) && MEM_P (operands[1]))"
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{
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switch (which_alternative)
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{
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@ -1795,12 +1830,14 @@
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gcc_unreachable ();
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}
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}
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[(set_attr "type" "*,*,sselog1,ssemov,ssemov")
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[(set_attr "isa" "x64,x64,*,*,*")
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(set_attr "type" "*,*,sselog1,ssemov,ssemov")
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(set_attr "prefix" "*,*,maybe_vex,maybe_vex,maybe_vex")
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(set (attr "mode")
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(cond [(eq_attr "alternative" "0,1")
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(const_string "DI")
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(match_test "TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL")
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(ior (not (match_test "TARGET_SSE2"))
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(match_test "TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL"))
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(const_string "V4SF")
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(and (eq_attr "alternative" "4")
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(match_test "TARGET_SSE_TYPELESS_STORES"))
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@ -1820,81 +1857,20 @@
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[(const_int 0)]
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"ix86_split_long_move (operands); DONE;")
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(define_insn "*movti_internal_sse"
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[(set (match_operand:TI 0 "nonimmediate_operand" "=x,x ,m")
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(match_operand:TI 1 "vector_move_operand" "C ,xm,x"))]
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"TARGET_SSE && !TARGET_64BIT
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&& !(MEM_P (operands[0]) && MEM_P (operands[1]))"
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{
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switch (which_alternative)
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{
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case 0:
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return standard_sse_constant_opcode (insn, operands[1]);
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case 1:
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case 2:
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/* TDmode values are passed as TImode on the stack. Moving them
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to stack may result in unaligned memory access. */
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if (misaligned_operand (operands[0], TImode)
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|| misaligned_operand (operands[1], TImode))
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{
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if (get_attr_mode (insn) == MODE_V4SF)
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return "%vmovups\t{%1, %0|%0, %1}";
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else
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return "%vmovdqu\t{%1, %0|%0, %1}";
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}
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else
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{
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if (get_attr_mode (insn) == MODE_V4SF)
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return "%vmovaps\t{%1, %0|%0, %1}";
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else
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return "%vmovdqa\t{%1, %0|%0, %1}";
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}
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default:
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gcc_unreachable ();
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}
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}
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[(set_attr "type" "sselog1,ssemov,ssemov")
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(set_attr "prefix" "maybe_vex")
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(set (attr "mode")
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(cond [(match_test "TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL")
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(const_string "V4SF")
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(and (eq_attr "alternative" "2")
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(match_test "TARGET_SSE_TYPELESS_STORES"))
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(const_string "V4SF")
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(match_test "TARGET_AVX")
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(const_string "TI")
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(ior (not (match_test "TARGET_SSE2"))
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(match_test "optimize_function_for_size_p (cfun)"))
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(const_string "V4SF")
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]
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(const_string "TI")))])
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(define_insn "*movdi_internal_rex64"
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(define_insn "*movdi_internal"
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[(set (match_operand:DI 0 "nonimmediate_operand"
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"=r,r ,r,m ,*y,m*y,?*y,?r ,?*Ym,*x,m ,*x,*x,?r ,?*Yi,?*x,?*Ym")
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"=r ,o ,r,r ,r,m ,*y,m*y,*y,?*y,?r ,?*Ym,*x,m ,*x,*x,?r ,?*Yi,?*x,?*Ym")
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(match_operand:DI 1 "general_operand"
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"Z ,rem,i,re,C ,*y ,m ,*Ym,r ,C ,*x,*x,m ,*Yi,r ,*Ym,*x"))]
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"TARGET_64BIT && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
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"riFo,riF,Z,rem,i,re,C ,*y ,m ,m ,*Ym,r ,C ,*x,*x,m ,*Yi,r ,*Ym,*x"))]
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"!(MEM_P (operands[0]) && MEM_P (operands[1]))"
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{
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switch (get_attr_type (insn))
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{
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case TYPE_SSECVT:
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if (SSE_REG_P (operands[0]))
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return "movq2dq\t{%1, %0|%0, %1}";
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else
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return "movdq2q\t{%1, %0|%0, %1}";
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case TYPE_MULTI:
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return "#";
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case TYPE_SSEMOV:
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if (get_attr_mode (insn) == MODE_V4SF)
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return "%vmovaps\t{%1, %0|%0, %1}";
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else if (get_attr_mode (insn) == MODE_TI)
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return "%vmovdqa\t{%1, %0|%0, %1}";
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/* Handle broken assemblers that require movd instead of movq. */
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if (GENERAL_REG_P (operands[0]) || GENERAL_REG_P (operands[1]))
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return "%vmovd\t{%1, %0|%0, %1}";
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else
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return "%vmovq\t{%1, %0|%0, %1}";
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case TYPE_MMX:
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return "pxor\t%0, %0";
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case TYPE_MMXMOV:
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/* Handle broken assemblers that require movd instead of movq. */
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@ -1906,8 +1882,27 @@
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case TYPE_SSELOG1:
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return standard_sse_constant_opcode (insn, operands[1]);
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case TYPE_MMX:
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return "pxor\t%0, %0";
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case TYPE_SSEMOV:
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switch (get_attr_mode (insn))
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{
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case MODE_DI:
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return "%vmovq\t{%1, %0|%0, %1}";
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case MODE_TI:
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return "%vmovdqa\t{%1, %0|%0, %1}";
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case MODE_V4SF:
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return "%vmovaps\t{%1, %0|%0, %1}";
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case MODE_V2SF:
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gcc_assert (!TARGET_AVX);
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return "movlps\t{%1, %0|%0, %1}";
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default:
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gcc_unreachable ();
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}
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case TYPE_SSECVT:
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if (SSE_REG_P (operands[0]))
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return "movq2dq\t{%1, %0|%0, %1}";
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else
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return "movdq2q\t{%1, %0|%0, %1}";
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case TYPE_LEA:
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return "lea{q}\t{%E1, %0|%0, %E1}";
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@ -1916,7 +1911,7 @@
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gcc_assert (!flag_pic || LEGITIMATE_PIC_OPERAND_P (operands[1]));
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if (get_attr_mode (insn) == MODE_SI)
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return "mov{l}\t{%k1, %k0|%k0, %k1}";
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else if (which_alternative == 2)
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else if (which_alternative == 4)
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return "movabs{q}\t{%1, %0|%0, %1}";
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else if (ix86_use_lea_for_mov (insn, operands))
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return "lea{q}\t{%E1, %0|%0, %E1}";
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@ -1924,16 +1919,27 @@
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return "mov{q}\t{%1, %0|%0, %1}";
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}
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}
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[(set (attr "type")
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(cond [(eq_attr "alternative" "4")
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[(set (attr "isa")
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(cond [(eq_attr "alternative" "0,1,8")
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(const_string "nox64")
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(eq_attr "alternative" "2,3,4,5,9,10,11,16,17")
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(const_string "x64")
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(eq_attr "alternative" "18,19")
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(const_string "sse2")
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]
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(const_string "*")))
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(set (attr "type")
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(cond [(eq_attr "alternative" "0,1")
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(const_string "multi")
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(eq_attr "alternative" "6")
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(const_string "mmx")
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(eq_attr "alternative" "5,6,7,8")
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(eq_attr "alternative" "7,8,9,10,11")
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(const_string "mmxmov")
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(eq_attr "alternative" "9")
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(eq_attr "alternative" "12")
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(const_string "sselog1")
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(eq_attr "alternative" "10,11,12,13,14")
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(eq_attr "alternative" "13,14,15,16,17")
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(const_string "ssemov")
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(eq_attr "alternative" "15,16")
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(eq_attr "alternative" "18,19")
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(const_string "ssecvt")
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(match_operand 1 "pic_32bit_operand")
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(const_string "lea")
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@ -1941,159 +1947,43 @@
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(const_string "imov")))
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(set (attr "modrm")
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(if_then_else
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(and (eq_attr "alternative" "2") (eq_attr "type" "imov"))
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(and (eq_attr "alternative" "4") (eq_attr "type" "imov"))
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(const_string "0")
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(const_string "*")))
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(set (attr "length_immediate")
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(if_then_else
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(and (eq_attr "alternative" "2") (eq_attr "type" "imov"))
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(and (eq_attr "alternative" "4") (eq_attr "type" "imov"))
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(const_string "8")
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(const_string "*")))
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(set (attr "prefix_rex")
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(if_then_else (eq_attr "alternative" "7,8")
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(if_then_else (eq_attr "alternative" "10,11")
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(const_string "1")
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(const_string "*")))
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(set (attr "prefix")
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(if_then_else (eq_attr "type" "sselog1,ssemov")
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(const_string "maybe_vex")
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(const_string "orig")))
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(set (attr "prefix_data16")
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(if_then_else (eq_attr "alternative" "10")
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(if_then_else (and (eq_attr "type" "ssemov") (eq_attr "mode" "DI"))
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(const_string "1")
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(const_string "*")))
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(set (attr "prefix")
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(if_then_else (eq_attr "alternative" "9,10,11,12,13,14")
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(const_string "maybe_vex")
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(const_string "orig")))
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(set (attr "mode")
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(cond [(eq_attr "alternative" "0")
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(const_string "SI")
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(eq_attr "alternative" "9,11")
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(cond [(match_test "TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL")
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(const_string "V4SF")
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(match_test "TARGET_AVX")
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(const_string "TI")
|
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(match_test "optimize_function_for_size_p (cfun)")
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(const_string "V4SF")
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]
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(const_string "TI"))
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]
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(const_string "DI")))])
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(cond [(eq_attr "alternative" "2")
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(const_string "SI")
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(eq_attr "alternative" "12,14")
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(cond [(ior (not (match_test "TARGET_SSE2"))
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(match_test "TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL"))
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(const_string "V4SF")
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(match_test "TARGET_AVX")
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(const_string "TI")
|
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(match_test "optimize_function_for_size_p (cfun)")
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(const_string "V4SF")
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]
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(const_string "TI"))
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|
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;; Reload patterns to support multi-word load/store
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;; with non-offsetable address.
|
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(define_expand "reload_noff_store"
|
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[(parallel [(match_operand 0 "memory_operand" "=m")
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(match_operand 1 "register_operand" "r")
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(match_operand:DI 2 "register_operand" "=&r")])]
|
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"TARGET_64BIT"
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{
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rtx mem = operands[0];
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rtx addr = XEXP (mem, 0);
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emit_move_insn (operands[2], addr);
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mem = replace_equiv_address_nv (mem, operands[2]);
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emit_insn (gen_rtx_SET (VOIDmode, mem, operands[1]));
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DONE;
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})
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|
||||
(define_expand "reload_noff_load"
|
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[(parallel [(match_operand 0 "register_operand" "=r")
|
||||
(match_operand 1 "memory_operand" "m")
|
||||
(match_operand:DI 2 "register_operand" "=r")])]
|
||||
"TARGET_64BIT"
|
||||
{
|
||||
rtx mem = operands[1];
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||||
rtx addr = XEXP (mem, 0);
|
||||
|
||||
emit_move_insn (operands[2], addr);
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mem = replace_equiv_address_nv (mem, operands[2]);
|
||||
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emit_insn (gen_rtx_SET (VOIDmode, operands[0], mem));
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||||
DONE;
|
||||
})
|
||||
|
||||
(define_insn "*movdi_internal"
|
||||
[(set (match_operand:DI 0 "nonimmediate_operand"
|
||||
"=r ,o ,*y,m*y,*y,*x,m ,*x,*x,*x,m ,*x,*x,?*x,?*Ym")
|
||||
(match_operand:DI 1 "general_operand"
|
||||
"riFo,riF,C ,*y ,m ,C ,*x,*x,m ,C ,*x,*x,m ,*Ym,*x"))]
|
||||
"!TARGET_64BIT && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
|
||||
{
|
||||
switch (get_attr_type (insn))
|
||||
{
|
||||
case TYPE_SSECVT:
|
||||
if (SSE_REG_P (operands[0]))
|
||||
return "movq2dq\t{%1, %0|%0, %1}";
|
||||
else
|
||||
return "movdq2q\t{%1, %0|%0, %1}";
|
||||
|
||||
case TYPE_SSEMOV:
|
||||
switch (get_attr_mode (insn))
|
||||
{
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||||
case MODE_TI:
|
||||
return "%vmovdqa\t{%1, %0|%0, %1}";
|
||||
case MODE_DI:
|
||||
return "%vmovq\t{%1, %0|%0, %1}";
|
||||
case MODE_V4SF:
|
||||
return "%vmovaps\t{%1, %0|%0, %1}";
|
||||
case MODE_V2SF:
|
||||
return "movlps\t{%1, %0|%0, %1}";
|
||||
default:
|
||||
gcc_unreachable ();
|
||||
}
|
||||
|
||||
case TYPE_MMXMOV:
|
||||
return "movq\t{%1, %0|%0, %1}";
|
||||
|
||||
case TYPE_SSELOG1:
|
||||
return standard_sse_constant_opcode (insn, operands[1]);
|
||||
|
||||
case TYPE_MMX:
|
||||
return "pxor\t%0, %0";
|
||||
|
||||
case TYPE_MULTI:
|
||||
return "#";
|
||||
|
||||
default:
|
||||
gcc_unreachable ();
|
||||
}
|
||||
}
|
||||
[(set (attr "isa")
|
||||
(cond [(eq_attr "alternative" "5,6,7,8,13,14")
|
||||
(const_string "sse2")
|
||||
(eq_attr "alternative" "9,10,11,12")
|
||||
(const_string "noavx")
|
||||
]
|
||||
(const_string "*")))
|
||||
(set (attr "type")
|
||||
(cond [(eq_attr "alternative" "0,1")
|
||||
(const_string "multi")
|
||||
(eq_attr "alternative" "2")
|
||||
(const_string "mmx")
|
||||
(eq_attr "alternative" "3,4")
|
||||
(const_string "mmxmov")
|
||||
(eq_attr "alternative" "5,9")
|
||||
(const_string "sselog1")
|
||||
(eq_attr "alternative" "13,14")
|
||||
(const_string "ssecvt")
|
||||
]
|
||||
(const_string "ssemov")))
|
||||
(set (attr "prefix")
|
||||
(if_then_else (eq_attr "alternative" "5,6,7,8")
|
||||
(const_string "maybe_vex")
|
||||
(const_string "orig")))
|
||||
(set (attr "mode")
|
||||
(cond [(eq_attr "alternative" "9,11")
|
||||
(const_string "V4SF")
|
||||
(eq_attr "alternative" "10,12")
|
||||
(const_string "V2SF")
|
||||
(eq_attr "alternative" "5,7")
|
||||
(cond [(match_test "TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL")
|
||||
(const_string "V4SF")
|
||||
(match_test "TARGET_AVX")
|
||||
(const_string "TI")
|
||||
(match_test "optimize_function_for_size_p (cfun)")
|
||||
(const_string "V4SF")
|
||||
]
|
||||
(const_string "TI"))
|
||||
(and (eq_attr "alternative" "13,15")
|
||||
(not (match_test "TARGET_SSE2")))
|
||||
(const_string "V2SF")
|
||||
]
|
||||
(const_string "DI")))])
|
||||
|
||||
|
|
@ -2186,6 +2076,7 @@
|
|||
(const_string "V4SF")
|
||||
]
|
||||
(const_string "TI"))
|
||||
|
||||
(and (eq_attr "alternative" "8,9,10,11")
|
||||
(not (match_test "TARGET_SSE2")))
|
||||
(const_string "SF")
|
||||
|
|
@ -2896,7 +2787,8 @@
|
|||
case MODE_V1DF:
|
||||
return "%vmovlpd\t{%1, %d0|%d0, %1}";
|
||||
case MODE_V2SF:
|
||||
return "%vmovlps\t{%1, %d0|%d0, %1}";
|
||||
gcc_assert (!TARGET_AVX);
|
||||
return "movlps\t{%1, %0|%0, %1}";
|
||||
default:
|
||||
gcc_unreachable ();
|
||||
}
|
||||
|
|
@ -2994,10 +2886,9 @@
|
|||
]
|
||||
(const_string "DF"))
|
||||
|
||||
(eq_attr "alternative" "12,16")
|
||||
(if_then_else (match_test "TARGET_SSE2")
|
||||
(const_string "DF")
|
||||
(const_string "V2SF"))
|
||||
(and (eq_attr "alternative" "12,16")
|
||||
(not (match_test "TARGET_SSE2")))
|
||||
(const_string "V2SF")
|
||||
]
|
||||
(const_string "DF")))])
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue