expr.h (prepare_operand): Move to...
gcc/ 2011-03-21 Richard Sandiford <richard.sandiford@linaro.org> * expr.h (prepare_operand): Move to... * optabs.h (prepare_operand): ...here and change the insn code parameter from "int" to "enum insn_code". (insn_operand_matches): Declare. * expr.c (init_expr_target): Use insn_operand_matches. (compress_float_constant): Likewise. * function.c (safe_insn_predicate, assign_parm_setup_reg): Likewise. * optabs.c (can_compare_p, prepare_cmp_insn): Likewise. (emit_cmp_and_jump_insn_1, gen_add2_insn, gen_add3_insn): Likewise. (have_add2_insn, gen_sub2_insn, gen_sub3_insn, have_sub2_insn): Likewise. (gen_cond_trap): Likewise. (prepare_operand): Likewise. Change icode to an insn_code. (insn_operand_matches): New function. * reload.c (find_reloads_address_1): Use insn_operand_matches. * reload1.c (gen_reload): Likewise. * targhooks.c (default_secondary_reload): Likewise. From-SVN: r171270
This commit is contained in:
Richard Sandiford
Richard Sandiford
parent
9a96da32eb
commit
2ef6ce06d3
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@ -1,3 +1,22 @@
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2011-03-21 Richard Sandiford <richard.sandiford@linaro.org>
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* expr.h (prepare_operand): Move to...
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* optabs.h (prepare_operand): ...here and change the insn code
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parameter from "int" to "enum insn_code".
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(insn_operand_matches): Declare.
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* expr.c (init_expr_target): Use insn_operand_matches.
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(compress_float_constant): Likewise.
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* function.c (safe_insn_predicate, assign_parm_setup_reg): Likewise.
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* optabs.c (can_compare_p, prepare_cmp_insn): Likewise.
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(emit_cmp_and_jump_insn_1, gen_add2_insn, gen_add3_insn): Likewise.
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(have_add2_insn, gen_sub2_insn, gen_sub3_insn, have_sub2_insn): Likewise.
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(gen_cond_trap): Likewise.
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(prepare_operand): Likewise. Change icode to an insn_code.
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(insn_operand_matches): New function.
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* reload.c (find_reloads_address_1): Use insn_operand_matches.
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* reload1.c (gen_reload): Likewise.
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* targhooks.c (default_secondary_reload): Likewise.
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2011-03-21 Uros Bizjak <ubizjak@gmail.com>
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* config/alpha/alpha.md (unspec): New define_c_enum.
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@ -286,7 +286,7 @@ init_expr_target (void)
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PUT_MODE (mem, srcmode);
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if ((*insn_data[ic].operand[1].predicate) (mem, srcmode))
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if (insn_operand_matches (ic, 1, mem))
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float_extend_from_mem[mode][srcmode] = true;
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}
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}
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@ -3446,7 +3446,7 @@ compress_float_constant (rtx x, rtx y)
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{
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/* Skip if the target needs extra instructions to perform
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the extension. */
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if (! (*insn_data[ic].operand[1].predicate) (trunc_y, srcmode))
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if (!insn_operand_matches (ic, 1, trunc_y))
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continue;
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/* This is valid, but may not be cheaper than the original. */
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newcost = rtx_cost (gen_rtx_FLOAT_EXTEND (dstmode, trunc_y), SET, speed);
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@ -173,9 +173,6 @@ extern rtx expand_simple_unop (enum machine_mode, enum rtx_code, rtx, rtx,
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perform the operation described by CODE and MODE. */
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extern int have_insn_for (enum rtx_code, enum machine_mode);
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extern rtx prepare_operand (int, rtx, int, enum machine_mode, enum machine_mode,
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int);
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/* Emit code to make a call to a constant function or a library call. */
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extern void emit_libcall_block (rtx, rtx, rtx, rtx);
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@ -1493,16 +1493,7 @@ instantiate_virtual_regs_in_rtx (rtx *loc, void *data)
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static int
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safe_insn_predicate (int code, int operand, rtx x)
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{
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const struct insn_operand_data *op_data;
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if (code < 0)
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return true;
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op_data = &insn_data[code].operand[operand];
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if (op_data->predicate == NULL)
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return true;
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return op_data->predicate (x, op_data->mode);
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return code < 0 || insn_operand_matches ((enum insn_code) code, operand, x);
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}
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/* A subroutine of instantiate_virtual_regs. Instantiate any virtual
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@ -3013,8 +3004,8 @@ assign_parm_setup_reg (struct assign_parm_data_all *all, tree parm,
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op0 = parmreg;
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op1 = validated_mem;
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if (icode != CODE_FOR_nothing
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&& insn_data[icode].operand[0].predicate (op0, promoted_nominal_mode)
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&& insn_data[icode].operand[1].predicate (op1, data->passed_mode))
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&& insn_operand_matches (icode, 0, op0)
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&& insn_operand_matches (icode, 1, op1))
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{
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enum rtx_code code = unsignedp ? ZERO_EXTEND : SIGN_EXTEND;
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rtx insn, insns;
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107
gcc/optabs.c
107
gcc/optabs.c
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@ -3943,15 +3943,15 @@ can_compare_p (enum rtx_code code, enum machine_mode mode,
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test = gen_rtx_fmt_ee (code, mode, const0_rtx, const0_rtx);
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do
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{
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int icode;
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enum insn_code icode;
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if (purpose == ccp_jump
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&& (icode = optab_handler (cbranch_optab, mode)) != CODE_FOR_nothing
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&& insn_data[icode].operand[0].predicate (test, mode))
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&& insn_operand_matches (icode, 0, test))
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return 1;
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if (purpose == ccp_store_flag
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&& (icode = optab_handler (cstore_optab, mode)) != CODE_FOR_nothing
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&& insn_data[icode].operand[1].predicate (test, mode))
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&& insn_operand_matches (icode, 1, test))
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return 1;
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if (purpose == ccp_cmov
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&& optab_handler (cmov_optab, mode) != CODE_FOR_nothing)
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@ -4112,16 +4112,14 @@ prepare_cmp_insn (rtx x, rtx y, enum rtx_code comparison, rtx size,
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enum insn_code icode;
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icode = optab_handler (cbranch_optab, cmp_mode);
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if (icode != CODE_FOR_nothing
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&& insn_data[icode].operand[0].predicate (test, VOIDmode))
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&& insn_operand_matches (icode, 0, test))
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{
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rtx last = get_last_insn ();
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rtx op0 = prepare_operand (icode, x, 1, mode, cmp_mode, unsignedp);
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rtx op1 = prepare_operand (icode, y, 2, mode, cmp_mode, unsignedp);
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if (op0 && op1
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&& insn_data[icode].operand[1].predicate
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(op0, insn_data[icode].operand[1].mode)
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&& insn_data[icode].operand[2].predicate
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(op1, insn_data[icode].operand[2].mode))
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&& insn_operand_matches (icode, 1, op0)
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&& insn_operand_matches (icode, 2, op1))
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{
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XEXP (test, 0) = op0;
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XEXP (test, 1) = op1;
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@ -4200,18 +4198,17 @@ prepare_cmp_insn (rtx x, rtx y, enum rtx_code comparison, rtx size,
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that it is accepted by the operand predicate. Return the new value. */
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rtx
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prepare_operand (int icode, rtx x, int opnum, enum machine_mode mode,
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prepare_operand (enum insn_code icode, rtx x, int opnum, enum machine_mode mode,
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enum machine_mode wider_mode, int unsignedp)
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{
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if (mode != wider_mode)
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x = convert_modes (wider_mode, mode, x, unsignedp);
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if (!insn_data[icode].operand[opnum].predicate
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(x, insn_data[icode].operand[opnum].mode))
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if (!insn_operand_matches (icode, opnum, x))
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{
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if (reload_completed)
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return NULL_RTX;
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x = copy_to_mode_reg (insn_data[icode].operand[opnum].mode, x);
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x = copy_to_mode_reg (insn_data[(int) icode].operand[opnum].mode, x);
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}
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return x;
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@ -4232,7 +4229,7 @@ emit_cmp_and_jump_insn_1 (rtx test, enum machine_mode mode, rtx label)
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icode = optab_handler (cbranch_optab, optab_mode);
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gcc_assert (icode != CODE_FOR_nothing);
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gcc_assert (insn_data[icode].operand[0].predicate (test, VOIDmode));
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gcc_assert (insn_operand_matches (icode, 0, test));
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emit_jump_insn (GEN_FCN (icode) (test, XEXP (test, 0), XEXP (test, 1), label));
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}
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@ -4699,14 +4696,11 @@ emit_conditional_add (rtx target, enum rtx_code code, rtx op0, rtx op1,
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rtx
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gen_add2_insn (rtx x, rtx y)
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{
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int icode = (int) optab_handler (add_optab, GET_MODE (x));
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enum insn_code icode = optab_handler (add_optab, GET_MODE (x));
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gcc_assert (insn_data[icode].operand[0].predicate
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(x, insn_data[icode].operand[0].mode));
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gcc_assert (insn_data[icode].operand[1].predicate
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(x, insn_data[icode].operand[1].mode));
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gcc_assert (insn_data[icode].operand[2].predicate
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(y, insn_data[icode].operand[2].mode));
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gcc_assert (insn_operand_matches (icode, 0, x));
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gcc_assert (insn_operand_matches (icode, 1, x));
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gcc_assert (insn_operand_matches (icode, 2, y));
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return GEN_FCN (icode) (x, x, y);
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}
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@ -4717,15 +4711,12 @@ gen_add2_insn (rtx x, rtx y)
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rtx
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gen_add3_insn (rtx r0, rtx r1, rtx c)
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{
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int icode = (int) optab_handler (add_optab, GET_MODE (r0));
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enum insn_code icode = optab_handler (add_optab, GET_MODE (r0));
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if (icode == CODE_FOR_nothing
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|| !(insn_data[icode].operand[0].predicate
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(r0, insn_data[icode].operand[0].mode))
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|| !(insn_data[icode].operand[1].predicate
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(r1, insn_data[icode].operand[1].mode))
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|| !(insn_data[icode].operand[2].predicate
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(c, insn_data[icode].operand[2].mode)))
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|| !insn_operand_matches (icode, 0, r0)
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|| !insn_operand_matches (icode, 1, r1)
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|| !insn_operand_matches (icode, 2, c))
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return NULL_RTX;
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return GEN_FCN (icode) (r0, r1, c);
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@ -4734,21 +4725,18 @@ gen_add3_insn (rtx r0, rtx r1, rtx c)
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int
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have_add2_insn (rtx x, rtx y)
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{
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int icode;
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enum insn_code icode;
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gcc_assert (GET_MODE (x) != VOIDmode);
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icode = (int) optab_handler (add_optab, GET_MODE (x));
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icode = optab_handler (add_optab, GET_MODE (x));
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if (icode == CODE_FOR_nothing)
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return 0;
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if (!(insn_data[icode].operand[0].predicate
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(x, insn_data[icode].operand[0].mode))
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|| !(insn_data[icode].operand[1].predicate
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(x, insn_data[icode].operand[1].mode))
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|| !(insn_data[icode].operand[2].predicate
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(y, insn_data[icode].operand[2].mode)))
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if (!insn_operand_matches (icode, 0, x)
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|| !insn_operand_matches (icode, 1, x)
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|| !insn_operand_matches (icode, 2, y))
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return 0;
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return 1;
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@ -4759,14 +4747,11 @@ have_add2_insn (rtx x, rtx y)
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rtx
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gen_sub2_insn (rtx x, rtx y)
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{
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int icode = (int) optab_handler (sub_optab, GET_MODE (x));
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enum insn_code icode = optab_handler (sub_optab, GET_MODE (x));
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gcc_assert (insn_data[icode].operand[0].predicate
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(x, insn_data[icode].operand[0].mode));
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gcc_assert (insn_data[icode].operand[1].predicate
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(x, insn_data[icode].operand[1].mode));
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gcc_assert (insn_data[icode].operand[2].predicate
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(y, insn_data[icode].operand[2].mode));
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gcc_assert (insn_operand_matches (icode, 0, x));
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gcc_assert (insn_operand_matches (icode, 1, x));
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gcc_assert (insn_operand_matches (icode, 2, y));
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return GEN_FCN (icode) (x, x, y);
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}
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@ -4777,15 +4762,12 @@ gen_sub2_insn (rtx x, rtx y)
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rtx
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gen_sub3_insn (rtx r0, rtx r1, rtx c)
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{
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int icode = (int) optab_handler (sub_optab, GET_MODE (r0));
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enum insn_code icode = optab_handler (sub_optab, GET_MODE (r0));
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if (icode == CODE_FOR_nothing
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|| !(insn_data[icode].operand[0].predicate
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(r0, insn_data[icode].operand[0].mode))
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|| !(insn_data[icode].operand[1].predicate
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(r1, insn_data[icode].operand[1].mode))
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|| !(insn_data[icode].operand[2].predicate
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(c, insn_data[icode].operand[2].mode)))
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|| !insn_operand_matches (icode, 0, r0)
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|| !insn_operand_matches (icode, 1, r1)
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|| !insn_operand_matches (icode, 2, c))
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return NULL_RTX;
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return GEN_FCN (icode) (r0, r1, c);
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@ -4794,21 +4776,18 @@ gen_sub3_insn (rtx r0, rtx r1, rtx c)
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int
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have_sub2_insn (rtx x, rtx y)
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{
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int icode;
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enum insn_code icode;
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gcc_assert (GET_MODE (x) != VOIDmode);
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icode = (int) optab_handler (sub_optab, GET_MODE (x));
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icode = optab_handler (sub_optab, GET_MODE (x));
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if (icode == CODE_FOR_nothing)
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return 0;
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if (!(insn_data[icode].operand[0].predicate
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(x, insn_data[icode].operand[0].mode))
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|| !(insn_data[icode].operand[1].predicate
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(x, insn_data[icode].operand[1].mode))
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|| !(insn_data[icode].operand[2].predicate
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(y, insn_data[icode].operand[2].mode)))
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if (!insn_operand_matches (icode, 0, x)
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|| !insn_operand_matches (icode, 1, x)
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|| !insn_operand_matches (icode, 2, y))
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return 0;
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return 1;
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@ -6643,8 +6622,7 @@ gen_cond_trap (enum rtx_code code, rtx op1, rtx op2, rtx tcode)
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return 0;
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/* Some targets only accept a zero trap code. */
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if (insn_data[icode].operand[3].predicate
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&& !insn_data[icode].operand[3].predicate (tcode, VOIDmode))
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if (!insn_operand_matches (icode, 3, tcode))
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return 0;
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do_pending_stack_adjust ();
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@ -7329,5 +7307,16 @@ expand_sync_lock_test_and_set (rtx mem, rtx val, rtx target)
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return NULL_RTX;
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}
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/* Return true if OPERAND is suitable for operand number OPNO of
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instruction ICODE. */
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bool
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insn_operand_matches (enum insn_code icode, unsigned int opno, rtx operand)
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{
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return (!insn_data[(int) icode].operand[opno].predicate
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|| (insn_data[(int) icode].operand[opno].predicate
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(operand, insn_data[(int) icode].operand[opno].mode)));
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}
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#include "gt-optabs.h"
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@ -923,4 +923,10 @@ set_direct_optab_handler (direct_optab op, enum machine_mode mode,
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extern rtx optab_libfunc (optab optab, enum machine_mode mode);
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extern rtx convert_optab_libfunc (convert_optab optab, enum machine_mode mode1,
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enum machine_mode mode2);
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extern bool insn_operand_matches (enum insn_code icode, unsigned int opno,
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rtx operand);
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extern rtx prepare_operand (enum insn_code, rtx, int, enum machine_mode,
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enum machine_mode, int);
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#endif /* GCC_OPTABS_H */
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@ -5819,17 +5819,15 @@ find_reloads_address_1 (enum machine_mode mode, rtx x, int context,
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rtx equiv = (MEM_P (XEXP (x, 0))
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? XEXP (x, 0)
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: reg_equiv_mem[regno]);
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int icode = (int) optab_handler (add_optab, GET_MODE (x));
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enum insn_code icode = optab_handler (add_optab, GET_MODE (x));
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if (insn && NONJUMP_INSN_P (insn) && equiv
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&& memory_operand (equiv, GET_MODE (equiv))
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#ifdef HAVE_cc0
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&& ! sets_cc0_p (PATTERN (insn))
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#endif
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&& ! (icode != CODE_FOR_nothing
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&& ((*insn_data[icode].operand[0].predicate)
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(equiv, GET_MODE (x)))
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&& ((*insn_data[icode].operand[1].predicate)
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(equiv, GET_MODE (x)))))
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&& insn_operand_matches (icode, 0, equiv)
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&& insn_operand_matches (icode, 1, equiv)))
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{
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/* We use the original pseudo for loc, so that
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emit_reload_insns() knows which pseudo this
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|
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@ -8479,7 +8479,7 @@ gen_reload (rtx out, rtx in, int opnum, enum reload_type type)
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not valid than to dummy things up. */
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rtx op0, op1, tem, insn;
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int code;
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enum insn_code code;
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op0 = find_replacement (&XEXP (in, 0));
|
||||
op1 = find_replacement (&XEXP (in, 1));
|
||||
|
|
@ -8517,14 +8517,13 @@ gen_reload (rtx out, rtx in, int opnum, enum reload_type type)
|
|||
DEFINE_PEEPHOLE should be specified that recognizes the sequence
|
||||
we emit below. */
|
||||
|
||||
code = (int) optab_handler (add_optab, GET_MODE (out));
|
||||
code = optab_handler (add_optab, GET_MODE (out));
|
||||
|
||||
if (CONSTANT_P (op1) || MEM_P (op1) || GET_CODE (op1) == SUBREG
|
||||
|| (REG_P (op1)
|
||||
&& REGNO (op1) >= FIRST_PSEUDO_REGISTER)
|
||||
|| (code != CODE_FOR_nothing
|
||||
&& ! ((*insn_data[code].operand[2].predicate)
|
||||
(op1, insn_data[code].operand[2].mode))))
|
||||
&& !insn_operand_matches (code, 2, op1)))
|
||||
tem = op0, op0 = op1, op1 = tem;
|
||||
|
||||
gen_reload (out, op0, opnum, type);
|
||||
|
|
|
|||
|
|
@ -893,8 +893,7 @@ default_secondary_reload (bool in_p ATTRIBUTE_UNUSED, rtx x ATTRIBUTE_UNUSED,
|
|||
reload_mode);
|
||||
|
||||
if (icode != CODE_FOR_nothing
|
||||
&& insn_data[(int) icode].operand[in_p].predicate
|
||||
&& ! insn_data[(int) icode].operand[in_p].predicate (x, reload_mode))
|
||||
&& !insn_operand_matches (icode, in_p, x))
|
||||
icode = CODE_FOR_nothing;
|
||||
else if (icode != CODE_FOR_nothing)
|
||||
{
|
||||
|
|
|
|||
Loading…
Reference in New Issue