re PR target/50447 ([avr] Better support of AND, OR, XOR and PLUS with constant integers for 16- and 32-bit values)
PR target/50447 * config/avr/avr.md (cc): New alternative out_plus_noclobber. (adjust_len): Ditto. (addhi3): Don't pipe through short; use gen_int_mode instead. Prior to reload, expand to gen_addhi3_clobber. (*addhi3): Use avr_out_plus_noclobber if applicable, use out_plus_noclobber in cc and adjust_len attribute. (addhi3_clobber): 2 new RTL peepholes. (addhi3_clobber): New insn. * config/avr/avr-protos.h: (avr_out_plus_noclobber): New prototype. * config/avr/avr.c (avr_out_plus_noclobber): New function. (notice_update_cc): Handle CC_OUT_PLUS_NOCLOBBER. (avr_out_plus_1): Tweak if only MSB is +/-1 and other bytes are 0. Set cc0 to set_zn for adiw on 16-bit values. (adjust_insn_length): Handle ADJUST_LEN_OUT_PLUS_NOCLOBBER. (expand_epilogue): No need to add 0 to frame_pointer_rtx. From-SVN: r180193
This commit is contained in:
Georg-Johann Lay
Georg-Johann Lay
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dd46054a5f
commit
2f47b8d3be
@ -1,3 +1,22 @@
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2011-10-19 Georg-Johann Lay <avr@gjlay.de>
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PR target/50447
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* config/avr/avr.md (cc): New alternative out_plus_noclobber.
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(adjust_len): Ditto.
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(addhi3): Don't pipe through short; use gen_int_mode instead.
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Prior to reload, expand to gen_addhi3_clobber.
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(*addhi3): Use avr_out_plus_noclobber if applicable, use
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out_plus_noclobber in cc and adjust_len attribute.
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(addhi3_clobber): 2 new RTL peepholes.
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(addhi3_clobber): New insn.
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* config/avr/avr-protos.h: (avr_out_plus_noclobber): New prototype.
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* config/avr/avr.c (avr_out_plus_noclobber): New function.
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(notice_update_cc): Handle CC_OUT_PLUS_NOCLOBBER.
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(avr_out_plus_1): Tweak if only MSB is +/-1 and other bytes are 0.
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Set cc0 to set_zn for adiw on 16-bit values.
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(adjust_insn_length): Handle ADJUST_LEN_OUT_PLUS_NOCLOBBER.
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(expand_epilogue): No need to add 0 to frame_pointer_rtx.
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2011-10-19 Richard Guenther <rguenther@suse.de>
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PR middle-end/50780
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@ -83,6 +83,7 @@ extern void avr_output_addr_vec_elt (FILE *stream, int value);
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extern const char *avr_out_sbxx_branch (rtx insn, rtx operands[]);
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extern const char* avr_out_bitop (rtx, rtx*, int*);
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extern const char* avr_out_plus (rtx*, int*, int*);
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extern const char* avr_out_plus_noclobber (rtx*, int*, int*);
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extern const char* avr_out_addto_sp (rtx*, int*);
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extern bool avr_popcount_each_byte (rtx, int, int);
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@ -1051,9 +1051,10 @@ expand_epilogue (bool sibcall_p)
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if (frame_pointer_needed)
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{
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/* Get rid of frame. */
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emit_move_insn(frame_pointer_rtx,
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gen_rtx_PLUS (HImode, frame_pointer_rtx,
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gen_int_mode (size, HImode)));
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if (size)
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emit_move_insn (frame_pointer_rtx,
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gen_rtx_PLUS (HImode, frame_pointer_rtx,
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gen_int_mode (size, HImode)));
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}
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else
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{
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@ -1682,14 +1683,19 @@ notice_update_cc (rtx body ATTRIBUTE_UNUSED, rtx insn)
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break;
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case CC_OUT_PLUS:
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case CC_OUT_PLUS_NOCLOBBER:
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{
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rtx *op = recog_data.operand;
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int len_dummy, icc;
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/* Extract insn's operands. */
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extract_constrain_insn_cached (insn);
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if (CC_OUT_PLUS == cc)
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avr_out_plus (op, &len_dummy, &icc);
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else
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avr_out_plus_noclobber (op, &len_dummy, &icc);
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avr_out_plus (op, &len_dummy, &icc);
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cc = (enum attr_cc) icc;
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break;
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@ -4773,7 +4779,8 @@ avr_out_plus_1 (rtx *xop, int *plen, enum rtx_code code, int *pcc)
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/* Value to add. There are two ways to add VAL: R += VAL and R -= -VAL. */
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rtx xval = xop[2];
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/* Addition does not set cc0 in a usable way. */
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/* Except in the case of ADIW with 16-bit register (see below)
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addition does not set cc0 in a usable way. */
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*pcc = (MINUS == code) ? CC_SET_CZN : CC_CLOBBER;
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@ -4821,6 +4828,9 @@ avr_out_plus_1 (rtx *xop, int *plen, enum rtx_code code, int *pcc)
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started = true;
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avr_asm_len (code == PLUS ? "adiw %0,%1" : "sbiw %0,%1",
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op, plen, 1);
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if (n_bytes == 2 && PLUS == code)
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*pcc = CC_SET_ZN;
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}
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i++;
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@ -4836,6 +4846,14 @@ avr_out_plus_1 (rtx *xop, int *plen, enum rtx_code code, int *pcc)
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op, plen, 1);
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continue;
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}
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else if ((val8 == 1 || val8 == 0xff)
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&& !started
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&& i == n_bytes - 1)
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{
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avr_asm_len ((code == PLUS) ^ (val8 == 1) ? "dec %0" : "inc %0",
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op, plen, 1);
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break;
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}
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switch (code)
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{
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@ -4924,6 +4942,22 @@ avr_out_plus (rtx *xop, int *plen, int *pcc)
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}
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/* Same as above but XOP has just 3 entries.
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Supply a dummy 4th operand. */
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const char*
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avr_out_plus_noclobber (rtx *xop, int *plen, int *pcc)
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{
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rtx op[4];
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op[0] = xop[0];
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op[1] = xop[1];
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op[2] = xop[2];
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op[3] = NULL_RTX;
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return avr_out_plus (op, plen, pcc);
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}
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/* Output bit operation (IOR, AND, XOR) with register XOP[0] and compile
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time constant XOP[2]:
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@ -5308,6 +5342,8 @@ adjust_insn_length (rtx insn, int len)
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case ADJUST_LEN_OUT_BITOP: avr_out_bitop (insn, op, &len); break;
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case ADJUST_LEN_OUT_PLUS: avr_out_plus (op, &len, NULL); break;
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case ADJUST_LEN_OUT_PLUS_NOCLOBBER:
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avr_out_plus_noclobber (op, &len, NULL); break;
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case ADJUST_LEN_ADDTO_SP: avr_out_addto_sp (op, &len); break;
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@ -78,7 +78,7 @@
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;; Condition code settings.
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(define_attr "cc" "none,set_czn,set_zn,set_n,compare,clobber,
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out_plus"
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out_plus, out_plus_noclobber"
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(const_string "none"))
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(define_attr "type" "branch,branch1,arith,xcall"
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@ -125,7 +125,8 @@
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;; Otherwise do special processing depending on the attribute.
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(define_attr "adjust_len"
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"out_bitop, out_plus, addto_sp, tsthi, tstsi, compare, call,
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"out_bitop, out_plus, out_plus_noclobber, addto_sp,
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tsthi, tstsi, compare, call,
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mov8, mov16, mov32, reload_in16, reload_in32,
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ashlqi, ashrqi, lshrqi,
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ashlhi, ashrhi, lshrhi,
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@ -759,14 +760,22 @@
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(plus:HI (match_operand:HI 1 "register_operand" "")
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(match_operand:HI 2 "nonmemory_operand" "")))]
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""
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"
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{
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if (GET_CODE (operands[2]) == CONST_INT)
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{
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short tmp = INTVAL (operands[2]);
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operands[2] = GEN_INT(tmp);
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}
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}")
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{
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if (CONST_INT_P (operands[2]))
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{
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operands[2] = gen_int_mode (INTVAL (operands[2]), HImode);
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if (can_create_pseudo_p()
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&& !stack_register_operand (operands[0], HImode)
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&& !stack_register_operand (operands[1], HImode)
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&& !d_register_operand (operands[0], HImode)
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&& !d_register_operand (operands[1], HImode))
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{
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emit_insn (gen_addhi3_clobber (operands[0], operands[1], operands[2]));
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DONE;
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}
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}
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})
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(define_insn "*addhi3_zero_extend"
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@ -803,20 +812,77 @@
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(set_attr "adjust_len" "addto_sp")])
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(define_insn "*addhi3"
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[(set (match_operand:HI 0 "register_operand" "=r,!w,!w,d,r,r")
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(plus:HI
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(match_operand:HI 1 "register_operand" "%0,0,0,0,0,0")
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(match_operand:HI 2 "nonmemory_operand" "r,I,J,i,P,N")))]
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[(set (match_operand:HI 0 "register_operand" "=r,d,d")
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(plus:HI (match_operand:HI 1 "register_operand" "%0,0,0")
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(match_operand:HI 2 "nonmemory_operand" "r,s,n")))]
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""
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"@
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add %A0,%A2\;adc %B0,%B2
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adiw %A0,%2
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sbiw %A0,%n2
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subi %A0,lo8(-(%2))\;sbci %B0,hi8(-(%2))
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sec\;adc %A0,__zero_reg__\;adc %B0,__zero_reg__
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sec\;sbc %A0,__zero_reg__\;sbc %B0,__zero_reg__"
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[(set_attr "length" "2,1,1,2,3,3")
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(set_attr "cc" "set_n,set_czn,set_czn,set_czn,set_n,set_n")])
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{
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static const char * const asm_code[] =
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{
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"add %A0,%A2\;adc %B0,%B2",
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"subi %A0,lo8(-(%2))\;sbci %B0,hi8(-(%2))",
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""
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};
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if (*asm_code[which_alternative])
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return asm_code[which_alternative];
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return avr_out_plus_noclobber (operands, NULL, NULL);
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}
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[(set_attr "length" "2,2,2")
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(set_attr "adjust_len" "*,*,out_plus_noclobber")
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(set_attr "cc" "set_n,set_czn,out_plus_noclobber")])
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;; Adding a constant to NO_LD_REGS might have lead to a reload of
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;; that constant to LD_REGS. We don't add a scratch to *addhi3
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;; itself because that insn is special to reload.
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(define_peephole2 ; addhi3_clobber
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[(set (match_operand:HI 0 "d_register_operand" "")
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(match_operand:HI 1 "const_int_operand" ""))
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(set (match_operand:HI 2 "l_register_operand" "")
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(plus:HI (match_dup 2)
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(match_dup 0)))]
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"peep2_reg_dead_p (2, operands[0])"
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[(parallel [(set (match_dup 2)
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(plus:HI (match_dup 2)
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(match_dup 1)))
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(clobber (match_dup 3))])]
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{
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operands[3] = simplify_gen_subreg (QImode, operands[0], HImode, 0);
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})
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;; Same, but with reload to NO_LD_REGS
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;; Combine *reload_inhi with *addhi3
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(define_peephole2 ; addhi3_clobber
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[(parallel [(set (match_operand:HI 0 "l_register_operand" "")
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(match_operand:HI 1 "const_int_operand" ""))
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(clobber (match_operand:QI 2 "d_register_operand" ""))])
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(set (match_operand:HI 3 "l_register_operand" "")
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(plus:HI (match_dup 3)
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(match_dup 0)))]
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"peep2_reg_dead_p (2, operands[0])"
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[(parallel [(set (match_dup 3)
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(plus:HI (match_dup 3)
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(match_dup 1)))
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(clobber (match_dup 2))])])
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(define_insn "addhi3_clobber"
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[(set (match_operand:HI 0 "register_operand" "=d,l")
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(plus:HI (match_operand:HI 1 "register_operand" "%0,0")
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(match_operand:HI 2 "const_int_operand" "n,n")))
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(clobber (match_scratch:QI 3 "=X,&d"))]
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""
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{
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gcc_assert (REGNO (operands[0]) == REGNO (operands[1]));
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return avr_out_plus (operands, NULL, NULL);
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}
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[(set_attr "length" "4")
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(set_attr "adjust_len" "out_plus")
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(set_attr "cc" "out_plus")])
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(define_insn "addsi3"
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[(set (match_operand:SI 0 "register_operand" "=r,d ,d,r")
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@ -3606,12 +3672,8 @@
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(if_then_else (match_test "!AVR_HAVE_JMP_CALL")
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(const_int 1)
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(const_int 2))
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(if_then_else (and (ge (minus (pc)
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(match_dup 0))
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(const_int -2047))
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(le (minus (pc)
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(match_dup 0))
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(const_int 2047)))
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(if_then_else (and (ge (minus (pc) (match_dup 0)) (const_int -2047))
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(le (minus (pc) (match_dup 0)) (const_int 2047)))
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(const_int 1)
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(const_int 2))))
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(set_attr "cc" "none")])
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