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sparc.c (sparc_expand_vec_perm_bmask): Use %g0 as destination register for bmasksi_vis. 

* config/sparc/sparc.c (sparc_expand_vec_perm_bmask): Use %g0 as
	destination register for bmasksi_vis.
	(vector_init_bshuffle): Likewise.
	* config/sparc/sparc.md (vec_perm_constv8qi): Likewise.

From-SVN: r199370
This commit is contained in:
Eric Botcazou 2013-05-28 09:56:33 +00:00 committed by Eric Botcazou
parent 388c13d667
commit 2f56a3116f
5 changed files with 18 additions and 6 deletions
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7
gcc/ChangeLog
View File

@ -1,3 +1,10 @@
2013-05-28 Eric Botcazou <ebotcazou@adacore.com>
* config/sparc/sparc.c (sparc_expand_vec_perm_bmask): Use %g0 as
destination register for bmasksi_vis.
(vector_init_bshuffle): Likewise.
* config/sparc/sparc.md (vec_perm_constv8qi): Likewise.
2013-05-28 Eric Botcazou <ebotcazou@adacore.com>
* doc/invoke.texi (SPARC Options): Document -mfix-ut699.

8
gcc/config/sparc/sparc.c
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@ -11527,7 +11527,7 @@ sparc_expand_vec_perm_bmask (enum machine_mode vmode, rtx sel)
}
/* Always perform the final addition/merge within the bmask insn. */
emit_insn (gen_bmasksi_vis (gen_reg_rtx (SImode), sel, t_1));
emit_insn (gen_bmasksi_vis (gen_rtx_REG (SImode, 0), sel, t_1));
}
/* Implement TARGET_FRAME_POINTER_REQUIRED. */
@ -11766,7 +11766,7 @@ static void
vector_init_bshuffle (rtx target, rtx elt, enum machine_mode mode,
enum machine_mode inner_mode)
{
rtx t1, final_insn;
rtx t1, final_insn, sel;
int bmask;
t1 = gen_reg_rtx (mode);
@ -11792,8 +11792,8 @@ vector_init_bshuffle (rtx target, rtx elt, enum machine_mode mode,
gcc_unreachable ();
}
emit_insn (gen_bmasksi_vis (gen_reg_rtx (SImode), CONST0_RTX (SImode),
force_reg (SImode, GEN_INT (bmask))));
sel = force_reg (SImode, GEN_INT (bmask));
emit_insn (gen_bmasksi_vis (gen_rtx_REG (SImode, 0), sel, const0_rtx));
emit_insn (final_insn);
}

2
gcc/config/sparc/sparc.md
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@ -8589,7 +8589,7 @@
mask |= (INTVAL (XVECEXP (sel, 0, i)) & 0xf) << (28 - i*4);
sel = force_reg (SImode, gen_int_mode (mask, SImode));
emit_insn (gen_bmasksi_vis (gen_reg_rtx (SImode), sel, const0_rtx));
emit_insn (gen_bmasksi_vis (gen_rtx_REG (SImode, 0), sel, const0_rtx));
emit_insn (gen_bshufflev8qi_vis (operands[0], operands[1], operands[2]));
DONE;
})

4
gcc/testsuite/ChangeLog
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@ -1,3 +1,7 @@
2013-05-28 Eric Botcazou <ebotcazou@adacore.com>
* gcc.target/sparc/bmaskbshuf.c: Remove superfluous options.
2013-05-27 Richard Biener <rguenther@suse.de>
PR middle-end/57412

3
gcc/testsuite/gcc.target/sparc/bmaskbshuf.c
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@ -1,5 +1,6 @@
/* { dg-do compile } */
/* { dg-options "-O -mcpu=ultrasparc3 -mvis -mvis2" } */
/* { dg-options "-O -mvis2" } */
typedef long long int64_t;
typedef int vec32 __attribute__((vector_size(8)));
typedef short vec16 __attribute__((vector_size(8)));