sparc.c (sparc_expand_vec_perm_bmask): Use %g0 as destination register for bmasksi_vis.
* config/sparc/sparc.c (sparc_expand_vec_perm_bmask): Use %g0 as destination register for bmasksi_vis. (vector_init_bshuffle): Likewise. * config/sparc/sparc.md (vec_perm_constv8qi): Likewise. From-SVN: r199370
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@ -1,3 +1,10 @@
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2013-05-28 Eric Botcazou <ebotcazou@adacore.com>
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* config/sparc/sparc.c (sparc_expand_vec_perm_bmask): Use %g0 as
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destination register for bmasksi_vis.
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(vector_init_bshuffle): Likewise.
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* config/sparc/sparc.md (vec_perm_constv8qi): Likewise.
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2013-05-28 Eric Botcazou <ebotcazou@adacore.com>
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2013-05-28 Eric Botcazou <ebotcazou@adacore.com>
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* doc/invoke.texi (SPARC Options): Document -mfix-ut699.
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* doc/invoke.texi (SPARC Options): Document -mfix-ut699.
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@ -11527,7 +11527,7 @@ sparc_expand_vec_perm_bmask (enum machine_mode vmode, rtx sel)
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}
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}
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/* Always perform the final addition/merge within the bmask insn. */
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/* Always perform the final addition/merge within the bmask insn. */
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emit_insn (gen_bmasksi_vis (gen_reg_rtx (SImode), sel, t_1));
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emit_insn (gen_bmasksi_vis (gen_rtx_REG (SImode, 0), sel, t_1));
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}
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}
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/* Implement TARGET_FRAME_POINTER_REQUIRED. */
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/* Implement TARGET_FRAME_POINTER_REQUIRED. */
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@ -11766,7 +11766,7 @@ static void
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vector_init_bshuffle (rtx target, rtx elt, enum machine_mode mode,
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vector_init_bshuffle (rtx target, rtx elt, enum machine_mode mode,
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enum machine_mode inner_mode)
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enum machine_mode inner_mode)
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{
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{
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rtx t1, final_insn;
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rtx t1, final_insn, sel;
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int bmask;
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int bmask;
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t1 = gen_reg_rtx (mode);
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t1 = gen_reg_rtx (mode);
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@ -11792,8 +11792,8 @@ vector_init_bshuffle (rtx target, rtx elt, enum machine_mode mode,
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gcc_unreachable ();
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gcc_unreachable ();
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}
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}
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emit_insn (gen_bmasksi_vis (gen_reg_rtx (SImode), CONST0_RTX (SImode),
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sel = force_reg (SImode, GEN_INT (bmask));
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force_reg (SImode, GEN_INT (bmask))));
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emit_insn (gen_bmasksi_vis (gen_rtx_REG (SImode, 0), sel, const0_rtx));
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emit_insn (final_insn);
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emit_insn (final_insn);
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}
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}
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@ -8589,7 +8589,7 @@
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mask |= (INTVAL (XVECEXP (sel, 0, i)) & 0xf) << (28 - i*4);
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mask |= (INTVAL (XVECEXP (sel, 0, i)) & 0xf) << (28 - i*4);
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sel = force_reg (SImode, gen_int_mode (mask, SImode));
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sel = force_reg (SImode, gen_int_mode (mask, SImode));
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emit_insn (gen_bmasksi_vis (gen_reg_rtx (SImode), sel, const0_rtx));
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emit_insn (gen_bmasksi_vis (gen_rtx_REG (SImode, 0), sel, const0_rtx));
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emit_insn (gen_bshufflev8qi_vis (operands[0], operands[1], operands[2]));
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emit_insn (gen_bshufflev8qi_vis (operands[0], operands[1], operands[2]));
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DONE;
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DONE;
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})
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})
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@ -1,3 +1,7 @@
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2013-05-28 Eric Botcazou <ebotcazou@adacore.com>
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* gcc.target/sparc/bmaskbshuf.c: Remove superfluous options.
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2013-05-27 Richard Biener <rguenther@suse.de>
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2013-05-27 Richard Biener <rguenther@suse.de>
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PR middle-end/57412
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PR middle-end/57412
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@ -1,5 +1,6 @@
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/* { dg-do compile } */
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/* { dg-do compile } */
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/* { dg-options "-O -mcpu=ultrasparc3 -mvis -mvis2" } */
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/* { dg-options "-O -mvis2" } */
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typedef long long int64_t;
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typedef long long int64_t;
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typedef int vec32 __attribute__((vector_size(8)));
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typedef int vec32 __attribute__((vector_size(8)));
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typedef short vec16 __attribute__((vector_size(8)));
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typedef short vec16 __attribute__((vector_size(8)));
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