aarch64: Remove redundant mult patterns
Following on from the previous commit to fix up the syntax for add/sub/adds/subs and friends with a sign/zero-extended operand, this patch removes the "mult" variants of these patterns which are all redundant. This patch removes the following patterns from the AArch64 backend: *adds_mul_imm_<mode> *subs_mul_imm_<mode> *adds_<optab><mode>_multp2 *subs_<optab><mode>_multp2 *add_mul_imm_<mode> *add_<optab><ALLX:mode>_mult_<GPI:mode> *add_<optab><SHORT:mode>_mult_si_uxtw *add_<optab><mode>_multp2 *add_<optab>si_multp2_uxtw *add_uxt<mode>_multp2 *add_uxtsi_multp2_uxtw *sub_mul_imm_<mode> *sub_mul_imm_si_uxtw *sub_<optab><mode>_multp2 *sub_<optab>si_multp2_uxtw *sub_uxt<mode>_multp2 *sub_uxtsi_multp2_uxtw *neg_mul_imm_<mode>2 *neg_mul_imm_si2_uxtw Together with the following predicates which were used only by these patterns: aarch64_pwr_imm3 aarch64_pwr_2_si aarch64_pwr_2_di These patterns are all redundant since multiplications by powers of two should be represented as shfits outside a (mem). --- gcc/ChangeLog: * config/aarch64/aarch64.md (*adds_mul_imm_<mode>): Delete. (*subs_mul_imm_<mode>): Delete. (*adds_<optab><mode>_multp2): Delete. (*subs_<optab><mode>_multp2): Delete. (*add_mul_imm_<mode>): Delete. (*add_<optab><ALLX:mode>_mult_<GPI:mode>): Delete. (*add_<optab><SHORT:mode>_mult_si_uxtw): Delete. (*add_<optab><mode>_multp2): Delete. (*add_<optab>si_multp2_uxtw): Delete. (*add_uxt<mode>_multp2): Delete. (*add_uxtsi_multp2_uxtw): Delete. (*sub_mul_imm_<mode>): Delete. (*sub_mul_imm_si_uxtw): Delete. (*sub_<optab><mode>_multp2): Delete. (*sub_<optab>si_multp2_uxtw): Delete. (*sub_uxt<mode>_multp2): Delete. (*sub_uxtsi_multp2_uxtw): Delete. (*neg_mul_imm_<mode>2): Delete. (*neg_mul_imm_si2_uxtw): Delete. * config/aarch64/predicates.md (aarch64_pwr_imm3): Delete. (aarch64_pwr_2_si): Delete. (aarch64_pwr_2_di): Delete.
This commit is contained in:
Alex Coplan
parent
d4febc75e8
commit
2f8ae301f6
@ -2341,38 +2341,6 @@
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[(set_attr "type" "alus_shift_imm")]
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[(set_attr "type" "alus_shift_imm")]
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)
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)
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(define_insn "*adds_mul_imm_<mode>"
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[(set (reg:CC_NZ CC_REGNUM)
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(compare:CC_NZ
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(plus:GPI (mult:GPI
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(match_operand:GPI 1 "register_operand" "r")
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(match_operand:QI 2 "aarch64_pwr_2_<mode>" "n"))
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(match_operand:GPI 3 "register_operand" "r"))
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(const_int 0)))
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(set (match_operand:GPI 0 "register_operand" "=r")
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(plus:GPI (mult:GPI (match_dup 1) (match_dup 2))
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(match_dup 3)))]
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""
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"adds\\t%<w>0, %<w>3, %<w>1, lsl %p2"
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[(set_attr "type" "alus_shift_imm")]
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)
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(define_insn "*subs_mul_imm_<mode>"
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[(set (reg:CC_NZ CC_REGNUM)
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(compare:CC_NZ
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(minus:GPI (match_operand:GPI 1 "register_operand" "r")
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(mult:GPI
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(match_operand:GPI 2 "register_operand" "r")
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(match_operand:QI 3 "aarch64_pwr_2_<mode>" "n")))
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(const_int 0)))
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(set (match_operand:GPI 0 "register_operand" "=r")
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(minus:GPI (match_dup 1)
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(mult:GPI (match_dup 2) (match_dup 3))))]
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""
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"subs\\t%<w>0, %<w>1, %<w>2, lsl %p3"
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[(set_attr "type" "alus_shift_imm")]
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)
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(define_insn "*adds_<optab><ALLX:mode>_<GPI:mode>"
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(define_insn "*adds_<optab><ALLX:mode>_<GPI:mode>"
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[(set (reg:CC_NZ CC_REGNUM)
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[(set (reg:CC_NZ CC_REGNUM)
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(compare:CC_NZ
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(compare:CC_NZ
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@ -2437,46 +2405,6 @@
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[(set_attr "type" "alus_ext")]
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[(set_attr "type" "alus_ext")]
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)
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)
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(define_insn "*adds_<optab><mode>_multp2"
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[(set (reg:CC_NZ CC_REGNUM)
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(compare:CC_NZ
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(plus:GPI (ANY_EXTRACT:GPI
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(mult:GPI (match_operand:GPI 1 "register_operand" "r")
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(match_operand 2 "aarch64_pwr_imm3" "Up3"))
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(match_operand 3 "const_int_operand" "n")
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(const_int 0))
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(match_operand:GPI 4 "register_operand" "rk"))
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(const_int 0)))
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(set (match_operand:GPI 0 "register_operand" "=r")
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(plus:GPI (ANY_EXTRACT:GPI (mult:GPI (match_dup 1) (match_dup 2))
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(match_dup 3)
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(const_int 0))
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(match_dup 4)))]
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"aarch64_is_extend_from_extract (<MODE>mode, operands[2], operands[3])"
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"adds\\t%<w>0, %<w>4, %<w>1, <su>xt%e3 %p2"
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[(set_attr "type" "alus_ext")]
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)
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(define_insn "*subs_<optab><mode>_multp2"
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[(set (reg:CC_NZ CC_REGNUM)
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(compare:CC_NZ
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(minus:GPI (match_operand:GPI 4 "register_operand" "rk")
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(ANY_EXTRACT:GPI
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(mult:GPI (match_operand:GPI 1 "register_operand" "r")
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(match_operand 2 "aarch64_pwr_imm3" "Up3"))
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(match_operand 3 "const_int_operand" "n")
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(const_int 0)))
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(const_int 0)))
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(set (match_operand:GPI 0 "register_operand" "=r")
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(minus:GPI (match_dup 4) (ANY_EXTRACT:GPI
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(mult:GPI (match_dup 1) (match_dup 2))
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(match_dup 3)
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(const_int 0))))]
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"aarch64_is_extend_from_extract (<MODE>mode, operands[2], operands[3])"
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"subs\\t%<w>0, %<w>4, %<w>1, <su>xt%e3 %p2"
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[(set_attr "type" "alus_ext")]
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)
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(define_insn "*add<mode>3nr_compare0"
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(define_insn "*add<mode>3nr_compare0"
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[(set (reg:CC_NZ CC_REGNUM)
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[(set (reg:CC_NZ CC_REGNUM)
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(compare:CC_NZ
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(compare:CC_NZ
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@ -2534,16 +2462,6 @@
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[(set_attr "type" "alu_shift_imm")]
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[(set_attr "type" "alu_shift_imm")]
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)
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)
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(define_insn "*add_mul_imm_<mode>"
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[(set (match_operand:GPI 0 "register_operand" "=r")
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(plus:GPI (mult:GPI (match_operand:GPI 1 "register_operand" "r")
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(match_operand:QI 2 "aarch64_pwr_2_<mode>" "n"))
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(match_operand:GPI 3 "register_operand" "r")))]
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""
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"add\\t%<w>0, %<w>3, %<w>1, lsl %p2"
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[(set_attr "type" "alu_shift_imm")]
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)
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(define_insn "*add_<optab><ALLX:mode>_<GPI:mode>"
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(define_insn "*add_<optab><ALLX:mode>_<GPI:mode>"
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[(set (match_operand:GPI 0 "register_operand" "=rk")
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[(set (match_operand:GPI 0 "register_operand" "=rk")
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(plus:GPI (ANY_EXTEND:GPI (match_operand:ALLX 1 "register_operand" "r"))
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(plus:GPI (ANY_EXTEND:GPI (match_operand:ALLX 1 "register_operand" "r"))
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@ -2588,57 +2506,6 @@
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[(set_attr "type" "alu_ext")]
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[(set_attr "type" "alu_ext")]
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)
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)
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(define_insn "*add_<optab><ALLX:mode>_mult_<GPI:mode>"
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[(set (match_operand:GPI 0 "register_operand" "=rk")
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(plus:GPI (mult:GPI (ANY_EXTEND:GPI
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(match_operand:ALLX 1 "register_operand" "r"))
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(match_operand 2 "aarch64_pwr_imm3" "Up3"))
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(match_operand:GPI 3 "register_operand" "r")))]
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""
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"add\\t%<GPI:w>0, %<GPI:w>3, %<GPI:w>1, <su>xt<ALLX:size> %p2"
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[(set_attr "type" "alu_ext")]
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)
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;; zero_extend version of above
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(define_insn "*add_<optab><SHORT:mode>_mult_si_uxtw"
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[(set (match_operand:DI 0 "register_operand" "=rk")
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(zero_extend:DI (plus:SI (mult:SI (ANY_EXTEND:SI
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(match_operand:SHORT 1 "register_operand" "r"))
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(match_operand 2 "aarch64_pwr_imm3" "Up3"))
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(match_operand:SI 3 "register_operand" "r"))))]
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""
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"add\\t%w0, %w3, %w1, <su>xt<SHORT:size> %p2"
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[(set_attr "type" "alu_ext")]
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)
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(define_insn "*add_<optab><mode>_multp2"
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[(set (match_operand:GPI 0 "register_operand" "=rk")
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(plus:GPI (ANY_EXTRACT:GPI
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(mult:GPI (match_operand:GPI 1 "register_operand" "r")
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(match_operand 2 "aarch64_pwr_imm3" "Up3"))
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(match_operand 3 "const_int_operand" "n")
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(const_int 0))
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(match_operand:GPI 4 "register_operand" "r")))]
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"aarch64_is_extend_from_extract (<MODE>mode, operands[2], operands[3])"
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"add\\t%<w>0, %<w>4, %<w>1, <su>xt%e3 %p2"
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[(set_attr "type" "alu_ext")]
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)
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;; zero_extend version of above
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(define_insn "*add_<optab>si_multp2_uxtw"
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[(set (match_operand:DI 0 "register_operand" "=rk")
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(zero_extend:DI
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(plus:SI (ANY_EXTRACT:SI
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(mult:SI (match_operand:SI 1 "register_operand" "r")
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(match_operand 2 "aarch64_pwr_imm3" "Up3"))
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(match_operand 3 "const_int_operand" "n")
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(const_int 0))
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(match_operand:SI 4 "register_operand" "r"))))]
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"aarch64_is_extend_from_extract (SImode, operands[2], operands[3])"
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"add\\t%w0, %w4, %w1, <su>xt%e3 %p2"
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[(set_attr "type" "alu_ext")]
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)
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(define_expand "add<mode>3_carryin"
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(define_expand "add<mode>3_carryin"
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[(set (match_operand:GPI 0 "register_operand")
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[(set (match_operand:GPI 0 "register_operand")
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(plus:GPI
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(plus:GPI
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@ -2840,38 +2707,6 @@
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[(set_attr "type" "alu_ext")]
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[(set_attr "type" "alu_ext")]
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)
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)
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(define_insn "*add_uxt<mode>_multp2"
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[(set (match_operand:GPI 0 "register_operand" "=rk")
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(plus:GPI (and:GPI
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(mult:GPI (match_operand:GPI 1 "register_operand" "r")
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(match_operand 2 "aarch64_pwr_imm3" "Up3"))
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(match_operand 3 "const_int_operand" "n"))
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(match_operand:GPI 4 "register_operand" "r")))]
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"aarch64_uxt_size (exact_log2 (INTVAL (operands[2])), INTVAL (operands[3])) != 0"
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"*
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operands[3] = GEN_INT (aarch64_uxt_size (exact_log2 (INTVAL (operands[2])),
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INTVAL (operands[3])));
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return \"add\t%<w>0, %<w>4, %<w>1, uxt%e3 %p2\";"
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[(set_attr "type" "alu_ext")]
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)
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;; zero_extend version of above
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(define_insn "*add_uxtsi_multp2_uxtw"
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[(set (match_operand:DI 0 "register_operand" "=rk")
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(zero_extend:DI
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(plus:SI (and:SI
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(mult:SI (match_operand:SI 1 "register_operand" "r")
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(match_operand 2 "aarch64_pwr_imm3" "Up3"))
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(match_operand 3 "const_int_operand" "n"))
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(match_operand:SI 4 "register_operand" "r"))))]
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"aarch64_uxt_size (exact_log2 (INTVAL (operands[2])), INTVAL (operands[3])) != 0"
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"*
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operands[3] = GEN_INT (aarch64_uxt_size (exact_log2 (INTVAL (operands[2])),
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INTVAL (operands[3])));
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return \"add\t%w0, %w4, %w1, uxt%e3 %p2\";"
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[(set_attr "type" "alu_ext")]
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)
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(define_insn "subsi3"
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(define_insn "subsi3"
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[(set (match_operand:SI 0 "register_operand" "=rk")
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[(set (match_operand:SI 0 "register_operand" "=rk")
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(minus:SI (match_operand:SI 1 "register_operand" "rk")
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(minus:SI (match_operand:SI 1 "register_operand" "rk")
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@ -3275,30 +3110,6 @@
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[(set_attr "type" "alu_shift_imm")]
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[(set_attr "type" "alu_shift_imm")]
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)
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)
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(define_insn "*sub_mul_imm_<mode>"
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[(set (match_operand:GPI 0 "register_operand" "=r")
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(minus:GPI (match_operand:GPI 3 "register_operand" "r")
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(mult:GPI
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(match_operand:GPI 1 "register_operand" "r")
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(match_operand:QI 2 "aarch64_pwr_2_<mode>" "n"))))]
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""
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"sub\\t%<w>0, %<w>3, %<w>1, lsl %p2"
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[(set_attr "type" "alu_shift_imm")]
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)
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;; zero_extend version of above
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(define_insn "*sub_mul_imm_si_uxtw"
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[(set (match_operand:DI 0 "register_operand" "=r")
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(zero_extend:DI
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(minus:SI (match_operand:SI 3 "register_operand" "r")
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(mult:SI
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(match_operand:SI 1 "register_operand" "r")
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(match_operand:QI 2 "aarch64_pwr_2_si" "n")))))]
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""
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"sub\\t%w0, %w3, %w1, lsl %p2"
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[(set_attr "type" "alu_shift_imm")]
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)
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(define_insn "*sub_<optab><ALLX:mode>_<GPI:mode>"
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(define_insn "*sub_<optab><ALLX:mode>_<GPI:mode>"
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[(set (match_operand:GPI 0 "register_operand" "=rk")
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[(set (match_operand:GPI 0 "register_operand" "=rk")
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(minus:GPI (match_operand:GPI 1 "register_operand" "rk")
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(minus:GPI (match_operand:GPI 1 "register_operand" "rk")
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[(set_attr "type" "alu_ext")]
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[(set_attr "type" "alu_ext")]
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)
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)
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(define_insn "*sub_<optab><mode>_multp2"
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[(set (match_operand:GPI 0 "register_operand" "=rk")
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(minus:GPI (match_operand:GPI 4 "register_operand" "rk")
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(ANY_EXTRACT:GPI
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(mult:GPI (match_operand:GPI 1 "register_operand" "r")
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(match_operand 2 "aarch64_pwr_imm3" "Up3"))
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(match_operand 3 "const_int_operand" "n")
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(const_int 0))))]
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"aarch64_is_extend_from_extract (<MODE>mode, operands[2], operands[3])"
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"sub\\t%<w>0, %<w>4, %<w>1, <su>xt%e3 %p2"
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[(set_attr "type" "alu_ext")]
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)
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;; zero_extend version of above
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(define_insn "*sub_<optab>si_multp2_uxtw"
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[(set (match_operand:DI 0 "register_operand" "=rk")
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(zero_extend:DI
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(minus:SI (match_operand:SI 4 "register_operand" "rk")
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(ANY_EXTRACT:SI
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(mult:SI (match_operand:SI 1 "register_operand" "r")
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(match_operand 2 "aarch64_pwr_imm3" "Up3"))
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(match_operand 3 "const_int_operand" "n")
|
|
||||||
(const_int 0)))))]
|
|
||||||
"aarch64_is_extend_from_extract (SImode, operands[2], operands[3])"
|
|
||||||
"sub\\t%w0, %w4, %w1, <su>xt%e3 %p2"
|
|
||||||
[(set_attr "type" "alu_ext")]
|
|
||||||
)
|
|
||||||
|
|
||||||
;; The hardware description is op1 + ~op2 + C.
|
;; The hardware description is op1 + ~op2 + C.
|
||||||
;; = op1 + (-op2 + 1) + (1 - !C)
|
;; = op1 + (-op2 + 1) + (1 - !C)
|
||||||
;; = op1 - op2 - 1 + 1 - !C
|
;; = op1 - op2 - 1 + 1 - !C
|
||||||
@ -3628,38 +3411,6 @@
|
|||||||
[(set_attr "type" "alu_ext")]
|
[(set_attr "type" "alu_ext")]
|
||||||
)
|
)
|
||||||
|
|
||||||
(define_insn "*sub_uxt<mode>_multp2"
|
|
||||||
[(set (match_operand:GPI 0 "register_operand" "=rk")
|
|
||||||
(minus:GPI (match_operand:GPI 4 "register_operand" "rk")
|
|
||||||
(and:GPI
|
|
||||||
(mult:GPI (match_operand:GPI 1 "register_operand" "r")
|
|
||||||
(match_operand 2 "aarch64_pwr_imm3" "Up3"))
|
|
||||||
(match_operand 3 "const_int_operand" "n"))))]
|
|
||||||
"aarch64_uxt_size (exact_log2 (INTVAL (operands[2])),INTVAL (operands[3])) != 0"
|
|
||||||
"*
|
|
||||||
operands[3] = GEN_INT (aarch64_uxt_size (exact_log2 (INTVAL (operands[2])),
|
|
||||||
INTVAL (operands[3])));
|
|
||||||
return \"sub\t%<w>0, %<w>4, %<w>1, uxt%e3 %p2\";"
|
|
||||||
[(set_attr "type" "alu_ext")]
|
|
||||||
)
|
|
||||||
|
|
||||||
;; zero_extend version of above
|
|
||||||
(define_insn "*sub_uxtsi_multp2_uxtw"
|
|
||||||
[(set (match_operand:DI 0 "register_operand" "=rk")
|
|
||||||
(zero_extend:DI
|
|
||||||
(minus:SI (match_operand:SI 4 "register_operand" "rk")
|
|
||||||
(and:SI
|
|
||||||
(mult:SI (match_operand:SI 1 "register_operand" "r")
|
|
||||||
(match_operand 2 "aarch64_pwr_imm3" "Up3"))
|
|
||||||
(match_operand 3 "const_int_operand" "n")))))]
|
|
||||||
"aarch64_uxt_size (exact_log2 (INTVAL (operands[2])),INTVAL (operands[3])) != 0"
|
|
||||||
"*
|
|
||||||
operands[3] = GEN_INT (aarch64_uxt_size (exact_log2 (INTVAL (operands[2])),
|
|
||||||
INTVAL (operands[3])));
|
|
||||||
return \"sub\t%w0, %w4, %w1, uxt%e3 %p2\";"
|
|
||||||
[(set_attr "type" "alu_ext")]
|
|
||||||
)
|
|
||||||
|
|
||||||
(define_expand "abs<mode>2"
|
(define_expand "abs<mode>2"
|
||||||
[(match_operand:GPI 0 "register_operand")
|
[(match_operand:GPI 0 "register_operand")
|
||||||
(match_operand:GPI 1 "register_operand")]
|
(match_operand:GPI 1 "register_operand")]
|
||||||
@ -3772,28 +3523,6 @@
|
|||||||
[(set_attr "type" "alu_shift_imm")]
|
[(set_attr "type" "alu_shift_imm")]
|
||||||
)
|
)
|
||||||
|
|
||||||
(define_insn "*neg_mul_imm_<mode>2"
|
|
||||||
[(set (match_operand:GPI 0 "register_operand" "=r")
|
|
||||||
(neg:GPI (mult:GPI
|
|
||||||
(match_operand:GPI 1 "register_operand" "r")
|
|
||||||
(match_operand:QI 2 "aarch64_pwr_2_<mode>" "n"))))]
|
|
||||||
""
|
|
||||||
"neg\\t%<w>0, %<w>1, lsl %p2"
|
|
||||||
[(set_attr "type" "alu_shift_imm")]
|
|
||||||
)
|
|
||||||
|
|
||||||
;; zero_extend version of above
|
|
||||||
(define_insn "*neg_mul_imm_si2_uxtw"
|
|
||||||
[(set (match_operand:DI 0 "register_operand" "=r")
|
|
||||||
(zero_extend:DI
|
|
||||||
(neg:SI (mult:SI
|
|
||||||
(match_operand:SI 1 "register_operand" "r")
|
|
||||||
(match_operand:QI 2 "aarch64_pwr_2_si" "n")))))]
|
|
||||||
""
|
|
||||||
"neg\\t%w0, %w1, lsl %p2"
|
|
||||||
[(set_attr "type" "alu_shift_imm")]
|
|
||||||
)
|
|
||||||
|
|
||||||
(define_insn "mul<mode>3"
|
(define_insn "mul<mode>3"
|
||||||
[(set (match_operand:GPI 0 "register_operand" "=r")
|
[(set (match_operand:GPI 0 "register_operand" "=r")
|
||||||
(mult:GPI (match_operand:GPI 1 "register_operand" "r")
|
(mult:GPI (match_operand:GPI 1 "register_operand" "r")
|
||||||
|
|||||||
@ -235,21 +235,6 @@
|
|||||||
(and (match_code "const_int")
|
(and (match_code "const_int")
|
||||||
(match_test "IN_RANGE (UINTVAL (op), 0, 0xffffff)")))
|
(match_test "IN_RANGE (UINTVAL (op), 0, 0xffffff)")))
|
||||||
|
|
||||||
(define_predicate "aarch64_pwr_imm3"
|
|
||||||
(and (match_code "const_int")
|
|
||||||
(match_test "INTVAL (op) != 0
|
|
||||||
&& (unsigned) exact_log2 (INTVAL (op)) <= 4")))
|
|
||||||
|
|
||||||
(define_predicate "aarch64_pwr_2_si"
|
|
||||||
(and (match_code "const_int")
|
|
||||||
(match_test "INTVAL (op) != 0
|
|
||||||
&& (unsigned) exact_log2 (INTVAL (op)) < 32")))
|
|
||||||
|
|
||||||
(define_predicate "aarch64_pwr_2_di"
|
|
||||||
(and (match_code "const_int")
|
|
||||||
(match_test "INTVAL (op) != 0
|
|
||||||
&& (unsigned) exact_log2 (INTVAL (op)) < 64")))
|
|
||||||
|
|
||||||
(define_predicate "aarch64_mem_pair_offset"
|
(define_predicate "aarch64_mem_pair_offset"
|
||||||
(and (match_code "const_int")
|
(and (match_code "const_int")
|
||||||
(match_test "aarch64_offset_7bit_signed_scaled_p (mode, INTVAL (op))")))
|
(match_test "aarch64_offset_7bit_signed_scaled_p (mode, INTVAL (op))")))
|
||||||
|
|||||||
Loading…
Reference in New Issue
Block a user