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S/390: Add support for double<->long vector converts

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gcc/ChangeLog:

2018-12-21  Andreas Krebbel  <krebbel@linux.ibm.com>

	* config/s390/vector.md ("floatv2div2df2", "floatunsv2div2df2")
	("fix_truncv2dfv2di2", "fixuns_truncv2dfv2di2"): New pattern
	definitions.

gcc/testsuite/ChangeLog:

2018-12-21  Andreas Krebbel  <krebbel@linux.ibm.com>

	* gcc.target/s390/vector/fp-signedint-convert-1.c: New test.
	* gcc.target/s390/vector/fp-unsignedint-convert-1.c: New test.

From-SVN: r267336
This commit is contained in:
Andreas Krebbel 2018-12-21 18:57:00 +00:00 committed by Andreas Krebbel
parent c3d62ffdc2
commit 2f8df14d37
5 changed files with 115 additions and 0 deletions
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6
gcc/ChangeLog
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@ -1,3 +1,9 @@
2018-12-21 Andreas Krebbel <krebbel@linux.ibm.com>
* config/s390/vector.md ("floatv2div2df2", "floatunsv2div2df2")
("fix_truncv2dfv2di2", "fixuns_truncv2dfv2di2"): New pattern
definitions.
2018-12-21 Eric Botcazou <ebotcazou@adacore.com>
PR rtl-optimization/87727

52
gcc/config/s390/vector.md
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@ -1960,6 +1960,58 @@
operands[6] = gen_reg_rtx (V16QImode);
})
;
; BFP <-> integer conversions
;
; signed integer to floating point
; op2: inexact exception not suppressed (IEEE 754 2008)
; op3: according to current rounding mode
(define_insn "floatv2div2df2"
[(set (match_operand:V2DF 0 "register_operand" "=v")
(float:V2DF (match_operand:V2DI 1 "register_operand" "v")))]
"TARGET_VX"
"vcdgb\t%v0,%v1,0,0"
[(set_attr "op_type" "VRR")])
; unsigned integer to floating point
; op2: inexact exception not suppressed (IEEE 754 2008)
; op3: according to current rounding mode
(define_insn "floatunsv2div2df2"
[(set (match_operand:V2DF 0 "register_operand" "=v")
(unsigned_float:V2DF (match_operand:V2DI 1 "register_operand" "v")))]
"TARGET_VX"
"vcdlgb\t%v0,%v1,0,0"
[(set_attr "op_type" "VRR")])
; floating point to signed integer
; op2: inexact exception not suppressed (IEEE 754 2008)
; op3: rounding mode 5 (round towards 0 C11 6.3.1.4)
(define_insn "fix_truncv2dfv2di2"
[(set (match_operand:V2DI 0 "register_operand" "=v")
(fix:V2DI (match_operand:V2DF 1 "register_operand" "v")))]
"TARGET_VX"
"vcgdb\t%v0,%v1,0,5"
[(set_attr "op_type" "VRR")])
; floating point to unsigned integer
; op2: inexact exception not suppressed (IEEE 754 2008)
; op3: rounding mode 5 (round towards 0 C11 6.3.1.4)
(define_insn "fixuns_truncv2dfv2di2"
[(set (match_operand:V2DI 0 "register_operand" "=v")
(unsigned_fix:V2DI (match_operand:V2DF 1 "register_operand" "v")))]
"TARGET_VX"
"vclgdb\t%v0,%v1,0,5"
[(set_attr "op_type" "VRR")])
; reduc_smin
; reduc_smax
; reduc_umin

5
gcc/testsuite/ChangeLog
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@ -1,3 +1,8 @@
2018-12-21 Andreas Krebbel <krebbel@linux.ibm.com>
* gcc.target/s390/vector/fp-signedint-convert-1.c: New test.
* gcc.target/s390/vector/fp-unsignedint-convert-1.c: New test.
2018-12-21 Jakub Jelinek <jakub@redhat.com>
PR rtl-optimization/88563

26
gcc/testsuite/gcc.target/s390/vector/fp-signedint-convert-1.c Normal file
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@ -0,0 +1,26 @@
/* { dg-compile } */
/* { dg-options "-O3 -march=z13 -mzarch" } */
typedef long long __attribute__((vector_size(16))) v2di;
typedef double __attribute__((vector_size(16))) v2df;
v2di longvec;
v2df doublevec;
v2di
tolong (v2df a)
{
v2di out = (v2di){ (long long)a[0], (long long)a[1] };
return out;
}
/* { dg-final { scan-assembler-times "vcgdb\t%v24,%v24,0,5" 1 } } */
v2df
todouble (v2di a)
{
v2df out = (v2df){ (double)a[0], (double)a[1] };
return out;
}
/* { dg-final { scan-assembler-times "vcdgb\t%v24,%v24,0,0" 1 } } */

26
gcc/testsuite/gcc.target/s390/vector/fp-unsignedint-convert-1.c Normal file
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@ -0,0 +1,26 @@
/* { dg-compile } */
/* { dg-options "-O3 -march=z13 -mzarch" } */
typedef unsigned long long __attribute__((vector_size(16))) v2di;
typedef double __attribute__((vector_size(16))) v2df;
v2di longvec;
v2df doublevec;
v2di
toulong (v2df a)
{
v2di out = (v2di){ (unsigned long long)a[0], (unsigned long long)a[1] };
return out;
}
/* { dg-final { scan-assembler-times "vclgdb\t%v24,%v24,0,5" 1 } } */
v2df
todouble (v2di a)
{
v2df out = (v2df){ (double)a[0], (double)a[1] };
return out;
}
/* { dg-final { scan-assembler-times "vcdlgb\t%v24,%v24,0,0" 1 } } */