ia64.c (ia64_split_tmode, [...]): Rewrite to use POST_INC/POST_DEC/POST_MODIFY instead of a scratch pointer.
2004-01-28 Zack Weinberg <zack@codesourcery.com> Jim Wilson <wilson@specifixinc.com> * config/ia64/ia64.c (ia64_split_tmode, ia64_split_tmode_move): Rewrite to use POST_INC/POST_DEC/POST_MODIFY instead of a scratch pointer. (ia64_secondary_reload_class): Delete case GR_REGS. * config/ia64/ia64.md (movti, *movti_internal, movtf, *movtf_internal): Do not allocate a scratch register. (reload_inti, reload_outti, reload_intf, reload_outtf): Delete. From-SVN: r76798
This commit is contained in:
Zack Weinberg
parent
f15f99a14e
commit
2ffe0e0241
@ -1,3 +1,14 @@
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2004-01-28 Zack Weinberg <zack@codesourcery.com>
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Jim Wilson <wilson@specifixinc.com>
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* config/ia64/ia64.c (ia64_split_tmode, ia64_split_tmode_move):
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Rewrite to use POST_INC/POST_DEC/POST_MODIFY instead of a
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scratch pointer.
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(ia64_secondary_reload_class): Delete case GR_REGS.
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* config/ia64/ia64.md (movti, *movti_internal, movtf, *movtf_internal):
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Do not allocate a scratch register.
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(reload_inti, reload_outti, reload_intf, reload_outtf): Delete.
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2004-01-28 Jan Hubicka <jh@suse.cz>
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* gcse.c (bypass_block): Prevent edges to be unified when we are
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@ -43,7 +54,7 @@
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* config/s390/s390.h (TARGET_DEFAULT): Default to !TARGET_BACKCHAIN.
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* config/s390/s390.c (s390_return_addr_rtx): Fail for all but current
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frame if !TARGET_BACKCHAIN.
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* config/s390/s390.md ("allocate_stack"): Use pattern only if
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* config/s390/s390.md ("allocate_stack"): Use pattern only if
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TARGET_BACKCHAIN.
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* doc/invoke.texi (-mbackchain/-mno-backchain): Document new default.
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@ -1395,62 +1395,37 @@ ia64_emit_cond_move (rtx op0, rtx op1, rtx cond)
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}
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/* Split a post-reload TImode or TFmode reference into two DImode
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components. */
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components. This is made extra difficult by the fact that we do
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not get any scratch registers to work with, because reload cannot
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be prevented from giving us a scratch that overlaps the register
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pair involved. So instead, when addressing memory, we tweak the
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pointer register up and back down with POST_INCs. Or up and not
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back down when we can get away with it.
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REVERSED is true when the loads must be done in reversed order
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(high word first) for correctness. DEAD is true when the pointer
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dies with the second insn we generate and therefore the second
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address must not carry a postmodify.
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May return an insn which is to be emitted after the moves. */
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static rtx
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ia64_split_tmode (rtx out[2], rtx in, rtx scratch)
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ia64_split_tmode (rtx out[2], rtx in, bool reversed, bool dead)
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{
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rtx fixup = 0;
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switch (GET_CODE (in))
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{
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case REG:
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out[0] = gen_rtx_REG (DImode, REGNO (in));
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out[1] = gen_rtx_REG (DImode, REGNO (in) + 1);
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return NULL_RTX;
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case MEM:
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{
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rtx base = XEXP (in, 0);
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switch (GET_CODE (base))
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{
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case REG:
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out[0] = adjust_address (in, DImode, 0);
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break;
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case POST_MODIFY:
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base = XEXP (base, 0);
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out[0] = adjust_address (in, DImode, 0);
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break;
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/* Since we're changing the mode, we need to change to POST_MODIFY
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as well to preserve the size of the increment. Either that or
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do the update in two steps, but we've already got this scratch
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register handy so let's use it. */
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case POST_INC:
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base = XEXP (base, 0);
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out[0]
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= change_address (in, DImode,
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gen_rtx_POST_MODIFY
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(Pmode, base, plus_constant (base, 16)));
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break;
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case POST_DEC:
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base = XEXP (base, 0);
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out[0]
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= change_address (in, DImode,
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gen_rtx_POST_MODIFY
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(Pmode, base, plus_constant (base, -16)));
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break;
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default:
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abort ();
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}
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if (scratch == NULL_RTX)
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abort ();
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out[1] = change_address (in, DImode, scratch);
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return gen_adddi3 (scratch, base, GEN_INT (8));
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}
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out[reversed] = gen_rtx_REG (DImode, REGNO (in));
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out[!reversed] = gen_rtx_REG (DImode, REGNO (in) + 1);
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break;
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case CONST_INT:
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case CONST_DOUBLE:
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/* Cannot occur reversed. */
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if (reversed) abort ();
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if (GET_MODE (in) != TFmode)
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split_double (in, &out[0], &out[1]);
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else
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@ -1477,11 +1452,108 @@ ia64_split_tmode (rtx out[2], rtx in, rtx scratch)
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out[0] = GEN_INT (p[0]);
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out[1] = GEN_INT (p[1]);
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}
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return NULL_RTX;
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break;
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case MEM:
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{
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rtx base = XEXP (in, 0);
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rtx offset;
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switch (GET_CODE (base))
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{
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case REG:
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if (!reversed)
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{
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out[0] = adjust_automodify_address
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(in, DImode, gen_rtx_POST_INC (Pmode, base), 0);
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out[1] = adjust_automodify_address
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(in, DImode, dead ? 0 : gen_rtx_POST_DEC (Pmode, base), 8);
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}
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else
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{
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/* Reversal requires a pre-increment, which can only
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be done as a separate insn. */
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emit_insn (gen_adddi3 (base, base, GEN_INT (8)));
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out[0] = adjust_automodify_address
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(in, DImode, gen_rtx_POST_DEC (Pmode, base), 8);
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out[1] = adjust_address (in, DImode, 0);
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}
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break;
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case POST_INC:
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if (reversed || dead) abort ();
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/* Just do the increment in two steps. */
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out[0] = adjust_automodify_address (in, DImode, 0, 0);
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out[1] = adjust_automodify_address (in, DImode, 0, 8);
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break;
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case POST_DEC:
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if (reversed || dead) abort ();
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/* Add 8, subtract 24. */
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base = XEXP (base, 0);
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out[0] = adjust_automodify_address
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(in, DImode, gen_rtx_POST_INC (Pmode, base), 0);
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out[1] = adjust_automodify_address
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(in, DImode,
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gen_rtx_POST_MODIFY (Pmode, base, plus_constant (base, -24)),
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8);
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break;
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case POST_MODIFY:
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if (reversed || dead) abort ();
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/* Extract and adjust the modification. This case is
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trickier than the others, because we might have an
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index register, or we might have a combined offset that
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doesn't fit a signed 9-bit displacement field. We can
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assume the incoming expression is already legitimate. */
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offset = XEXP (base, 1);
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base = XEXP (base, 0);
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out[0] = adjust_automodify_address
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(in, DImode, gen_rtx_POST_INC (Pmode, base), 0);
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if (GET_CODE (XEXP (offset, 1)) == REG)
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{
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/* Can't adjust the postmodify to match. Emit the
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original, then a separate addition insn. */
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out[1] = adjust_automodify_address (in, DImode, 0, 8);
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fixup = gen_adddi3 (base, base, GEN_INT (-8));
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}
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else if (GET_CODE (XEXP (offset, 1)) != CONST_INT)
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abort ();
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else if (INTVAL (XEXP (offset, 1)) < -256 + 8)
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{
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/* Again the postmodify cannot be made to match, but
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in this case it's more efficient to get rid of the
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postmodify entirely and fix up with an add insn. */
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out[1] = adjust_automodify_address (in, DImode, base, 8);
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fixup = gen_adddi3 (base, base,
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GEN_INT (INTVAL (XEXP (offset, 1)) - 8));
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}
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else
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{
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/* Combined offset still fits in the displacement field.
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(We cannot overflow it at the high end.) */
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out[1] = adjust_automodify_address
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(in, DImode,
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gen_rtx_POST_MODIFY (Pmode, base,
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gen_rtx_PLUS (Pmode, base,
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GEN_INT (INTVAL (XEXP (offset, 1)) - 8))),
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8);
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}
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break;
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default:
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abort ();
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}
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break;
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}
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default:
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abort ();
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}
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return fixup;
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}
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/* Split a TImode or TFmode move instruction after reload.
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@ -1489,39 +1561,60 @@ ia64_split_tmode (rtx out[2], rtx in, rtx scratch)
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void
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ia64_split_tmode_move (rtx operands[])
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{
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rtx adj1, adj2, in[2], out[2], insn;
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int first;
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rtx in[2], out[2], insn;
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rtx fixup[2];
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bool dead = false;
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bool reversed = false;
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adj1 = ia64_split_tmode (in, operands[1], operands[2]);
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adj2 = ia64_split_tmode (out, operands[0], operands[2]);
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first = 0;
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if (reg_overlap_mentioned_p (out[0], in[1]))
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/* It is possible for reload to decide to overwrite a pointer with
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the value it points to. In that case we have to do the loads in
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the appropriate order so that the pointer is not destroyed too
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early. Also we must not generate a postmodify for that second
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load, or rws_access_regno will abort. */
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if (GET_CODE (operands[1]) == MEM
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&& reg_overlap_mentioned_p (operands[0], operands[1]))
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{
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if (reg_overlap_mentioned_p (out[1], in[0]))
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abort ();
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first = 1;
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rtx base = XEXP (operands[1], 0);
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while (GET_CODE (base) != REG)
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base = XEXP (base, 0);
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if (REGNO (base) == REGNO (operands[0]))
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reversed = true;
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dead = true;
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}
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/* Another reason to do the moves in reversed order is if the first
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element of the target register pair is also the second element of
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the source register pair. */
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if (GET_CODE (operands[0]) == REG && GET_CODE (operands[1]) == REG
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&& REGNO (operands[0]) == REGNO (operands[1]) + 1)
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reversed = true;
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if (adj1 && adj2)
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abort ();
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if (adj1)
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emit_insn (adj1);
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if (adj2)
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emit_insn (adj2);
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insn = emit_insn (gen_rtx_SET (VOIDmode, out[first], in[first]));
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if (GET_CODE (out[first]) == MEM
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&& GET_CODE (XEXP (out[first], 0)) == POST_MODIFY)
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REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_INC,
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XEXP (XEXP (out[first], 0), 0),
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REG_NOTES (insn));
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insn = emit_insn (gen_rtx_SET (VOIDmode, out[!first], in[!first]));
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if (GET_CODE (out[!first]) == MEM
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&& GET_CODE (XEXP (out[!first], 0)) == POST_MODIFY)
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REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_INC,
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XEXP (XEXP (out[!first], 0), 0),
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REG_NOTES (insn));
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fixup[0] = ia64_split_tmode (in, operands[1], reversed, dead);
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fixup[1] = ia64_split_tmode (out, operands[0], reversed, dead);
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#define MAYBE_ADD_REG_INC_NOTE(INSN, EXP) \
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if (GET_CODE (EXP) == MEM \
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&& (GET_CODE (XEXP (EXP, 0)) == POST_MODIFY \
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|| GET_CODE (XEXP (EXP, 0)) == POST_INC \
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|| GET_CODE (XEXP (EXP, 0)) == POST_DEC)) \
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REG_NOTES (INSN) = gen_rtx_EXPR_LIST (REG_INC, \
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XEXP (XEXP (EXP, 0), 0), \
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REG_NOTES (INSN))
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insn = emit_insn (gen_rtx_SET (VOIDmode, out[0], in[0]));
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MAYBE_ADD_REG_INC_NOTE (insn, in[0]);
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MAYBE_ADD_REG_INC_NOTE (insn, out[0]);
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insn = emit_insn (gen_rtx_SET (VOIDmode, out[1], in[1]));
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MAYBE_ADD_REG_INC_NOTE (insn, in[1]);
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MAYBE_ADD_REG_INC_NOTE (insn, out[1]);
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if (fixup[0])
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emit_insn (fixup[0]);
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if (fixup[1])
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emit_insn (fixup[1]);
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#undef MAYBE_ADD_REG_INC_NOTE
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}
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/* ??? Fixing GR->FR XFmode moves during reload is hard. You need to go
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@ -4492,13 +4585,6 @@ ia64_secondary_reload_class (enum reg_class class,
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return GR_REGS;
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break;
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case GR_REGS:
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/* Since we have no offsettable memory addresses, we need a temporary
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to hold the address of the second word. */
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if (mode == TImode || mode == TFmode)
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return GR_REGS;
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break;
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default:
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break;
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}
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@ -584,11 +584,12 @@
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[(set_attr "itanium_class" "ialu")])
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;; With no offsettable memory references, we've got to have a scratch
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;; around to play with the second word.
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;; around to play with the second word. However, in order to avoid a
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;; reload nightmare we lie, claim we don't need one, and fix it up
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;; in ia64_split_tmode_move.
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(define_expand "movti"
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[(parallel [(set (match_operand:TI 0 "general_operand" "")
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(match_operand:TI 1 "general_operand" ""))
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(clobber (match_scratch:DI 2 ""))])]
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[(set (match_operand:TI 0 "general_operand" "")
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(match_operand:TI 1 "general_operand" ""))]
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""
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{
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rtx op1 = ia64_expand_move (operands[0], operands[1]);
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@ -599,8 +600,7 @@
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(define_insn_and_split "*movti_internal"
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[(set (match_operand:TI 0 "nonimmediate_operand" "=r,r,m")
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(match_operand:TI 1 "general_operand" "ri,m,r"))
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(clobber (match_scratch:DI 2 "=X,&r,&r"))]
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(match_operand:TI 1 "general_operand" "ri,m,r"))]
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"ia64_move_ok (operands[0], operands[1])"
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"#"
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"reload_completed"
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@ -612,20 +612,6 @@
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[(set_attr "itanium_class" "unknown")
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(set_attr "predicable" "no")])
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(define_expand "reload_inti"
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[(parallel [(set (match_operand:TI 0 "register_operand" "=r")
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(match_operand:TI 1 "memory_operand" "m"))
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(clobber (match_operand:DI 2 "register_operand" "=&r"))])]
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""
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"")
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(define_expand "reload_outti"
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[(parallel [(set (match_operand:TI 0 "memory_operand" "=m")
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(match_operand:TI 1 "register_operand" "r"))
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(clobber (match_operand:DI 2 "register_operand" "=&r"))])]
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""
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"")
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;; Floating Point Moves
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;;
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;; Note - Patterns for SF mode moves are compulsory, but
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@ -764,13 +750,10 @@
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[(set_attr "itanium_class" "fmisc,fld,stf")])
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;; Better code generation via insns that deal with TFmode register pairs
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;; directly.
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;; With no offsettable memory references, we've got to have a scratch
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;; around to play with the second word.
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;; directly. Same concerns apply as for TImode.
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(define_expand "movtf"
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[(parallel [(set (match_operand:TF 0 "general_operand" "")
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(match_operand:TF 1 "general_operand" ""))
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(clobber (match_scratch:DI 2 ""))])]
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[(set (match_operand:TF 0 "general_operand" "")
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(match_operand:TF 1 "general_operand" ""))]
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""
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{
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rtx op1 = ia64_expand_move (operands[0], operands[1]);
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@ -781,8 +764,7 @@
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(define_insn_and_split "*movtf_internal"
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[(set (match_operand:TF 0 "nonimmediate_operand" "=r,r,m")
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(match_operand:TF 1 "general_operand" "ri,m,r"))
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(clobber (match_scratch:DI 2 "=X,&r,&r"))]
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(match_operand:TF 1 "general_operand" "ri,m,r"))]
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"ia64_move_ok (operands[0], operands[1])"
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"#"
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"reload_completed"
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@ -794,19 +776,6 @@
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[(set_attr "itanium_class" "unknown")
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(set_attr "predicable" "no")])
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(define_expand "reload_intf"
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[(parallel [(set (match_operand:TF 0 "register_operand" "=r")
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(match_operand:TF 1 "memory_operand" "m"))
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(clobber (match_operand:DI 2 "register_operand" "=&r"))])]
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""
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"")
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(define_expand "reload_outtf"
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[(parallel [(set (match_operand:TF 0 "memory_operand" "=m")
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(match_operand:TF 1 "register_operand" "r"))
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(clobber (match_operand:DI 2 "register_operand" "=&r"))])]
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""
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"")
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;; ::::::::::::::::::::
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;; ::
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Reference in New Issue
Block a user