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bfin.md (addpdi3, [...]): New patterns.

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* config/bfin/bfin.md (addpdi3, us_truncpdisi2): New patterns.
	(umulsi3_highpart): Use them.
	* config/bfin/lib1funcs.asm (__umulsi3_highpart): Use unsigned move
	for final accumulator to D regisster tranfser.

From-SVN: r124376
This commit is contained in:
Bernd Schmidt 2007-05-03 13:17:51 +00:00 committed by Bernd Schmidt
parent cb9ed5d79f
commit 314f99131f
3 changed files with 26 additions and 2 deletions
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7
gcc/ChangeLog
View File

@ -1,3 +1,10 @@
2007-05-03 Bernd Schmidt <bernd.schmidt@analog.com>
* config/bfin/bfin.md (addpdi3, us_truncpdisi2): New patterns.
(umulsi3_highpart): Use them.
* config/bfin/lib1funcs.asm (__umulsi3_highpart): Use unsigned move
for final accumulator to D regisster tranfser.
2007-05-03 Dorit Nuzman <dorit@il.ibm.com>
PR tree-optimization/31699

18
gcc/config/bfin/bfin.md
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@ -1227,6 +1227,14 @@
;; Accumulator addition
(define_insn "addpdi3"
[(set (match_operand:PDI 0 "register_operand" "=A")
(ss_plus:PDI (match_operand:PDI 1 "register_operand" "%0")
(match_operand:PDI 2 "nonmemory_operand" "B")))]
""
"A0 += A1%!"
[(set_attr "type" "dsp32")])
(define_insn "sum_of_accumulators"
[(set (match_operand:SI 0 "register_operand" "=d")
(ss_truncate:SI
@ -1238,6 +1246,13 @@
"%0 = (A0 += A1)%!"
[(set_attr "type" "dsp32")])
(define_insn "us_truncpdisi2"
[(set (match_operand:SI 0 "register_operand" "=D,W")
(us_truncate:SI (match_operand:PDI 1 "register_operand" "A,B")))]
""
"%0 = %1 (FU)%!"
[(set_attr "type" "dsp32")])
;; Bit test instructions
(define_insn "*not_bittst"
@ -1501,7 +1516,8 @@
const1_rtx, const0_rtx,
a1reg, const0_rtx, GEN_INT (MACFLAG_FU)));
emit_insn (gen_lshrpdi3 (a1reg, a1reg, GEN_INT (16)));
emit_insn (gen_sum_of_accumulators (operands[0], a0reg, a0reg, a1reg));
emit_insn (gen_addpdi3 (a0reg, a0reg, a1reg));
emit_insn (gen_us_truncpdisi2 (operands[0], a0reg));
}
else
{

3
gcc/config/bfin/lib1funcs.asm
View File

@ -128,7 +128,8 @@ ___umulsi3_highpart:
A0 = R1.H * R0.H, A1 += R1.L * R0.H (FU);
A1 += R0.L * R1.H (FU);
A1 = A1 >> 16;
R0 = (A0 += A1);
A0 += A1;
R0 = A0 (FU);
RTS;
#endif