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[rtlanal.c] Convert conditional compilation on WORD_REGISTER_OPERATIONS 

* rtlanal.c (nonzero_bits1): Convert preprocessor check
	for WORD_REGISTER_OPERATIONS to runtime check.

From-SVN: r235512
This commit is contained in:
Kyrylo Tkachov 2016-04-27 14:38:10 +00:00 committed by Kyrylo Tkachov
parent 72ed2b9c76
commit 317d98872b
2 changed files with 11 additions and 5 deletions
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5
gcc/ChangeLog
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@ -1,3 +1,8 @@
2016-04-27 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* rtlanal.c (nonzero_bits1): Convert preprocessor check
for WORD_REGISTER_OPERATIONS to runtime check.
2016-04-27 Richard Biener <rguenther@suse.de>
PR ipa/70760

11
gcc/rtlanal.c
View File

@ -4584,13 +4584,14 @@ nonzero_bits1 (const_rtx x, machine_mode mode, const_rtx known_x,
nonzero &= cached_nonzero_bits (SUBREG_REG (x), mode,
known_x, known_mode, known_ret);
#if WORD_REGISTER_OPERATIONS && defined (LOAD_EXTEND_OP)
#ifdef LOAD_EXTEND_OP
/* If this is a typical RISC machine, we only have to worry
about the way loads are extended. */
if ((LOAD_EXTEND_OP (inner_mode) == SIGN_EXTEND
? val_signbit_known_set_p (inner_mode, nonzero)
: LOAD_EXTEND_OP (inner_mode) != ZERO_EXTEND)
|| !MEM_P (SUBREG_REG (x)))
if (WORD_REGISTER_OPERATIONS
&& ((LOAD_EXTEND_OP (inner_mode) == SIGN_EXTEND
? val_signbit_known_set_p (inner_mode, nonzero)
: LOAD_EXTEND_OP (inner_mode) != ZERO_EXTEND)
|| !MEM_P (SUBREG_REG (x))))
#endif
{
/* On many CISC machines, accessing an object in a wider mode