arm.c (neon_immediate_valid_for_shift): New function.
2011-06-22 Dmitry Plotnikov <dplotnikov@ispras.ru> Dmitry Melnik <dm@ispras.ru> * config/arm/arm.c (neon_immediate_valid_for_shift): New function. (neon_output_shift_immediate): Ditto. * config/arm/arm-protos.h (neon_immediate_valid_for_shift): New prototype. (neon_output_shift_immediate): Ditto. * config/arm/neon.md (vashl<mode>3): Modified constraint. (vashr<mode>3_imm): New insn pattern. (vlshr<mode>3_imm): Ditto. (vashr<mode>3): Modified constraint. (vlshr<mode>3): Ditto. * config/arm/predicates.md (imm_for_neon_lshift_operand): New predicate. (imm_for_neon_rshift_operand): Ditto. (imm_lshift_or_reg_neon): Ditto. (imm_rshift_or_reg_neon): Ditto. * optabs.c (init_optabs): Init optab codes for vashl, vashr, vlshr. testsuite: * gcc.target/arm/neon-vshr-imm-1.c: New testcase. * gcc.target/arm/neon-vshl-imm-1.c: New testcase. * gcc.target/arm/neon-vlshr-imm-1.c: New testcase. Co-Authored-By: Dmitry Melnik <dm@ispras.ru> From-SVN: r175293
This commit is contained in:
Dmitry Plotnikov
Alexander Monakov
parent
1da9434b4b
commit
31a0c8251b
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@ -1,3 +1,24 @@
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2011-06-22 Dmitry Plotnikov <dplotnikov@ispras.ru>
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Dmitry Melnik <dm@ispras.ru>
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* config/arm/arm.c (neon_immediate_valid_for_shift): New function.
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(neon_output_shift_immediate): Ditto.
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* config/arm/arm-protos.h (neon_immediate_valid_for_shift): New
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prototype.
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(neon_output_shift_immediate): Ditto.
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* config/arm/neon.md (vashl<mode>3): Modified constraint.
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(vashr<mode>3_imm): New insn pattern.
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(vlshr<mode>3_imm): Ditto.
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(vashr<mode>3): Modified constraint.
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(vlshr<mode>3): Ditto.
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* config/arm/predicates.md (imm_for_neon_lshift_operand): New
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predicate.
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(imm_for_neon_rshift_operand): Ditto.
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(imm_lshift_or_reg_neon): Ditto.
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(imm_rshift_or_reg_neon): Ditto.
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* optabs.c (init_optabs): Init optab codes for vashl, vashr, vlshr.
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2011-06-22 Jakub Jelinek <jakub@redhat.com>
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* tree-ssa-ccp.c (evaluate_stmt): Try bitwise tracking for
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@ -66,8 +66,12 @@ extern int vfp3_const_double_rtx (rtx);
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extern int neon_immediate_valid_for_move (rtx, enum machine_mode, rtx *, int *);
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extern int neon_immediate_valid_for_logic (rtx, enum machine_mode, int, rtx *,
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int *);
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extern int neon_immediate_valid_for_shift (rtx, enum machine_mode, rtx *,
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int *, bool);
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extern char *neon_output_logic_immediate (const char *, rtx *,
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enum machine_mode, int, int);
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extern char *neon_output_shift_immediate (const char *, char, rtx *,
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enum machine_mode, int, bool);
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extern void neon_pairwise_reduce (rtx, rtx, enum machine_mode,
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rtx (*) (rtx, rtx, rtx));
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extern rtx neon_make_constant (rtx);
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@ -8608,6 +8608,66 @@ neon_immediate_valid_for_logic (rtx op, enum machine_mode mode, int inverse,
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return 1;
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}
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/* Return TRUE if rtx OP is legal for use in a VSHR or VSHL instruction. If
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the immediate is valid, write a constant suitable for using as an operand
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to VSHR/VSHL to *MODCONST and the corresponding element width to
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*ELEMENTWIDTH. ISLEFTSHIFT is for determine left or right shift,
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because they have different limitations. */
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int
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neon_immediate_valid_for_shift (rtx op, enum machine_mode mode,
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rtx *modconst, int *elementwidth,
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bool isleftshift)
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{
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unsigned int innersize = GET_MODE_SIZE (GET_MODE_INNER (mode));
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unsigned int n_elts = CONST_VECTOR_NUNITS (op), i;
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unsigned HOST_WIDE_INT last_elt = 0;
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unsigned HOST_WIDE_INT maxshift;
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/* Split vector constant out into a byte vector. */
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for (i = 0; i < n_elts; i++)
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{
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rtx el = CONST_VECTOR_ELT (op, i);
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unsigned HOST_WIDE_INT elpart;
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if (GET_CODE (el) == CONST_INT)
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elpart = INTVAL (el);
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else if (GET_CODE (el) == CONST_DOUBLE)
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return 0;
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else
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gcc_unreachable ();
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if (i != 0 && elpart != last_elt)
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return 0;
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last_elt = elpart;
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}
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/* Shift less than element size. */
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maxshift = innersize * 8;
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if (isleftshift)
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{
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/* Left shift immediate value can be from 0 to <size>-1. */
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if (last_elt >= maxshift)
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return 0;
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}
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else
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{
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/* Right shift immediate value can be from 1 to <size>. */
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if (last_elt == 0 || last_elt > maxshift)
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return 0;
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}
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if (elementwidth)
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*elementwidth = innersize * 8;
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if (modconst)
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*modconst = CONST_VECTOR_ELT (op, 0);
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return 1;
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}
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/* Return a string suitable for output of Neon immediate logic operation
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MNEM. */
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@ -8630,6 +8690,28 @@ neon_output_logic_immediate (const char *mnem, rtx *op2, enum machine_mode mode,
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return templ;
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}
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/* Return a string suitable for output of Neon immediate shift operation
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(VSHR or VSHL) MNEM. */
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char *
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neon_output_shift_immediate (const char *mnem, char sign, rtx *op2,
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enum machine_mode mode, int quad,
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bool isleftshift)
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{
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int width, is_valid;
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static char templ[40];
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is_valid = neon_immediate_valid_for_shift (*op2, mode, op2, &width, isleftshift);
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gcc_assert (is_valid != 0);
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if (quad)
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sprintf (templ, "%s.%c%d\t%%q0, %%q1, %%2", mnem, sign, width);
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else
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sprintf (templ, "%s.%c%d\t%%P0, %%P1, %%2", mnem, sign, width);
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return templ;
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}
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/* Output a sequence of pairwise operations to implement a reduction.
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NOTE: We do "too much work" here, because pairwise operations work on two
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registers-worth of operands in one go. Unfortunately we can't exploit those
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@ -969,17 +969,59 @@
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; SImode elements.
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(define_insn "vashl<mode>3"
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[(set (match_operand:VDQIW 0 "s_register_operand" "=w")
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(ashift:VDQIW (match_operand:VDQIW 1 "s_register_operand" "w")
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(match_operand:VDQIW 2 "s_register_operand" "w")))]
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[(set (match_operand:VDQIW 0 "s_register_operand" "=w,w")
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(ashift:VDQIW (match_operand:VDQIW 1 "s_register_operand" "w,w")
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(match_operand:VDQIW 2 "imm_lshift_or_reg_neon" "w,Dn")))]
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"TARGET_NEON"
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"vshl.<V_s_elem>\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
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{
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switch (which_alternative)
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{
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case 0: return "vshl.<V_s_elem>\t%<V_reg>0, %<V_reg>1, %<V_reg>2";
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case 1: return neon_output_shift_immediate ("vshl", 'i', &operands[2],
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<MODE>mode,
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VALID_NEON_QREG_MODE (<MODE>mode),
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true);
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default: gcc_unreachable ();
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}
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}
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[(set (attr "neon_type")
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(if_then_else (ne (symbol_ref "<Is_d_reg>") (const_int 0))
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(const_string "neon_vshl_ddd")
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(const_string "neon_shift_3")))]
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)
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(define_insn "vashr<mode>3_imm"
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[(set (match_operand:VDQIW 0 "s_register_operand" "=w")
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(ashiftrt:VDQIW (match_operand:VDQIW 1 "s_register_operand" "w")
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(match_operand:VDQIW 2 "imm_for_neon_rshift_operand" "Dn")))]
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"TARGET_NEON"
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{
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return neon_output_shift_immediate ("vshr", 's', &operands[2],
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<MODE>mode, VALID_NEON_QREG_MODE (<MODE>mode),
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false);
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}
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[(set (attr "neon_type")
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(if_then_else (ne (symbol_ref "<Is_d_reg>") (const_int 0))
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(const_string "neon_vshl_ddd")
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(const_string "neon_shift_3")))]
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)
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(define_insn "vlshr<mode>3_imm"
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[(set (match_operand:VDQIW 0 "s_register_operand" "=w")
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(lshiftrt:VDQIW (match_operand:VDQIW 1 "s_register_operand" "w")
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(match_operand:VDQIW 2 "imm_for_neon_rshift_operand" "Dn")))]
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"TARGET_NEON"
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{
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return neon_output_shift_immediate ("vshr", 'u', &operands[2],
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<MODE>mode, VALID_NEON_QREG_MODE (<MODE>mode),
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false);
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}
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[(set (attr "neon_type")
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(if_then_else (ne (symbol_ref "<Is_d_reg>") (const_int 0))
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(const_string "neon_vshl_ddd")
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(const_string "neon_shift_3")))]
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)
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; Used for implementing logical shift-right, which is a left-shift by a negative
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; amount, with signed operands. This is essentially the same as ashl<mode>3
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; above, but using an unspec in case GCC tries anything tricky with negative
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@ -1017,28 +1059,34 @@
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(define_expand "vashr<mode>3"
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[(set (match_operand:VDQIW 0 "s_register_operand" "")
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(ashiftrt:VDQIW (match_operand:VDQIW 1 "s_register_operand" "")
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(match_operand:VDQIW 2 "s_register_operand" "")))]
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(match_operand:VDQIW 2 "imm_rshift_or_reg_neon" "")))]
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"TARGET_NEON"
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{
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rtx neg = gen_reg_rtx (<MODE>mode);
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emit_insn (gen_neg<mode>2 (neg, operands[2]));
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emit_insn (gen_ashl<mode>3_signed (operands[0], operands[1], neg));
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if (REG_P (operands[2]))
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{
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emit_insn (gen_neg<mode>2 (neg, operands[2]));
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emit_insn (gen_ashl<mode>3_signed (operands[0], operands[1], neg));
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}
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else
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emit_insn (gen_vashr<mode>3_imm (operands[0], operands[1], operands[2]));
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DONE;
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})
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(define_expand "vlshr<mode>3"
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[(set (match_operand:VDQIW 0 "s_register_operand" "")
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(lshiftrt:VDQIW (match_operand:VDQIW 1 "s_register_operand" "")
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(match_operand:VDQIW 2 "s_register_operand" "")))]
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(match_operand:VDQIW 2 "imm_rshift_or_reg_neon" "")))]
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"TARGET_NEON"
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{
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rtx neg = gen_reg_rtx (<MODE>mode);
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emit_insn (gen_neg<mode>2 (neg, operands[2]));
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emit_insn (gen_ashl<mode>3_unsigned (operands[0], operands[1], neg));
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if (REG_P (operands[2]))
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{
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emit_insn (gen_neg<mode>2 (neg, operands[2]));
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emit_insn (gen_ashl<mode>3_unsigned (operands[0], operands[1], neg));
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}
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else
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emit_insn (gen_vlshr<mode>3_imm (operands[0], operands[1], operands[2]));
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DONE;
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})
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@ -585,6 +585,26 @@
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return neon_immediate_valid_for_move (op, mode, NULL, NULL);
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})
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(define_predicate "imm_for_neon_lshift_operand"
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(match_code "const_vector")
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{
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return neon_immediate_valid_for_shift (op, mode, NULL, NULL, true);
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})
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(define_predicate "imm_for_neon_rshift_operand"
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(match_code "const_vector")
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{
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return neon_immediate_valid_for_shift (op, mode, NULL, NULL, false);
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})
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(define_predicate "imm_lshift_or_reg_neon"
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(ior (match_operand 0 "s_register_operand")
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(match_operand 0 "imm_for_neon_lshift_operand")))
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(define_predicate "imm_rshift_or_reg_neon"
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(ior (match_operand 0 "s_register_operand")
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(match_operand 0 "imm_for_neon_rshift_operand")))
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(define_predicate "imm_for_neon_logic_operand"
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(match_code "const_vector")
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{
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@ -5925,6 +5925,9 @@ init_optabs (void)
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init_optab (usashl_optab, US_ASHIFT);
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init_optab (ashr_optab, ASHIFTRT);
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init_optab (lshr_optab, LSHIFTRT);
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init_optabv (vashl_optab, ASHIFT);
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init_optabv (vashr_optab, ASHIFTRT);
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init_optabv (vlshr_optab, LSHIFTRT);
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init_optab (rotl_optab, ROTATE);
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init_optab (rotr_optab, ROTATERT);
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init_optab (smin_optab, SMIN);
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@ -1,3 +1,10 @@
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2011-06-22 Dmitry Plotnikov <dplotnikov@ispras.ru>
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Dmitry Melnik <dm@ispras.ru>
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* gcc.target/arm/neon-vshr-imm-1.c: New testcase.
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* gcc.target/arm/neon-vshl-imm-1.c: New testcase.
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* gcc.target/arm/neon-vlshr-imm-1.c: New testcase.
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2011-06-22 Uros Bizjak <ubizjak@gmail.com>
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* gcc.dg/torture/tls/run-le.c: Skip for -pie on alpha*-*-linux*.
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@ -0,0 +1,11 @@
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/* { dg-do compile } */
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/* { dg-require-effective-target arm_neon_ok } */
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/* { dg-options "-O2 -mfpu=neon -mfloat-abi=softfp -ftree-vectorize" } */
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/* { dg-final { scan-assembler "vshr\.u32.*#3" } } */
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/* Verify that VSHR immediate is used. */
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void f1(int n, unsigned int x[], unsigned int y[]) {
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int i;
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for (i = 0; i < n; ++i)
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y[i] = x[i] >> 3;
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}
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@ -0,0 +1,11 @@
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/* { dg-do compile } */
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/* { dg-require-effective-target arm_neon_ok } */
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/* { dg-options "-O2 -mfpu=neon -mfloat-abi=softfp -ftree-vectorize" } */
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/* { dg-final { scan-assembler "vshl\.i32.*#3" } } */
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/* Verify that VSHR immediate is used. */
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void f1(int n, int x[], int y[]) {
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int i;
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for (i = 0; i < n; ++i)
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y[i] = x[i] << 3;
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}
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@ -0,0 +1,11 @@
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/* { dg-do compile } */
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/* { dg-require-effective-target arm_neon_ok } */
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/* { dg-options "-O2 -mfpu=neon -mfloat-abi=softfp -ftree-vectorize" } */
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/* { dg-final { scan-assembler "vshr\.s32.*#3" } } */
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/* Verify that VSHR immediate is used. */
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void f1(int n, int x[], int y[]) {
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int i;
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for (i = 0; i < n; ++i)
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y[i] = x[i] >> 3;
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}
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