arm.md (arm_mulsi3_v6): Add alternative for 16-bit encoding.
2013-06-28 Kyrylo Tkachov <kyrylo.tkachov@arm.com> * config/arm/arm.md (arm_mulsi3_v6): Add alternative for 16-bit encoding. (mulsi3addsi_v6): Disable predicable variant for arm_restrict_it. (mulsi3subsi): Likewise. (mulsidi3adddi): Likewise. (mulsidi3_v6): Likewise. (umulsidi3_v6): Likewise. (umulsidi3adddi_v6): Likewise. (smulsi3_highpart_v6): Likewise. (umulsi3_highpart_v6): Likewise. (mulhisi3tb): Likewise. (mulhisi3bt): Likewise. (mulhisi3tt): Likewise. (maddhisi4): Likewise. (maddhisi4tb): Likewise. (maddhisi4tt): Likewise. (maddhidi4): Likewise. (maddhidi4tb): Likewise. (maddhidi4tt): Likewise. (zeroextractsi_compare0_scratch): Likewise. (insv_zero): Likewise. (insv_t2): Likewise. (anddi_notzesidi_di): Likewise. (anddi_notsesidi_di): Likewise. (andsi_notsi_si): Likewise. (iordi_zesidi_di): Likewise. (xordi_zesidi_di): Likewise. (andsi_iorsi3_notsi): Likewise. (smax_0): Likewise. (smax_m1): Likewise. (smin_0): Likewise. (not_shiftsi): Likewise. (unaligned_loadsi): Likewise. (unaligned_loadhis): Likewise. (unaligned_loadhiu): Likewise. (unaligned_storesi): Likewise. (unaligned_storehi): Likewise. (extv_reg): Likewise. (extzv_t2): Likewise. (divsi3): Likewise. (udivsi3): Likewise. (arm_zero_extendhisi2addsi): Likewise. (arm_zero_extendqisi2addsi): Likewise. (compareqi_eq0): Likewise. (arm_extendhisi2_v6): Likewise. (arm_extendqisi2addsi): Likewise. (arm_movt): Likewise. (thumb2_ldrd): Likewise. (thumb2_ldrd_base): Likewise. (thumb2_ldrd_base_neg): Likewise. (thumb2_strd): Likewise. (thumb2_strd_base): Likewise. (thumb2_strd_base_neg): Likewise. (arm_negsi2): Add alternative for 16-bit encoding. (arm_one_cmplsi2): Likewise. From-SVN: r200513
This commit is contained in:
Kyrylo Tkachov
Kyrylo Tkachov
parent
ee429bdfe0
commit
31dfce1008
@ -1,3 +1,61 @@
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2013-06-28 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
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* config/arm/arm.md (arm_mulsi3_v6): Add alternative for 16-bit
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encoding.
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(mulsi3addsi_v6): Disable predicable variant for arm_restrict_it.
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(mulsi3subsi): Likewise.
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(mulsidi3adddi): Likewise.
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(mulsidi3_v6): Likewise.
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(umulsidi3_v6): Likewise.
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(umulsidi3adddi_v6): Likewise.
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(smulsi3_highpart_v6): Likewise.
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(umulsi3_highpart_v6): Likewise.
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(mulhisi3tb): Likewise.
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(mulhisi3bt): Likewise.
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(mulhisi3tt): Likewise.
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(maddhisi4): Likewise.
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(maddhisi4tb): Likewise.
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(maddhisi4tt): Likewise.
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(maddhidi4): Likewise.
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(maddhidi4tb): Likewise.
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(maddhidi4tt): Likewise.
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(zeroextractsi_compare0_scratch): Likewise.
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(insv_zero): Likewise.
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(insv_t2): Likewise.
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(anddi_notzesidi_di): Likewise.
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(anddi_notsesidi_di): Likewise.
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(andsi_notsi_si): Likewise.
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(iordi_zesidi_di): Likewise.
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(xordi_zesidi_di): Likewise.
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(andsi_iorsi3_notsi): Likewise.
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(smax_0): Likewise.
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(smax_m1): Likewise.
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(smin_0): Likewise.
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(not_shiftsi): Likewise.
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(unaligned_loadsi): Likewise.
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(unaligned_loadhis): Likewise.
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(unaligned_loadhiu): Likewise.
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(unaligned_storesi): Likewise.
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(unaligned_storehi): Likewise.
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(extv_reg): Likewise.
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(extzv_t2): Likewise.
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(divsi3): Likewise.
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(udivsi3): Likewise.
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(arm_zero_extendhisi2addsi): Likewise.
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(arm_zero_extendqisi2addsi): Likewise.
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(compareqi_eq0): Likewise.
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(arm_extendhisi2_v6): Likewise.
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(arm_extendqisi2addsi): Likewise.
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(arm_movt): Likewise.
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(thumb2_ldrd): Likewise.
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(thumb2_ldrd_base): Likewise.
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(thumb2_ldrd_base_neg): Likewise.
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(thumb2_strd): Likewise.
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(thumb2_strd_base): Likewise.
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(thumb2_strd_base_neg): Likewise.
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(arm_negsi2): Add alternative for 16-bit encoding.
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(arm_one_cmplsi2): Likewise.
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2013-06-28 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
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* config/arm/predicates.md (arm_cond_move_operator): New predicate.
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@ -1565,13 +1565,16 @@
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)
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(define_insn "*arm_mulsi3_v6"
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[(set (match_operand:SI 0 "s_register_operand" "=r")
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(mult:SI (match_operand:SI 1 "s_register_operand" "r")
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(match_operand:SI 2 "s_register_operand" "r")))]
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[(set (match_operand:SI 0 "s_register_operand" "=l,l,r")
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(mult:SI (match_operand:SI 1 "s_register_operand" "0,l,r")
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(match_operand:SI 2 "s_register_operand" "l,0,r")))]
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"TARGET_32BIT && arm_arch6"
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"mul%?\\t%0, %1, %2"
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[(set_attr "type" "mul")
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(set_attr "predicable" "yes")]
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(set_attr "predicable" "yes")
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(set_attr "arch" "t2,t2,*")
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(set_attr "length" "4")
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(set_attr "predicable_short_it" "yes,yes,no")]
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)
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; Unfortunately with the Thumb the '&'/'0' trick can fails when operands
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@ -1684,7 +1687,8 @@
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"TARGET_32BIT && arm_arch6"
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"mla%?\\t%0, %2, %1, %3"
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[(set_attr "type" "mla")
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(set_attr "predicable" "yes")]
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(set_attr "predicable" "yes")
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(set_attr "predicable_short_it" "no")]
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)
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(define_insn "*mulsi3addsi_compare0"
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@ -1760,7 +1764,8 @@
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"TARGET_32BIT && arm_arch_thumb2"
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"mls%?\\t%0, %2, %1, %3"
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[(set_attr "type" "mla")
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(set_attr "predicable" "yes")]
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(set_attr "predicable" "yes")
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(set_attr "predicable_short_it" "no")]
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)
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(define_expand "maddsidi4"
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@ -1796,7 +1801,8 @@
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"TARGET_32BIT && arm_arch6"
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"smlal%?\\t%Q0, %R0, %3, %2"
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[(set_attr "type" "smlal")
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(set_attr "predicable" "yes")]
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(set_attr "predicable" "yes")
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(set_attr "predicable_short_it" "no")]
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)
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;; 32x32->64 widening multiply.
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@ -1833,7 +1839,8 @@
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"TARGET_32BIT && arm_arch6"
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"smull%?\\t%Q0, %R0, %1, %2"
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[(set_attr "type" "smull")
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(set_attr "predicable" "yes")]
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(set_attr "predicable" "yes")
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(set_attr "predicable_short_it" "no")]
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)
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(define_expand "umulsidi3"
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@ -1864,7 +1871,8 @@
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"TARGET_32BIT && arm_arch6"
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"umull%?\\t%Q0, %R0, %1, %2"
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[(set_attr "type" "umull")
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(set_attr "predicable" "yes")]
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(set_attr "predicable" "yes")
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(set_attr "predicable_short_it" "no")]
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)
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(define_expand "umaddsidi4"
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@ -1900,7 +1908,8 @@
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"TARGET_32BIT && arm_arch6"
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"umlal%?\\t%Q0, %R0, %3, %2"
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[(set_attr "type" "umlal")
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(set_attr "predicable" "yes")]
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(set_attr "predicable" "yes")
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(set_attr "predicable_short_it" "no")]
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)
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(define_expand "smulsi3_highpart"
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@ -1944,7 +1953,8 @@
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"TARGET_32BIT && arm_arch6"
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"smull%?\\t%3, %0, %2, %1"
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[(set_attr "type" "smull")
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(set_attr "predicable" "yes")]
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(set_attr "predicable" "yes")
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(set_attr "predicable_short_it" "no")]
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)
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(define_expand "umulsi3_highpart"
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@ -1988,7 +1998,8 @@
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"TARGET_32BIT && arm_arch6"
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"umull%?\\t%3, %0, %2, %1"
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[(set_attr "type" "umull")
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(set_attr "predicable" "yes")]
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(set_attr "predicable" "yes")
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(set_attr "predicable_short_it" "no")]
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)
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(define_insn "mulhisi3"
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@ -2013,7 +2024,8 @@
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"TARGET_DSP_MULTIPLY"
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"smultb%?\\t%0, %1, %2"
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[(set_attr "type" "smulxy")
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(set_attr "predicable" "yes")]
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(set_attr "predicable" "yes")
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(set_attr "predicable_short_it" "no")]
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)
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(define_insn "*mulhisi3bt"
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@ -2026,7 +2038,8 @@
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"TARGET_DSP_MULTIPLY"
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"smulbt%?\\t%0, %1, %2"
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[(set_attr "type" "smulxy")
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(set_attr "predicable" "yes")]
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(set_attr "predicable" "yes")
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(set_attr "predicable_short_it" "no")]
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)
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(define_insn "*mulhisi3tt"
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@ -2040,7 +2053,8 @@
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"TARGET_DSP_MULTIPLY"
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"smultt%?\\t%0, %1, %2"
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[(set_attr "type" "smulxy")
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(set_attr "predicable" "yes")]
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(set_attr "predicable" "yes")
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(set_attr "predicable_short_it" "no")]
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)
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(define_insn "maddhisi4"
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@ -2053,7 +2067,8 @@
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"TARGET_DSP_MULTIPLY"
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"smlabb%?\\t%0, %1, %2, %3"
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[(set_attr "type" "smlaxy")
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(set_attr "predicable" "yes")]
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(set_attr "predicable" "yes")
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(set_attr "predicable_short_it" "no")]
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)
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;; Note: there is no maddhisi4ibt because this one is canonical form
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@ -2068,7 +2083,8 @@
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"TARGET_DSP_MULTIPLY"
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"smlatb%?\\t%0, %1, %2, %3"
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[(set_attr "type" "smlaxy")
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(set_attr "predicable" "yes")]
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(set_attr "predicable" "yes")
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(set_attr "predicable_short_it" "no")]
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)
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(define_insn "*maddhisi4tt"
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@ -2083,21 +2099,23 @@
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"TARGET_DSP_MULTIPLY"
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"smlatt%?\\t%0, %1, %2, %3"
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[(set_attr "type" "smlaxy")
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(set_attr "predicable" "yes")]
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(set_attr "predicable" "yes")
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(set_attr "predicable_short_it" "no")]
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)
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(define_insn "maddhidi4"
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[(set (match_operand:DI 0 "s_register_operand" "=r")
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(plus:DI
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(mult:DI (sign_extend:DI
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(match_operand:HI 1 "s_register_operand" "r"))
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(match_operand:HI 1 "s_register_operand" "r"))
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(sign_extend:DI
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(match_operand:HI 2 "s_register_operand" "r")))
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(match_operand:DI 3 "s_register_operand" "0")))]
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"TARGET_DSP_MULTIPLY"
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"smlalbb%?\\t%Q0, %R0, %1, %2"
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[(set_attr "type" "smlalxy")
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(set_attr "predicable" "yes")])
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(set_attr "predicable" "yes")
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(set_attr "predicable_short_it" "no")])
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;; Note: there is no maddhidi4ibt because this one is canonical form
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(define_insn "*maddhidi4tb"
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@ -2113,7 +2131,8 @@
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"TARGET_DSP_MULTIPLY"
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"smlaltb%?\\t%Q0, %R0, %1, %2"
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[(set_attr "type" "smlalxy")
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(set_attr "predicable" "yes")])
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(set_attr "predicable" "yes")
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(set_attr "predicable_short_it" "no")])
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(define_insn "*maddhidi4tt"
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[(set (match_operand:DI 0 "s_register_operand" "=r")
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@ -2130,7 +2149,8 @@
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"TARGET_DSP_MULTIPLY"
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"smlaltt%?\\t%Q0, %R0, %1, %2"
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[(set_attr "type" "smlalxy")
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(set_attr "predicable" "yes")])
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(set_attr "predicable" "yes")
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(set_attr "predicable_short_it" "no")])
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(define_expand "mulsf3"
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[(set (match_operand:SF 0 "s_register_operand" "")
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@ -2486,7 +2506,7 @@
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[(set (reg:CC_NOOV CC_REGNUM)
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(compare:CC_NOOV (zero_extract:SI
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(match_operand:SI 0 "s_register_operand" "r")
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(match_operand 1 "const_int_operand" "n")
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(match_operand 1 "const_int_operand" "n")
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(match_operand 2 "const_int_operand" "n"))
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(const_int 0)))]
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"TARGET_32BIT
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@ -2502,6 +2522,7 @@
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"
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[(set_attr "conds" "set")
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(set_attr "predicable" "yes")
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(set_attr "predicable_short_it" "no")
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(set_attr "type" "simple_alu_imm")]
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)
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@ -2929,7 +2950,8 @@
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"arm_arch_thumb2"
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"bfc%?\t%0, %2, %1"
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[(set_attr "length" "4")
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(set_attr "predicable" "yes")]
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(set_attr "predicable" "yes")
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(set_attr "predicable_short_it" "no")]
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)
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(define_insn "insv_t2"
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@ -2940,7 +2962,8 @@
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"arm_arch_thumb2"
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"bfi%?\t%0, %3, %2, %1"
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[(set_attr "length" "4")
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(set_attr "predicable" "yes")]
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(set_attr "predicable" "yes")
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(set_attr "predicable_short_it" "no")]
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)
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; constants for op 2 will never be given to these patterns.
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@ -2967,7 +2990,7 @@
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[(set_attr "length" "8")
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(set_attr "predicable" "yes")]
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)
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(define_insn_and_split "*anddi_notzesidi_di"
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[(set (match_operand:DI 0 "s_register_operand" "=&r,&r")
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(and:DI (not:DI (zero_extend:DI
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@ -2992,9 +3015,10 @@
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operands[1] = gen_lowpart (SImode, operands[1]);
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}"
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[(set_attr "length" "4,8")
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(set_attr "predicable" "yes")]
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(set_attr "predicable" "yes")
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(set_attr "predicable_short_it" "no")]
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)
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(define_insn_and_split "*anddi_notsesidi_di"
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[(set (match_operand:DI 0 "s_register_operand" "=&r,&r")
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(and:DI (not:DI (sign_extend:DI
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@ -3015,16 +3039,18 @@
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operands[1] = gen_lowpart (SImode, operands[1]);
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}"
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[(set_attr "length" "8")
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(set_attr "predicable" "yes")]
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(set_attr "predicable" "yes")
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(set_attr "predicable_short_it" "no")]
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)
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(define_insn "andsi_notsi_si"
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[(set (match_operand:SI 0 "s_register_operand" "=r")
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(and:SI (not:SI (match_operand:SI 2 "s_register_operand" "r"))
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(match_operand:SI 1 "s_register_operand" "r")))]
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"TARGET_32BIT"
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"bic%?\\t%0, %1, %2"
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[(set_attr "predicable" "yes")]
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[(set_attr "predicable" "yes")
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(set_attr "predicable_short_it" "no")]
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)
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(define_insn "thumb1_bicsi3"
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@ -3137,7 +3163,8 @@
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orr%?\\t%Q0, %Q1, %2
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#"
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[(set_attr "length" "4,8")
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(set_attr "predicable" "yes")]
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(set_attr "predicable" "yes")
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(set_attr "predicable_short_it" "no")]
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)
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(define_insn "*iordi_sesidi_di"
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@ -3312,7 +3339,8 @@
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eor%?\\t%Q0, %Q1, %2
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#"
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[(set_attr "length" "4,8")
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(set_attr "predicable" "yes")]
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(set_attr "predicable" "yes")
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(set_attr "predicable_short_it" "no")]
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)
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(define_insn "*xordi_sesidi_di"
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@ -3442,7 +3470,8 @@
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""
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[(set_attr "length" "8")
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(set_attr "ce_count" "2")
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(set_attr "predicable" "yes")]
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(set_attr "predicable" "yes")
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(set_attr "predicable_short_it" "no")]
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)
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; ??? Are these four splitters still beneficial when the Thumb-2 bitfield
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@ -3578,7 +3607,8 @@
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(const_int 0)))]
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"TARGET_32BIT"
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"bic%?\\t%0, %1, %1, asr #31"
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[(set_attr "predicable" "yes")]
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[(set_attr "predicable" "yes")
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(set_attr "predicable_short_it" "no")]
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||||
)
|
||||
|
||||
(define_insn "*smax_m1"
|
||||
@ -3587,7 +3617,8 @@
|
||||
(const_int -1)))]
|
||||
"TARGET_32BIT"
|
||||
"orr%?\\t%0, %1, %1, asr #31"
|
||||
[(set_attr "predicable" "yes")]
|
||||
[(set_attr "predicable" "yes")
|
||||
(set_attr "predicable_short_it" "no")]
|
||||
)
|
||||
|
||||
(define_insn_and_split "*arm_smax_insn"
|
||||
@ -3635,7 +3666,8 @@
|
||||
(const_int 0)))]
|
||||
"TARGET_32BIT"
|
||||
"and%?\\t%0, %1, %1, asr #31"
|
||||
[(set_attr "predicable" "yes")]
|
||||
[(set_attr "predicable" "yes")
|
||||
(set_attr "predicable_short_it" "no")]
|
||||
)
|
||||
|
||||
(define_insn_and_split "*arm_smin_insn"
|
||||
@ -4310,6 +4342,7 @@
|
||||
"TARGET_32BIT"
|
||||
"mvn%?\\t%0, %1%S3"
|
||||
[(set_attr "predicable" "yes")
|
||||
(set_attr "predicable_short_it" "no")
|
||||
(set_attr "shift" "1")
|
||||
(set_attr "insn" "mvn")
|
||||
(set_attr "arch" "32,a")
|
||||
@ -4523,6 +4556,7 @@
|
||||
[(set_attr "arch" "t2,any")
|
||||
(set_attr "length" "2,4")
|
||||
(set_attr "predicable" "yes")
|
||||
(set_attr "predicable_short_it" "yes,no")
|
||||
(set_attr "type" "load1")])
|
||||
|
||||
(define_insn "unaligned_loadhis"
|
||||
@ -4535,6 +4569,7 @@
|
||||
[(set_attr "arch" "t2,any")
|
||||
(set_attr "length" "2,4")
|
||||
(set_attr "predicable" "yes")
|
||||
(set_attr "predicable_short_it" "yes,no")
|
||||
(set_attr "type" "load_byte")])
|
||||
|
||||
(define_insn "unaligned_loadhiu"
|
||||
@ -4547,6 +4582,7 @@
|
||||
[(set_attr "arch" "t2,any")
|
||||
(set_attr "length" "2,4")
|
||||
(set_attr "predicable" "yes")
|
||||
(set_attr "predicable_short_it" "yes,no")
|
||||
(set_attr "type" "load_byte")])
|
||||
|
||||
(define_insn "unaligned_storesi"
|
||||
@ -4558,6 +4594,7 @@
|
||||
[(set_attr "arch" "t2,any")
|
||||
(set_attr "length" "2,4")
|
||||
(set_attr "predicable" "yes")
|
||||
(set_attr "predicable_short_it" "yes,no")
|
||||
(set_attr "type" "store1")])
|
||||
|
||||
(define_insn "unaligned_storehi"
|
||||
@ -4569,6 +4606,7 @@
|
||||
[(set_attr "arch" "t2,any")
|
||||
(set_attr "length" "2,4")
|
||||
(set_attr "predicable" "yes")
|
||||
(set_attr "predicable_short_it" "yes,no")
|
||||
(set_attr "type" "store1")])
|
||||
|
||||
;; Unaligned double-word load and store.
|
||||
@ -4637,7 +4675,8 @@
|
||||
"arm_arch_thumb2"
|
||||
"sbfx%?\t%0, %1, %3, %2"
|
||||
[(set_attr "length" "4")
|
||||
(set_attr "predicable" "yes")]
|
||||
(set_attr "predicable" "yes")
|
||||
(set_attr "predicable_short_it" "no")]
|
||||
)
|
||||
|
||||
(define_insn "extzv_t2"
|
||||
@ -4648,7 +4687,8 @@
|
||||
"arm_arch_thumb2"
|
||||
"ubfx%?\t%0, %1, %3, %2"
|
||||
[(set_attr "length" "4")
|
||||
(set_attr "predicable" "yes")]
|
||||
(set_attr "predicable" "yes")
|
||||
(set_attr "predicable_short_it" "no")]
|
||||
)
|
||||
|
||||
|
||||
@ -4660,6 +4700,7 @@
|
||||
"TARGET_IDIV"
|
||||
"sdiv%?\t%0, %1, %2"
|
||||
[(set_attr "predicable" "yes")
|
||||
(set_attr "predicable_short_it" "no")
|
||||
(set_attr "type" "sdiv")]
|
||||
)
|
||||
|
||||
@ -4670,6 +4711,7 @@
|
||||
"TARGET_IDIV"
|
||||
"udiv%?\t%0, %1, %2"
|
||||
[(set_attr "predicable" "yes")
|
||||
(set_attr "predicable_short_it" "no")
|
||||
(set_attr "type" "udiv")]
|
||||
)
|
||||
|
||||
@ -4732,11 +4774,14 @@
|
||||
)
|
||||
|
||||
(define_insn "*arm_negsi2"
|
||||
[(set (match_operand:SI 0 "s_register_operand" "=r")
|
||||
(neg:SI (match_operand:SI 1 "s_register_operand" "r")))]
|
||||
[(set (match_operand:SI 0 "s_register_operand" "=l,r")
|
||||
(neg:SI (match_operand:SI 1 "s_register_operand" "l,r")))]
|
||||
"TARGET_32BIT"
|
||||
"rsb%?\\t%0, %1, #0"
|
||||
[(set_attr "predicable" "yes")]
|
||||
[(set_attr "predicable" "yes")
|
||||
(set_attr "predicable_short_it" "yes,no")
|
||||
(set_attr "arch" "t2,*")
|
||||
(set_attr "length" "4")]
|
||||
)
|
||||
|
||||
(define_insn "*thumb1_negsi2"
|
||||
@ -5054,11 +5099,14 @@
|
||||
)
|
||||
|
||||
(define_insn "*arm_one_cmplsi2"
|
||||
[(set (match_operand:SI 0 "s_register_operand" "=r")
|
||||
(not:SI (match_operand:SI 1 "s_register_operand" "r")))]
|
||||
[(set (match_operand:SI 0 "s_register_operand" "=l,r")
|
||||
(not:SI (match_operand:SI 1 "s_register_operand" "l,r")))]
|
||||
"TARGET_32BIT"
|
||||
"mvn%?\\t%0, %1"
|
||||
[(set_attr "predicable" "yes")
|
||||
(set_attr "predicable_short_it" "yes,no")
|
||||
(set_attr "arch" "t2,*")
|
||||
(set_attr "length" "4")
|
||||
(set_attr "insn" "mvn")]
|
||||
)
|
||||
|
||||
@ -5384,7 +5432,8 @@
|
||||
"TARGET_INT_SIMD"
|
||||
"uxtah%?\\t%0, %2, %1"
|
||||
[(set_attr "type" "alu_shift")
|
||||
(set_attr "predicable" "yes")]
|
||||
(set_attr "predicable" "yes")
|
||||
(set_attr "predicable_short_it" "no")]
|
||||
)
|
||||
|
||||
(define_expand "zero_extendqisi2"
|
||||
@ -5477,6 +5526,7 @@
|
||||
"TARGET_INT_SIMD"
|
||||
"uxtab%?\\t%0, %2, %1"
|
||||
[(set_attr "predicable" "yes")
|
||||
(set_attr "predicable_short_it" "no")
|
||||
(set_attr "insn" "xtab")
|
||||
(set_attr "type" "alu_shift")]
|
||||
)
|
||||
@ -5529,7 +5579,8 @@
|
||||
"TARGET_32BIT"
|
||||
"tst%?\\t%0, #255"
|
||||
[(set_attr "conds" "set")
|
||||
(set_attr "predicable" "yes")]
|
||||
(set_attr "predicable" "yes")
|
||||
(set_attr "predicable_short_it" "no")]
|
||||
)
|
||||
|
||||
(define_expand "extendhisi2"
|
||||
@ -5715,6 +5766,7 @@
|
||||
ldr%(sh%)\\t%0, %1"
|
||||
[(set_attr "type" "simple_alu_shift,load_byte")
|
||||
(set_attr "predicable" "yes")
|
||||
(set_attr "predicable_short_it" "no")
|
||||
(set_attr "pool_range" "*,256")
|
||||
(set_attr "neg_pool_range" "*,244")]
|
||||
)
|
||||
@ -5827,7 +5879,8 @@
|
||||
"sxtab%?\\t%0, %2, %1"
|
||||
[(set_attr "type" "alu_shift")
|
||||
(set_attr "insn" "xtab")
|
||||
(set_attr "predicable" "yes")]
|
||||
(set_attr "predicable" "yes")
|
||||
(set_attr "predicable_short_it" "no")]
|
||||
)
|
||||
|
||||
(define_split
|
||||
@ -6283,6 +6336,7 @@
|
||||
"arm_arch_thumb2"
|
||||
"movt%?\t%0, #:upper16:%c2"
|
||||
[(set_attr "predicable" "yes")
|
||||
(set_attr "predicable_short_it" "no")
|
||||
(set_attr "length" "4")]
|
||||
)
|
||||
|
||||
@ -12586,7 +12640,8 @@
|
||||
false, true))"
|
||||
"ldrd%?\t%0, %3, [%1, %2]"
|
||||
[(set_attr "type" "load2")
|
||||
(set_attr "predicable" "yes")])
|
||||
(set_attr "predicable" "yes")
|
||||
(set_attr "predicable_short_it" "no")])
|
||||
|
||||
(define_insn "*thumb2_ldrd_base"
|
||||
[(set (match_operand:SI 0 "s_register_operand" "=r")
|
||||
@ -12600,7 +12655,8 @@
|
||||
operands[1], 0, false, true))"
|
||||
"ldrd%?\t%0, %2, [%1]"
|
||||
[(set_attr "type" "load2")
|
||||
(set_attr "predicable" "yes")])
|
||||
(set_attr "predicable" "yes")
|
||||
(set_attr "predicable_short_it" "no")])
|
||||
|
||||
(define_insn "*thumb2_ldrd_base_neg"
|
||||
[(set (match_operand:SI 0 "s_register_operand" "=r")
|
||||
@ -12614,7 +12670,8 @@
|
||||
operands[1], -4, false, true))"
|
||||
"ldrd%?\t%0, %2, [%1, #-4]"
|
||||
[(set_attr "type" "load2")
|
||||
(set_attr "predicable" "yes")])
|
||||
(set_attr "predicable" "yes")
|
||||
(set_attr "predicable_short_it" "no")])
|
||||
|
||||
(define_insn "*thumb2_strd"
|
||||
[(set (mem:SI (plus:SI (match_operand:SI 0 "s_register_operand" "rk")
|
||||
@ -12631,7 +12688,8 @@
|
||||
false, false))"
|
||||
"strd%?\t%2, %4, [%0, %1]"
|
||||
[(set_attr "type" "store2")
|
||||
(set_attr "predicable" "yes")])
|
||||
(set_attr "predicable" "yes")
|
||||
(set_attr "predicable_short_it" "no")])
|
||||
|
||||
(define_insn "*thumb2_strd_base"
|
||||
[(set (mem:SI (match_operand:SI 0 "s_register_operand" "rk"))
|
||||
@ -12645,7 +12703,8 @@
|
||||
operands[0], 0, false, false))"
|
||||
"strd%?\t%1, %2, [%0]"
|
||||
[(set_attr "type" "store2")
|
||||
(set_attr "predicable" "yes")])
|
||||
(set_attr "predicable" "yes")
|
||||
(set_attr "predicable_short_it" "no")])
|
||||
|
||||
(define_insn "*thumb2_strd_base_neg"
|
||||
[(set (mem:SI (plus:SI (match_operand:SI 0 "s_register_operand" "rk")
|
||||
@ -12659,7 +12718,8 @@
|
||||
operands[0], -4, false, false))"
|
||||
"strd%?\t%1, %2, [%0, #-4]"
|
||||
[(set_attr "type" "store2")
|
||||
(set_attr "predicable" "yes")])
|
||||
(set_attr "predicable" "yes")
|
||||
(set_attr "predicable_short_it" "no")])
|
||||
|
||||
|
||||
;; Load the load/store double peephole optimizations.
|
||||
|
||||
Loading…
Reference in New Issue
Block a user