extend.texi (MIPS DSP Built-in Functions): Document the DSP REV 2.
* doc/extend.texi (MIPS DSP Built-in Functions): Document the DSP REV 2. * doc/invoke.texi (-mdspr2): Document new option. * config/mips/mips.md (UNSPEC_ABSQ_S_QB .. UNSPEC_DPSQX_SA_W_PH): New unspec for DSP REV 2. (<u>mulsidi3_32bit_internal): Check if !TARGET_DSPR2, because these instructions are extended in DSP REV 2. (mips-dspr2.md): Include. * config/mips/mips.opt (mdspr2): New option. * config/mips/mips.c (mips_function_type): Add MIPS_V4QI_FTYPE_V4QI, MIPS_SI_FTYPE_SI_SI_SI, MIPS_DI_FTYPE_DI_USI_USI, MIPS_DI_FTYPE_SI_SI, MIPS_DI_FTYPE_USI_USI, MIPS_V2HI_FTYPE_SI_SI_SI. (override_options): Check TARGET_DSPR2 to enable MASK_DSP. (CODE_FOR_mips_mul_ph): Define it to CODE_FOR_mulv2hi3. (dsp_bdesc): Add DSP REV 2 builtins. Remove 32-bit only DSP builtins. (dsp_32only_bdesc): New description table for 32-bit only DSP REV 1 and 2 builtins. (bdesc_map): Add one field of unsupported_target_flags. (bdesc_arrays): Update entries to have extra fields. Add dsp_32only_bdesc. (mips_init_builtins): Initialize new function types. Check unsupported_target_fileds to filter out builtins. * config/mips/mips.h (TARGET_CPU_CPP_BUILTINS): Define __mips_dspr2 if TARGET_DSPR2. (ASM_SPEC): Pass mdspr2 to the assembler. * config/mips/mips-dspr2.md: New file. From-SVN: r122756
This commit is contained in:
Chao-ying Fu
Chao-ying Fu
parent
4a71edd9b8
commit
3204138527
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@ -1,3 +1,32 @@
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2007-03-09 Chao-ying Fu <fu@mips.com>
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* doc/extend.texi (MIPS DSP Built-in Functions): Document the DSP
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REV 2.
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* doc/invoke.texi (-mdspr2): Document new option.
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* config/mips/mips.md (UNSPEC_ABSQ_S_QB .. UNSPEC_DPSQX_SA_W_PH):
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New unspec for DSP REV 2.
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(<u>mulsidi3_32bit_internal): Check if !TARGET_DSPR2, because
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these instructions are extended in DSP REV 2.
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(mips-dspr2.md): Include.
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* config/mips/mips.opt (mdspr2): New option.
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* config/mips/mips.c (mips_function_type): Add MIPS_V4QI_FTYPE_V4QI,
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MIPS_SI_FTYPE_SI_SI_SI, MIPS_DI_FTYPE_DI_USI_USI, MIPS_DI_FTYPE_SI_SI,
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MIPS_DI_FTYPE_USI_USI, MIPS_V2HI_FTYPE_SI_SI_SI.
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(override_options): Check TARGET_DSPR2 to enable MASK_DSP.
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(CODE_FOR_mips_mul_ph): Define it to CODE_FOR_mulv2hi3.
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(dsp_bdesc): Add DSP REV 2 builtins. Remove 32-bit only DSP builtins.
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(dsp_32only_bdesc): New description table for 32-bit only DSP REV 1
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and 2 builtins.
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(bdesc_map): Add one field of unsupported_target_flags.
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(bdesc_arrays): Update entries to have extra fields. Add
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dsp_32only_bdesc.
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(mips_init_builtins): Initialize new function types.
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Check unsupported_target_fileds to filter out builtins.
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* config/mips/mips.h (TARGET_CPU_CPP_BUILTINS): Define __mips_dspr2 if
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TARGET_DSPR2.
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(ASM_SPEC): Pass mdspr2 to the assembler.
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* config/mips/mips-dspr2.md: New file.
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2007-03-09 Sa Liu <saliu@de.ibm.com>
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* config/rs6000/altivec.md: Fix vcond patterns using if_then_else.
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@ -0,0 +1,626 @@
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; MIPS DSP ASE REV 2 Revision 0.02 11/24/2006
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(define_insn "mips_absq_s_qb"
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[(parallel
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[(set (match_operand:V4QI 0 "register_operand" "=d")
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(unspec:V4QI [(match_operand:V4QI 1 "reg_or_0_operand" "dYG")]
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UNSPEC_ABSQ_S_QB))
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(set (reg:CCDSP CCDSP_OU_REGNUM)
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(unspec:CCDSP [(match_dup 1)] UNSPEC_ABSQ_S_QB))])]
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"TARGET_DSPR2"
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"absq_s.qb\t%0,%z1"
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[(set_attr "type" "arith")
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(set_attr "mode" "SI")])
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(define_insn "mips_addu_ph"
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[(parallel
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[(set (match_operand:V2HI 0 "register_operand" "=d")
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(plus:V2HI (match_operand:V2HI 1 "reg_or_0_operand" "dYG")
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(match_operand:V2HI 2 "reg_or_0_operand" "dYG")))
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(set (reg:CCDSP CCDSP_OU_REGNUM)
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(unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_ADDU_PH))])]
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"TARGET_DSPR2"
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"addu.ph\t%0,%z1,%z2"
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[(set_attr "type" "arith")
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(set_attr "mode" "SI")])
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(define_insn "mips_addu_s_ph"
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[(parallel
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[(set (match_operand:V2HI 0 "register_operand" "=d")
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(unspec:V2HI [(match_operand:V2HI 1 "reg_or_0_operand" "dYG")
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(match_operand:V2HI 2 "reg_or_0_operand" "dYG")]
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UNSPEC_ADDU_S_PH))
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(set (reg:CCDSP CCDSP_OU_REGNUM)
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(unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_ADDU_S_PH))])]
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"TARGET_DSPR2"
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"addu_s.ph\t%0,%z1,%z2"
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[(set_attr "type" "arith")
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(set_attr "mode" "SI")])
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(define_insn "mips_adduh_qb"
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[(set (match_operand:V4QI 0 "register_operand" "=d")
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(unspec:V4QI [(match_operand:V4QI 1 "reg_or_0_operand" "dYG")
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(match_operand:V4QI 2 "reg_or_0_operand" "dYG")]
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UNSPEC_ADDUH_QB))]
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"TARGET_DSPR2"
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"adduh.qb\t%0,%z1,%z2"
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[(set_attr "type" "arith")
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(set_attr "mode" "SI")])
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(define_insn "mips_adduh_r_qb"
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[(set (match_operand:V4QI 0 "register_operand" "=d")
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(unspec:V4QI [(match_operand:V4QI 1 "reg_or_0_operand" "dYG")
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(match_operand:V4QI 2 "reg_or_0_operand" "dYG")]
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UNSPEC_ADDUH_R_QB))]
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"TARGET_DSPR2"
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"adduh_r.qb\t%0,%z1,%z2"
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[(set_attr "type" "arith")
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(set_attr "mode" "SI")])
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(define_insn "mips_append"
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[(set (match_operand:SI 0 "register_operand" "=d")
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(unspec:SI [(match_operand:SI 1 "register_operand" "0")
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(match_operand:SI 2 "reg_or_0_operand" "dJ")
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(match_operand:SI 3 "const_int_operand" "n")]
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UNSPEC_APPEND))]
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"TARGET_DSPR2"
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{
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if (INTVAL (operands[3]) & ~(unsigned HOST_WIDE_INT) 31)
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operands[2] = GEN_INT (INTVAL (operands[2]) & 31);
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return "append\t%0,%z2,%3";
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}
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[(set_attr "type" "arith")
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(set_attr "mode" "SI")])
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(define_insn "mips_balign"
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[(set (match_operand:SI 0 "register_operand" "=d")
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(unspec:SI [(match_operand:SI 1 "register_operand" "0")
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(match_operand:SI 2 "reg_or_0_operand" "dJ")
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(match_operand:SI 3 "const_int_operand" "n")]
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UNSPEC_BALIGN))]
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"TARGET_DSPR2"
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{
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if (INTVAL (operands[3]) & ~(unsigned HOST_WIDE_INT) 3)
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operands[2] = GEN_INT (INTVAL (operands[2]) & 3);
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return "balign\t%0,%z2,%3";
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}
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[(set_attr "type" "arith")
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(set_attr "mode" "SI")])
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(define_insn "mips_cmpgdu_eq_qb"
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[(parallel
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[(set (match_operand:SI 0 "register_operand" "=d")
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(unspec:SI [(match_operand:V4QI 1 "reg_or_0_operand" "dYG")
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(match_operand:V4QI 2 "reg_or_0_operand" "dYG")]
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UNSPEC_CMPGDU_EQ_QB))
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(set (reg:CCDSP CCDSP_CC_REGNUM)
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(unspec:CCDSP [(match_dup 1) (match_dup 2)
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(reg:CCDSP CCDSP_CC_REGNUM)]
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UNSPEC_CMPGDU_EQ_QB))])]
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"TARGET_DSPR2"
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"cmpgdu.eq.qb\t%0,%z1,%z2"
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[(set_attr "type" "arith")
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(set_attr "mode" "SI")])
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(define_insn "mips_cmpgdu_lt_qb"
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[(parallel
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[(set (match_operand:SI 0 "register_operand" "=d")
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(unspec:SI [(match_operand:V4QI 1 "reg_or_0_operand" "dYG")
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(match_operand:V4QI 2 "reg_or_0_operand" "dYG")]
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UNSPEC_CMPGDU_LT_QB))
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(set (reg:CCDSP CCDSP_CC_REGNUM)
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(unspec:CCDSP [(match_dup 1) (match_dup 2)
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(reg:CCDSP CCDSP_CC_REGNUM)]
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UNSPEC_CMPGDU_LT_QB))])]
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"TARGET_DSPR2"
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"cmpgdu.lt.qb\t%0,%z1,%z2"
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[(set_attr "type" "arith")
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(set_attr "mode" "SI")])
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(define_insn "mips_cmpgdu_le_qb"
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[(parallel
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[(set (match_operand:SI 0 "register_operand" "=d")
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(unspec:SI [(match_operand:V4QI 1 "reg_or_0_operand" "dYG")
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(match_operand:V4QI 2 "reg_or_0_operand" "dYG")]
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UNSPEC_CMPGDU_LE_QB))
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(set (reg:CCDSP CCDSP_CC_REGNUM)
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(unspec:CCDSP [(match_dup 1) (match_dup 2)
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(reg:CCDSP CCDSP_CC_REGNUM)]
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UNSPEC_CMPGDU_LE_QB))])]
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"TARGET_DSPR2"
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"cmpgdu.le.qb\t%0,%z1,%z2"
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[(set_attr "type" "arith")
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(set_attr "mode" "SI")])
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(define_insn "mips_dpa_w_ph"
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[(set (match_operand:DI 0 "register_operand" "=a")
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(unspec:DI [(match_operand:DI 1 "register_operand" "0")
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(match_operand:V2HI 2 "reg_or_0_operand" "dYG")
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(match_operand:V2HI 3 "reg_or_0_operand" "dYG")]
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UNSPEC_DPA_W_PH))]
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"TARGET_DSPR2 && !TARGET_64BIT"
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"dpa.w.ph\t%q0,%z2,%z3"
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[(set_attr "type" "imadd")
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(set_attr "mode" "SI")])
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(define_insn "mips_dps_w_ph"
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[(set (match_operand:DI 0 "register_operand" "=a")
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(unspec:DI [(match_operand:DI 1 "register_operand" "0")
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(match_operand:V2HI 2 "reg_or_0_operand" "dYG")
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(match_operand:V2HI 3 "reg_or_0_operand" "dYG")]
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UNSPEC_DPS_W_PH))]
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"TARGET_DSPR2 && !TARGET_64BIT"
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"dps.w.ph\t%q0,%z2,%z3"
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[(set_attr "type" "imadd")
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(set_attr "mode" "SI")])
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(define_insn "mips_madd"
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[(set (match_operand:DI 0 "register_operand" "=a")
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(plus:DI
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(mult:DI (sign_extend:DI
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(match_operand:SI 2 "register_operand" "d"))
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(sign_extend:DI
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(match_operand:SI 3 "register_operand" "d")))
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(match_operand:DI 1 "register_operand" "0")))]
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"TARGET_DSPR2 && !TARGET_64BIT"
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"madd\t%q0,%2,%3"
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[(set_attr "type" "imadd")
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(set_attr "mode" "SI")])
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(define_insn "mips_maddu"
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[(set (match_operand:DI 0 "register_operand" "=a")
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(plus:DI
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(mult:DI (zero_extend:DI
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(match_operand:SI 2 "register_operand" "d"))
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(zero_extend:DI
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(match_operand:SI 3 "register_operand" "d")))
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(match_operand:DI 1 "register_operand" "0")))]
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"TARGET_DSPR2 && !TARGET_64BIT"
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"maddu\t%q0,%2,%3"
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[(set_attr "type" "imadd")
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(set_attr "mode" "SI")])
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(define_insn "mips_msub"
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[(set (match_operand:DI 0 "register_operand" "=a")
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(minus:DI
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(match_operand:DI 1 "register_operand" "0")
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(mult:DI (sign_extend:DI
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(match_operand:SI 2 "register_operand" "d"))
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(sign_extend:DI
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(match_operand:SI 3 "register_operand" "d")))))]
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"TARGET_DSPR2 && !TARGET_64BIT"
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"msub\t%q0,%2,%3"
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[(set_attr "type" "imadd")
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(set_attr "mode" "SI")])
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(define_insn "mips_msubu"
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[(set (match_operand:DI 0 "register_operand" "=a")
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(minus:DI
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(match_operand:DI 1 "register_operand" "0")
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(mult:DI (zero_extend:DI
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(match_operand:SI 2 "register_operand" "d"))
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(zero_extend:DI
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(match_operand:SI 3 "register_operand" "d")))))]
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"TARGET_DSPR2 && !TARGET_64BIT"
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"msubu\t%q0,%2,%3"
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[(set_attr "type" "imadd")
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(set_attr "mode" "SI")])
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(define_insn "mulv2hi3"
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[(parallel
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[(set (match_operand:V2HI 0 "register_operand" "=d")
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(mult:V2HI (match_operand:V2HI 1 "register_operand" "d")
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(match_operand:V2HI 2 "register_operand" "d")))
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(set (reg:CCDSP CCDSP_OU_REGNUM)
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(unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_MUL_PH))
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(clobber (match_scratch:DI 3 "=x"))])]
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"TARGET_DSPR2"
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"mul.ph\t%0,%1,%2"
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[(set_attr "type" "imul3")
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(set_attr "mode" "SI")])
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(define_insn "mips_mul_s_ph"
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[(parallel
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[(set (match_operand:V2HI 0 "register_operand" "=d")
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(unspec:V2HI [(match_operand:V2HI 1 "reg_or_0_operand" "dYG")
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(match_operand:V2HI 2 "reg_or_0_operand" "dYG")]
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UNSPEC_MUL_S_PH))
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(set (reg:CCDSP CCDSP_OU_REGNUM)
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(unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_MUL_S_PH))
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(clobber (match_scratch:DI 3 "=x"))])]
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"TARGET_DSPR2"
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"mul_s.ph\t%0,%z1,%z2"
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[(set_attr "type" "imul3")
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(set_attr "mode" "SI")])
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(define_insn "mips_mulq_rs_w"
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[(parallel
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[(set (match_operand:SI 0 "register_operand" "=d")
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(unspec:SI [(match_operand:SI 1 "reg_or_0_operand" "dJ")
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(match_operand:SI 2 "reg_or_0_operand" "dJ")]
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UNSPEC_MULQ_RS_W))
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(set (reg:CCDSP CCDSP_OU_REGNUM)
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(unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_MULQ_RS_W))
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(clobber (match_scratch:DI 3 "=x"))])]
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"TARGET_DSPR2"
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"mulq_rs.w\t%0,%z1,%z2"
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[(set_attr "type" "imul3")
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(set_attr "mode" "SI")])
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(define_insn "mips_mulq_s_ph"
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[(parallel
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[(set (match_operand:V2HI 0 "register_operand" "=d")
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(unspec:V2HI [(match_operand:V2HI 1 "reg_or_0_operand" "dYG")
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(match_operand:V2HI 2 "reg_or_0_operand" "dYG")]
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UNSPEC_MULQ_S_PH))
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(set (reg:CCDSP CCDSP_OU_REGNUM)
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(unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_MULQ_S_PH))
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(clobber (match_scratch:DI 3 "=x"))])]
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"TARGET_DSPR2"
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"mulq_s.ph\t%0,%z1,%z2"
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[(set_attr "type" "imul3")
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(set_attr "mode" "SI")])
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(define_insn "mips_mulq_s_w"
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[(parallel
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[(set (match_operand:SI 0 "register_operand" "=d")
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(unspec:SI [(match_operand:SI 1 "reg_or_0_operand" "dJ")
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(match_operand:SI 2 "reg_or_0_operand" "dJ")]
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UNSPEC_MULQ_S_W))
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(set (reg:CCDSP CCDSP_OU_REGNUM)
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(unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_MULQ_S_W))
|
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(clobber (match_scratch:DI 3 "=x"))])]
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"TARGET_DSPR2"
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"mulq_s.w\t%0,%z1,%z2"
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[(set_attr "type" "imul3")
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(set_attr "mode" "SI")])
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|
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(define_insn "mips_mulsa_w_ph"
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[(set (match_operand:DI 0 "register_operand" "=a")
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(unspec:DI [(match_operand:DI 1 "register_operand" "0")
|
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(match_operand:V2HI 2 "reg_or_0_operand" "dYG")
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(match_operand:V2HI 3 "reg_or_0_operand" "dYG")]
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UNSPEC_MULSA_W_PH))]
|
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"TARGET_DSPR2 && !TARGET_64BIT"
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"mulsa.w.ph\t%q0,%z2,%z3"
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[(set_attr "type" "imadd")
|
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(set_attr "mode" "SI")])
|
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|
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(define_insn "mips_mult"
|
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[(set (match_operand:DI 0 "register_operand" "=a")
|
||||
(mult:DI
|
||||
(sign_extend:DI (match_operand:SI 1 "register_operand" "d"))
|
||||
(sign_extend:DI (match_operand:SI 2 "register_operand" "d"))))]
|
||||
"TARGET_DSPR2 && !TARGET_64BIT"
|
||||
"mult\t%q0,%1,%2"
|
||||
[(set_attr "type" "imul")
|
||||
(set_attr "mode" "SI")])
|
||||
|
||||
(define_insn "mips_multu"
|
||||
[(set (match_operand:DI 0 "register_operand" "=a")
|
||||
(mult:DI
|
||||
(zero_extend:DI (match_operand:SI 1 "register_operand" "d"))
|
||||
(zero_extend:DI (match_operand:SI 2 "register_operand" "d"))))]
|
||||
"TARGET_DSPR2 && !TARGET_64BIT"
|
||||
"multu\t%q0,%1,%2"
|
||||
[(set_attr "type" "imul")
|
||||
(set_attr "mode" "SI")])
|
||||
|
||||
(define_insn "mips_precr_qb_ph"
|
||||
[(set (match_operand:V4QI 0 "register_operand" "=d")
|
||||
(unspec:V4QI [(match_operand:V2HI 1 "reg_or_0_operand" "dYG")
|
||||
(match_operand:V2HI 2 "reg_or_0_operand" "dYG")]
|
||||
UNSPEC_PRECR_QB_PH))]
|
||||
"TARGET_DSPR2"
|
||||
"precr.qb.ph\t%0,%z1,%z2"
|
||||
[(set_attr "type" "arith")
|
||||
(set_attr "mode" "SI")])
|
||||
|
||||
(define_insn "mips_precr_sra_ph_w"
|
||||
[(set (match_operand:V2HI 0 "register_operand" "=d")
|
||||
(unspec:V2HI [(match_operand:SI 1 "register_operand" "0")
|
||||
(match_operand:SI 2 "reg_or_0_operand" "dJ")
|
||||
(match_operand:SI 3 "const_int_operand" "n")]
|
||||
UNSPEC_PRECR_SRA_PH_W))]
|
||||
"TARGET_DSPR2"
|
||||
{
|
||||
if (INTVAL (operands[3]) & ~(unsigned HOST_WIDE_INT) 31)
|
||||
operands[2] = GEN_INT (INTVAL (operands[2]) & 31);
|
||||
return "precr_sra.ph.w\t%0,%z2,%3";
|
||||
}
|
||||
[(set_attr "type" "arith")
|
||||
(set_attr "mode" "SI")])
|
||||
|
||||
(define_insn "mips_precr_sra_r_ph_w"
|
||||
[(set (match_operand:V2HI 0 "register_operand" "=d")
|
||||
(unspec:V2HI [(match_operand:SI 1 "register_operand" "0")
|
||||
(match_operand:SI 2 "reg_or_0_operand" "dJ")
|
||||
(match_operand:SI 3 "const_int_operand" "n")]
|
||||
UNSPEC_PRECR_SRA_R_PH_W))]
|
||||
"TARGET_DSPR2"
|
||||
{
|
||||
if (INTVAL (operands[3]) & ~(unsigned HOST_WIDE_INT) 31)
|
||||
operands[2] = GEN_INT (INTVAL (operands[2]) & 31);
|
||||
return "precr_sra_r.ph.w\t%0,%z2,%3";
|
||||
}
|
||||
[(set_attr "type" "arith")
|
||||
(set_attr "mode" "SI")])
|
||||
|
||||
(define_insn "mips_prepend"
|
||||
[(set (match_operand:SI 0 "register_operand" "=d")
|
||||
(unspec:SI [(match_operand:SI 1 "register_operand" "0")
|
||||
(match_operand:SI 2 "reg_or_0_operand" "dJ")
|
||||
(match_operand:SI 3 "const_int_operand" "n")]
|
||||
UNSPEC_PREPEND))]
|
||||
"TARGET_DSPR2"
|
||||
{
|
||||
if (INTVAL (operands[3]) & ~(unsigned HOST_WIDE_INT) 31)
|
||||
operands[2] = GEN_INT (INTVAL (operands[2]) & 31);
|
||||
return "prepend\t%0,%z2,%3";
|
||||
}
|
||||
[(set_attr "type" "arith")
|
||||
(set_attr "mode" "SI")])
|
||||
|
||||
(define_insn "mips_shra_qb"
|
||||
[(set (match_operand:V4QI 0 "register_operand" "=d,d")
|
||||
(unspec:V4QI [(match_operand:V4QI 1 "reg_or_0_operand" "dYG,dYG")
|
||||
(match_operand:SI 2 "arith_operand" "I,d")]
|
||||
UNSPEC_SHRA_QB))]
|
||||
"TARGET_DSPR2"
|
||||
{
|
||||
if (which_alternative == 0)
|
||||
{
|
||||
if (INTVAL (operands[2]) & ~(unsigned HOST_WIDE_INT) 7)
|
||||
operands[2] = GEN_INT (INTVAL (operands[2]) & 7);
|
||||
return "shra.qb\t%0,%z1,%2";
|
||||
}
|
||||
return "shrav.qb\t%0,%z1,%2";
|
||||
}
|
||||
[(set_attr "type" "shift")
|
||||
(set_attr "mode" "SI")])
|
||||
|
||||
|
||||
(define_insn "mips_shra_r_qb"
|
||||
[(set (match_operand:V4QI 0 "register_operand" "=d,d")
|
||||
(unspec:V4QI [(match_operand:V4QI 1 "reg_or_0_operand" "dYG,dYG")
|
||||
(match_operand:SI 2 "arith_operand" "I,d")]
|
||||
UNSPEC_SHRA_R_QB))]
|
||||
"TARGET_DSPR2"
|
||||
{
|
||||
if (which_alternative == 0)
|
||||
{
|
||||
if (INTVAL (operands[2]) & ~(unsigned HOST_WIDE_INT) 7)
|
||||
operands[2] = GEN_INT (INTVAL (operands[2]) & 7);
|
||||
return "shra_r.qb\t%0,%z1,%2";
|
||||
}
|
||||
return "shrav_r.qb\t%0,%z1,%2";
|
||||
}
|
||||
[(set_attr "type" "shift")
|
||||
(set_attr "mode" "SI")])
|
||||
|
||||
(define_insn "mips_shrl_ph"
|
||||
[(set (match_operand:V2HI 0 "register_operand" "=d,d")
|
||||
(unspec:V2HI [(match_operand:V2HI 1 "reg_or_0_operand" "dYG,dYG")
|
||||
(match_operand:SI 2 "arith_operand" "I,d")]
|
||||
UNSPEC_SHRL_PH))]
|
||||
"TARGET_DSPR2"
|
||||
{
|
||||
if (which_alternative == 0)
|
||||
{
|
||||
if (INTVAL (operands[2]) & ~(unsigned HOST_WIDE_INT) 15)
|
||||
operands[2] = GEN_INT (INTVAL (operands[2]) & 15);
|
||||
return "shrl.ph\t%0,%z1,%2";
|
||||
}
|
||||
return "shrlv.ph\t%0,%z1,%2";
|
||||
}
|
||||
[(set_attr "type" "shift")
|
||||
(set_attr "mode" "SI")])
|
||||
|
||||
(define_insn "mips_subu_ph"
|
||||
[(parallel
|
||||
[(set (match_operand:V2HI 0 "register_operand" "=d")
|
||||
(unspec:V2HI [(match_operand:V2HI 1 "reg_or_0_operand" "dYG")
|
||||
(match_operand:V2HI 2 "reg_or_0_operand" "dYG")]
|
||||
UNSPEC_SUBU_PH))
|
||||
(set (reg:CCDSP CCDSP_OU_REGNUM)
|
||||
(unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_SUBU_PH))])]
|
||||
"TARGET_DSPR2"
|
||||
"subu.ph\t%0,%z1,%z2"
|
||||
[(set_attr "type" "arith")
|
||||
(set_attr "mode" "SI")])
|
||||
|
||||
(define_insn "mips_subu_s_ph"
|
||||
[(parallel
|
||||
[(set (match_operand:V2HI 0 "register_operand" "=d")
|
||||
(unspec:V2HI [(match_operand:V2HI 1 "reg_or_0_operand" "dYG")
|
||||
(match_operand:V2HI 2 "reg_or_0_operand" "dYG")]
|
||||
UNSPEC_SUBU_S_PH))
|
||||
(set (reg:CCDSP CCDSP_OU_REGNUM)
|
||||
(unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_SUBU_S_PH))])]
|
||||
"TARGET_DSPR2"
|
||||
"subu_s.ph\t%0,%z1,%z2"
|
||||
[(set_attr "type" "arith")
|
||||
(set_attr "mode" "SI")])
|
||||
|
||||
(define_insn "mips_subuh_qb"
|
||||
[(set (match_operand:V4QI 0 "register_operand" "=d")
|
||||
(unspec:V4QI [(match_operand:V4QI 1 "reg_or_0_operand" "dYG")
|
||||
(match_operand:V4QI 2 "reg_or_0_operand" "dYG")]
|
||||
UNSPEC_SUBUH_QB))]
|
||||
"TARGET_DSPR2"
|
||||
"subuh.qb\t%0,%z1,%z2"
|
||||
[(set_attr "type" "arith")
|
||||
(set_attr "mode" "SI")])
|
||||
|
||||
(define_insn "mips_subuh_r_qb"
|
||||
[(set (match_operand:V4QI 0 "register_operand" "=d")
|
||||
(unspec:V4QI [(match_operand:V4QI 1 "reg_or_0_operand" "dYG")
|
||||
(match_operand:V4QI 2 "reg_or_0_operand" "dYG")]
|
||||
UNSPEC_SUBUH_R_QB))]
|
||||
"TARGET_DSPR2"
|
||||
"subuh_r.qb\t%0,%z1,%z2"
|
||||
[(set_attr "type" "arith")
|
||||
(set_attr "mode" "SI")])
|
||||
|
||||
(define_insn "mips_addqh_ph"
|
||||
[(set (match_operand:V2HI 0 "register_operand" "=d")
|
||||
(unspec:V2HI [(match_operand:V2HI 1 "reg_or_0_operand" "dYG")
|
||||
(match_operand:V2HI 2 "reg_or_0_operand" "dYG")]
|
||||
UNSPEC_ADDQH_PH))]
|
||||
"TARGET_DSPR2"
|
||||
"addqh.ph\t%0,%z1,%z2"
|
||||
[(set_attr "type" "arith")
|
||||
(set_attr "mode" "SI")])
|
||||
|
||||
(define_insn "mips_addqh_r_ph"
|
||||
[(set (match_operand:V2HI 0 "register_operand" "=d")
|
||||
(unspec:V2HI [(match_operand:V2HI 1 "reg_or_0_operand" "dYG")
|
||||
(match_operand:V2HI 2 "reg_or_0_operand" "dYG")]
|
||||
UNSPEC_ADDQH_R_PH))]
|
||||
"TARGET_DSPR2"
|
||||
"addqh_r.ph\t%0,%z1,%z2"
|
||||
[(set_attr "type" "arith")
|
||||
(set_attr "mode" "SI")])
|
||||
|
||||
(define_insn "mips_addqh_w"
|
||||
[(set (match_operand:SI 0 "register_operand" "=d")
|
||||
(unspec:SI [(match_operand:SI 1 "reg_or_0_operand" "dJ")
|
||||
(match_operand:SI 2 "reg_or_0_operand" "dJ")]
|
||||
UNSPEC_ADDQH_W))]
|
||||
"TARGET_DSPR2"
|
||||
"addqh.w\t%0,%z1,%z2"
|
||||
[(set_attr "type" "arith")
|
||||
(set_attr "mode" "SI")])
|
||||
|
||||
(define_insn "mips_addqh_r_w"
|
||||
[(set (match_operand:SI 0 "register_operand" "=d")
|
||||
(unspec:SI [(match_operand:SI 1 "reg_or_0_operand" "dJ")
|
||||
(match_operand:SI 2 "reg_or_0_operand" "dJ")]
|
||||
UNSPEC_ADDQH_R_W))]
|
||||
"TARGET_DSPR2"
|
||||
"addqh_r.w\t%0,%z1,%z2"
|
||||
[(set_attr "type" "arith")
|
||||
(set_attr "mode" "SI")])
|
||||
|
||||
(define_insn "mips_subqh_ph"
|
||||
[(set (match_operand:V2HI 0 "register_operand" "=d")
|
||||
(unspec:V2HI [(match_operand:V2HI 1 "reg_or_0_operand" "dYG")
|
||||
(match_operand:V2HI 2 "reg_or_0_operand" "dYG")]
|
||||
UNSPEC_SUBQH_PH))]
|
||||
"TARGET_DSPR2"
|
||||
"subqh.ph\t%0,%z1,%z2"
|
||||
[(set_attr "type" "arith")
|
||||
(set_attr "mode" "SI")])
|
||||
|
||||
(define_insn "mips_subqh_r_ph"
|
||||
[(set (match_operand:V2HI 0 "register_operand" "=d")
|
||||
(unspec:V2HI [(match_operand:V2HI 1 "reg_or_0_operand" "dYG")
|
||||
(match_operand:V2HI 2 "reg_or_0_operand" "dYG")]
|
||||
UNSPEC_SUBQH_R_PH))]
|
||||
"TARGET_DSPR2"
|
||||
"subqh_r.ph\t%0,%z1,%z2"
|
||||
[(set_attr "type" "arith")
|
||||
(set_attr "mode" "SI")])
|
||||
|
||||
(define_insn "mips_subqh_w"
|
||||
[(set (match_operand:SI 0 "register_operand" "=d")
|
||||
(unspec:SI [(match_operand:SI 1 "reg_or_0_operand" "dJ")
|
||||
(match_operand:SI 2 "reg_or_0_operand" "dJ")]
|
||||
UNSPEC_SUBQH_W))]
|
||||
"TARGET_DSPR2"
|
||||
"subqh.w\t%0,%z1,%z2"
|
||||
[(set_attr "type" "arith")
|
||||
(set_attr "mode" "SI")])
|
||||
|
||||
(define_insn "mips_subqh_r_w"
|
||||
[(set (match_operand:SI 0 "register_operand" "=d")
|
||||
(unspec:SI [(match_operand:SI 1 "reg_or_0_operand" "dJ")
|
||||
(match_operand:SI 2 "reg_or_0_operand" "dJ")]
|
||||
UNSPEC_SUBQH_R_W))]
|
||||
"TARGET_DSPR2"
|
||||
"subqh_r.w\t%0,%z1,%z2"
|
||||
[(set_attr "type" "arith")
|
||||
(set_attr "mode" "SI")])
|
||||
|
||||
(define_insn "mips_dpax_w_ph"
|
||||
[(set (match_operand:DI 0 "register_operand" "=a")
|
||||
(unspec:DI [(match_operand:DI 1 "register_operand" "0")
|
||||
(match_operand:V2HI 2 "reg_or_0_operand" "dYG")
|
||||
(match_operand:V2HI 3 "reg_or_0_operand" "dYG")]
|
||||
UNSPEC_DPAX_W_PH))]
|
||||
"TARGET_DSPR2 && !TARGET_64BIT"
|
||||
"dpax.w.ph\t%q0,%z2,%z3"
|
||||
[(set_attr "type" "imadd")
|
||||
(set_attr "mode" "SI")])
|
||||
|
||||
(define_insn "mips_dpsx_w_ph"
|
||||
[(set (match_operand:DI 0 "register_operand" "=a")
|
||||
(unspec:DI [(match_operand:DI 1 "register_operand" "0")
|
||||
(match_operand:V2HI 2 "reg_or_0_operand" "dYG")
|
||||
(match_operand:V2HI 3 "reg_or_0_operand" "dYG")]
|
||||
UNSPEC_DPSX_W_PH))]
|
||||
"TARGET_DSPR2 && !TARGET_64BIT"
|
||||
"dpsx.w.ph\t%q0,%z2,%z3"
|
||||
[(set_attr "type" "imadd")
|
||||
(set_attr "mode" "SI")])
|
||||
|
||||
(define_insn "mips_dpaqx_s_w_ph"
|
||||
[(parallel
|
||||
[(set (match_operand:DI 0 "register_operand" "=a")
|
||||
(unspec:DI [(match_operand:DI 1 "register_operand" "0")
|
||||
(match_operand:V2HI 2 "reg_or_0_operand" "dYG")
|
||||
(match_operand:V2HI 3 "reg_or_0_operand" "dYG")]
|
||||
UNSPEC_DPAQX_S_W_PH))
|
||||
(set (reg:CCDSP CCDSP_OU_REGNUM)
|
||||
(unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)]
|
||||
UNSPEC_DPAQX_S_W_PH))])]
|
||||
"TARGET_DSPR2 && !TARGET_64BIT"
|
||||
"dpaqx_s.w.ph\t%q0,%z2,%z3"
|
||||
[(set_attr "type" "imadd")
|
||||
(set_attr "mode" "SI")])
|
||||
|
||||
(define_insn "mips_dpaqx_sa_w_ph"
|
||||
[(parallel
|
||||
[(set (match_operand:DI 0 "register_operand" "=a")
|
||||
(unspec:DI [(match_operand:DI 1 "register_operand" "0")
|
||||
(match_operand:V2HI 2 "reg_or_0_operand" "dYG")
|
||||
(match_operand:V2HI 3 "reg_or_0_operand" "dYG")]
|
||||
UNSPEC_DPAQX_SA_W_PH))
|
||||
(set (reg:CCDSP CCDSP_OU_REGNUM)
|
||||
(unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)]
|
||||
UNSPEC_DPAQX_SA_W_PH))])]
|
||||
"TARGET_DSPR2 && !TARGET_64BIT"
|
||||
"dpaqx_sa.w.ph\t%q0,%z2,%z3"
|
||||
[(set_attr "type" "imadd")
|
||||
(set_attr "mode" "SI")])
|
||||
|
||||
(define_insn "mips_dpsqx_s_w_ph"
|
||||
[(parallel
|
||||
[(set (match_operand:DI 0 "register_operand" "=a")
|
||||
(unspec:DI [(match_operand:DI 1 "register_operand" "0")
|
||||
(match_operand:V2HI 2 "reg_or_0_operand" "dYG")
|
||||
(match_operand:V2HI 3 "reg_or_0_operand" "dYG")]
|
||||
UNSPEC_DPSQX_S_W_PH))
|
||||
(set (reg:CCDSP CCDSP_OU_REGNUM)
|
||||
(unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)]
|
||||
UNSPEC_DPSQX_S_W_PH))])]
|
||||
"TARGET_DSPR2 && !TARGET_64BIT"
|
||||
"dpsqx_s.w.ph\t%q0,%z2,%z3"
|
||||
[(set_attr "type" "imadd")
|
||||
(set_attr "mode" "SI")])
|
||||
|
||||
(define_insn "mips_dpsqx_sa_w_ph"
|
||||
[(parallel
|
||||
[(set (match_operand:DI 0 "register_operand" "=a")
|
||||
(unspec:DI [(match_operand:DI 1 "register_operand" "0")
|
||||
(match_operand:V2HI 2 "reg_or_0_operand" "dYG")
|
||||
(match_operand:V2HI 3 "reg_or_0_operand" "dYG")]
|
||||
UNSPEC_DPSQX_SA_W_PH))
|
||||
(set (reg:CCDSP CCDSP_OU_REGNUM)
|
||||
(unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)]
|
||||
UNSPEC_DPSQX_SA_W_PH))])]
|
||||
"TARGET_DSPR2 && !TARGET_64BIT"
|
||||
"dpsqx_sa.w.ph\t%q0,%z2,%z3"
|
||||
[(set_attr "type" "imadd")
|
||||
(set_attr "mode" "SI")])
|
||||
|
||||
|
|
@ -180,6 +180,14 @@ enum mips_function_type
|
|||
MIPS_VOID_FTYPE_V2HI_V2HI,
|
||||
MIPS_VOID_FTYPE_V4QI_V4QI,
|
||||
|
||||
/* For MIPS DSP REV 2 ASE. */
|
||||
MIPS_V4QI_FTYPE_V4QI,
|
||||
MIPS_SI_FTYPE_SI_SI_SI,
|
||||
MIPS_DI_FTYPE_DI_USI_USI,
|
||||
MIPS_DI_FTYPE_SI_SI,
|
||||
MIPS_DI_FTYPE_USI_USI,
|
||||
MIPS_V2HI_FTYPE_SI_SI_SI,
|
||||
|
||||
/* The last type. */
|
||||
MIPS_MAX_FTYPE_MAX
|
||||
};
|
||||
|
|
@ -4929,6 +4937,10 @@ override_options (void)
|
|||
if (TARGET_PAIRED_SINGLE_FLOAT && !ISA_MIPS64)
|
||||
error ("-mips3d/-mpaired-single must be used with -mips64");
|
||||
|
||||
/* If TARGET_DSPR2, enable MASK_DSP. */
|
||||
if (TARGET_DSPR2)
|
||||
target_flags |= MASK_DSP;
|
||||
|
||||
if (TARGET_MIPS16 && TARGET_DSP)
|
||||
error ("-mips16 and -mdsp cannot be used together");
|
||||
|
||||
|
|
@ -10096,6 +10108,7 @@ static const struct builtin_description sb1_bdesc[] =
|
|||
#define CODE_FOR_mips_addu_qb CODE_FOR_addv4qi3
|
||||
#define CODE_FOR_mips_subq_ph CODE_FOR_subv2hi3
|
||||
#define CODE_FOR_mips_subu_qb CODE_FOR_subv4qi3
|
||||
#define CODE_FOR_mips_mul_ph CODE_FOR_mulv2hi3
|
||||
|
||||
/* Define a MIPS_BUILTIN_DIRECT_NO_TARGET function for instruction
|
||||
CODE_FOR_mips_<INSN>. FUNCTION_TYPE and TARGET_FLAGS are
|
||||
|
|
@ -10155,19 +10168,6 @@ static const struct builtin_description dsp_bdesc[] =
|
|||
DIRECT_BUILTIN (mulq_rs_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSP),
|
||||
DIRECT_BUILTIN (muleq_s_w_phl, MIPS_SI_FTYPE_V2HI_V2HI, MASK_DSP),
|
||||
DIRECT_BUILTIN (muleq_s_w_phr, MIPS_SI_FTYPE_V2HI_V2HI, MASK_DSP),
|
||||
DIRECT_BUILTIN (dpau_h_qbl, MIPS_DI_FTYPE_DI_V4QI_V4QI, MASK_DSP),
|
||||
DIRECT_BUILTIN (dpau_h_qbr, MIPS_DI_FTYPE_DI_V4QI_V4QI, MASK_DSP),
|
||||
DIRECT_BUILTIN (dpsu_h_qbl, MIPS_DI_FTYPE_DI_V4QI_V4QI, MASK_DSP),
|
||||
DIRECT_BUILTIN (dpsu_h_qbr, MIPS_DI_FTYPE_DI_V4QI_V4QI, MASK_DSP),
|
||||
DIRECT_BUILTIN (dpaq_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSP),
|
||||
DIRECT_BUILTIN (dpsq_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSP),
|
||||
DIRECT_BUILTIN (mulsaq_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSP),
|
||||
DIRECT_BUILTIN (dpaq_sa_l_w, MIPS_DI_FTYPE_DI_SI_SI, MASK_DSP),
|
||||
DIRECT_BUILTIN (dpsq_sa_l_w, MIPS_DI_FTYPE_DI_SI_SI, MASK_DSP),
|
||||
DIRECT_BUILTIN (maq_s_w_phl, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSP),
|
||||
DIRECT_BUILTIN (maq_s_w_phr, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSP),
|
||||
DIRECT_BUILTIN (maq_sa_w_phl, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSP),
|
||||
DIRECT_BUILTIN (maq_sa_w_phr, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSP),
|
||||
DIRECT_BUILTIN (bitrev, MIPS_SI_FTYPE_SI, MASK_DSP),
|
||||
DIRECT_BUILTIN (insv, MIPS_SI_FTYPE_SI_SI, MASK_DSP),
|
||||
DIRECT_BUILTIN (repl_qb, MIPS_V4QI_FTYPE_SI, MASK_DSP),
|
||||
|
|
@ -10184,6 +10184,65 @@ static const struct builtin_description dsp_bdesc[] =
|
|||
DIRECT_BUILTIN (pick_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, MASK_DSP),
|
||||
DIRECT_BUILTIN (pick_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSP),
|
||||
DIRECT_BUILTIN (packrl_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSP),
|
||||
DIRECT_NO_TARGET_BUILTIN (wrdsp, MIPS_VOID_FTYPE_SI_SI, MASK_DSP),
|
||||
DIRECT_BUILTIN (rddsp, MIPS_SI_FTYPE_SI, MASK_DSP),
|
||||
DIRECT_BUILTIN (lbux, MIPS_SI_FTYPE_PTR_SI, MASK_DSP),
|
||||
DIRECT_BUILTIN (lhx, MIPS_SI_FTYPE_PTR_SI, MASK_DSP),
|
||||
DIRECT_BUILTIN (lwx, MIPS_SI_FTYPE_PTR_SI, MASK_DSP),
|
||||
BPOSGE_BUILTIN (32, MASK_DSP),
|
||||
|
||||
/* The following are for the MIPS DSP ASE REV 2. */
|
||||
DIRECT_BUILTIN (absq_s_qb, MIPS_V4QI_FTYPE_V4QI, MASK_DSPR2),
|
||||
DIRECT_BUILTIN (addu_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSPR2),
|
||||
DIRECT_BUILTIN (addu_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSPR2),
|
||||
DIRECT_BUILTIN (adduh_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, MASK_DSPR2),
|
||||
DIRECT_BUILTIN (adduh_r_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, MASK_DSPR2),
|
||||
DIRECT_BUILTIN (append, MIPS_SI_FTYPE_SI_SI_SI, MASK_DSPR2),
|
||||
DIRECT_BUILTIN (balign, MIPS_SI_FTYPE_SI_SI_SI, MASK_DSPR2),
|
||||
DIRECT_BUILTIN (cmpgdu_eq_qb, MIPS_SI_FTYPE_V4QI_V4QI, MASK_DSPR2),
|
||||
DIRECT_BUILTIN (cmpgdu_lt_qb, MIPS_SI_FTYPE_V4QI_V4QI, MASK_DSPR2),
|
||||
DIRECT_BUILTIN (cmpgdu_le_qb, MIPS_SI_FTYPE_V4QI_V4QI, MASK_DSPR2),
|
||||
DIRECT_BUILTIN (mul_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSPR2),
|
||||
DIRECT_BUILTIN (mul_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSPR2),
|
||||
DIRECT_BUILTIN (mulq_rs_w, MIPS_SI_FTYPE_SI_SI, MASK_DSPR2),
|
||||
DIRECT_BUILTIN (mulq_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSPR2),
|
||||
DIRECT_BUILTIN (mulq_s_w, MIPS_SI_FTYPE_SI_SI, MASK_DSPR2),
|
||||
DIRECT_BUILTIN (precr_qb_ph, MIPS_V4QI_FTYPE_V2HI_V2HI, MASK_DSPR2),
|
||||
DIRECT_BUILTIN (precr_sra_ph_w, MIPS_V2HI_FTYPE_SI_SI_SI, MASK_DSPR2),
|
||||
DIRECT_BUILTIN (precr_sra_r_ph_w, MIPS_V2HI_FTYPE_SI_SI_SI, MASK_DSPR2),
|
||||
DIRECT_BUILTIN (prepend, MIPS_SI_FTYPE_SI_SI_SI, MASK_DSPR2),
|
||||
DIRECT_BUILTIN (shra_qb, MIPS_V4QI_FTYPE_V4QI_SI, MASK_DSPR2),
|
||||
DIRECT_BUILTIN (shra_r_qb, MIPS_V4QI_FTYPE_V4QI_SI, MASK_DSPR2),
|
||||
DIRECT_BUILTIN (shrl_ph, MIPS_V2HI_FTYPE_V2HI_SI, MASK_DSPR2),
|
||||
DIRECT_BUILTIN (subu_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSPR2),
|
||||
DIRECT_BUILTIN (subu_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSPR2),
|
||||
DIRECT_BUILTIN (subuh_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, MASK_DSPR2),
|
||||
DIRECT_BUILTIN (subuh_r_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, MASK_DSPR2),
|
||||
DIRECT_BUILTIN (addqh_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSPR2),
|
||||
DIRECT_BUILTIN (addqh_r_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSPR2),
|
||||
DIRECT_BUILTIN (addqh_w, MIPS_SI_FTYPE_SI_SI, MASK_DSPR2),
|
||||
DIRECT_BUILTIN (addqh_r_w, MIPS_SI_FTYPE_SI_SI, MASK_DSPR2),
|
||||
DIRECT_BUILTIN (subqh_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSPR2),
|
||||
DIRECT_BUILTIN (subqh_r_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSPR2),
|
||||
DIRECT_BUILTIN (subqh_w, MIPS_SI_FTYPE_SI_SI, MASK_DSPR2),
|
||||
DIRECT_BUILTIN (subqh_r_w, MIPS_SI_FTYPE_SI_SI, MASK_DSPR2)
|
||||
};
|
||||
|
||||
static const struct builtin_description dsp_32only_bdesc[] =
|
||||
{
|
||||
DIRECT_BUILTIN (dpau_h_qbl, MIPS_DI_FTYPE_DI_V4QI_V4QI, MASK_DSP),
|
||||
DIRECT_BUILTIN (dpau_h_qbr, MIPS_DI_FTYPE_DI_V4QI_V4QI, MASK_DSP),
|
||||
DIRECT_BUILTIN (dpsu_h_qbl, MIPS_DI_FTYPE_DI_V4QI_V4QI, MASK_DSP),
|
||||
DIRECT_BUILTIN (dpsu_h_qbr, MIPS_DI_FTYPE_DI_V4QI_V4QI, MASK_DSP),
|
||||
DIRECT_BUILTIN (dpaq_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSP),
|
||||
DIRECT_BUILTIN (dpsq_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSP),
|
||||
DIRECT_BUILTIN (mulsaq_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSP),
|
||||
DIRECT_BUILTIN (dpaq_sa_l_w, MIPS_DI_FTYPE_DI_SI_SI, MASK_DSP),
|
||||
DIRECT_BUILTIN (dpsq_sa_l_w, MIPS_DI_FTYPE_DI_SI_SI, MASK_DSP),
|
||||
DIRECT_BUILTIN (maq_s_w_phl, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSP),
|
||||
DIRECT_BUILTIN (maq_s_w_phr, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSP),
|
||||
DIRECT_BUILTIN (maq_sa_w_phl, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSP),
|
||||
DIRECT_BUILTIN (maq_sa_w_phr, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSP),
|
||||
DIRECT_BUILTIN (extr_w, MIPS_SI_FTYPE_DI_SI, MASK_DSP),
|
||||
DIRECT_BUILTIN (extr_r_w, MIPS_SI_FTYPE_DI_SI, MASK_DSP),
|
||||
DIRECT_BUILTIN (extr_rs_w, MIPS_SI_FTYPE_DI_SI, MASK_DSP),
|
||||
|
|
@ -10192,12 +10251,23 @@ static const struct builtin_description dsp_bdesc[] =
|
|||
DIRECT_BUILTIN (extpdp, MIPS_SI_FTYPE_DI_SI, MASK_DSP),
|
||||
DIRECT_BUILTIN (shilo, MIPS_DI_FTYPE_DI_SI, MASK_DSP),
|
||||
DIRECT_BUILTIN (mthlip, MIPS_DI_FTYPE_DI_SI, MASK_DSP),
|
||||
DIRECT_NO_TARGET_BUILTIN (wrdsp, MIPS_VOID_FTYPE_SI_SI, MASK_DSP),
|
||||
DIRECT_BUILTIN (rddsp, MIPS_SI_FTYPE_SI, MASK_DSP),
|
||||
DIRECT_BUILTIN (lbux, MIPS_SI_FTYPE_PTR_SI, MASK_DSP),
|
||||
DIRECT_BUILTIN (lhx, MIPS_SI_FTYPE_PTR_SI, MASK_DSP),
|
||||
DIRECT_BUILTIN (lwx, MIPS_SI_FTYPE_PTR_SI, MASK_DSP),
|
||||
BPOSGE_BUILTIN (32, MASK_DSP)
|
||||
|
||||
/* The following are for the MIPS DSP ASE REV 2. */
|
||||
DIRECT_BUILTIN (dpa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSPR2),
|
||||
DIRECT_BUILTIN (dps_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSPR2),
|
||||
DIRECT_BUILTIN (madd, MIPS_DI_FTYPE_DI_SI_SI, MASK_DSPR2),
|
||||
DIRECT_BUILTIN (maddu, MIPS_DI_FTYPE_DI_USI_USI, MASK_DSPR2),
|
||||
DIRECT_BUILTIN (msub, MIPS_DI_FTYPE_DI_SI_SI, MASK_DSPR2),
|
||||
DIRECT_BUILTIN (msubu, MIPS_DI_FTYPE_DI_USI_USI, MASK_DSPR2),
|
||||
DIRECT_BUILTIN (mulsa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSPR2),
|
||||
DIRECT_BUILTIN (mult, MIPS_DI_FTYPE_SI_SI, MASK_DSPR2),
|
||||
DIRECT_BUILTIN (multu, MIPS_DI_FTYPE_USI_USI, MASK_DSPR2),
|
||||
DIRECT_BUILTIN (dpax_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSPR2),
|
||||
DIRECT_BUILTIN (dpsx_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSPR2),
|
||||
DIRECT_BUILTIN (dpaqx_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSPR2),
|
||||
DIRECT_BUILTIN (dpaqx_sa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSPR2),
|
||||
DIRECT_BUILTIN (dpsqx_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSPR2),
|
||||
DIRECT_BUILTIN (dpsqx_sa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSPR2)
|
||||
};
|
||||
|
||||
/* This helps provide a mapping from builtin function codes to bdesc
|
||||
|
|
@ -10214,13 +10284,19 @@ struct bdesc_map
|
|||
/* The target processor that supports these builtin functions.
|
||||
PROCESSOR_MAX means we enable them for all processors. */
|
||||
enum processor_type proc;
|
||||
|
||||
/* If the target has these flags, this builtin function table
|
||||
will not be supported. */
|
||||
int unsupported_target_flags;
|
||||
};
|
||||
|
||||
static const struct bdesc_map bdesc_arrays[] =
|
||||
{
|
||||
{ mips_bdesc, ARRAY_SIZE (mips_bdesc), PROCESSOR_MAX },
|
||||
{ sb1_bdesc, ARRAY_SIZE (sb1_bdesc), PROCESSOR_SB1 },
|
||||
{ dsp_bdesc, ARRAY_SIZE (dsp_bdesc), PROCESSOR_MAX }
|
||||
{ mips_bdesc, ARRAY_SIZE (mips_bdesc), PROCESSOR_MAX, 0 },
|
||||
{ sb1_bdesc, ARRAY_SIZE (sb1_bdesc), PROCESSOR_SB1, 0 },
|
||||
{ dsp_bdesc, ARRAY_SIZE (dsp_bdesc), PROCESSOR_MAX, 0 },
|
||||
{ dsp_32only_bdesc, ARRAY_SIZE (dsp_32only_bdesc), PROCESSOR_MAX,
|
||||
MASK_64BIT }
|
||||
};
|
||||
|
||||
/* Take the argument ARGNUM of the arglist of EXP and convert it into a form
|
||||
|
|
@ -10541,6 +10617,41 @@ mips_init_builtins (void)
|
|||
|
||||
types[MIPS_SI_FTYPE_VOID]
|
||||
= build_function_type (intSI_type_node, void_list_node);
|
||||
|
||||
if (TARGET_DSPR2)
|
||||
{
|
||||
types[MIPS_V4QI_FTYPE_V4QI]
|
||||
= build_function_type_list (V4QI_type_node,
|
||||
V4QI_type_node,
|
||||
NULL_TREE);
|
||||
|
||||
types[MIPS_SI_FTYPE_SI_SI_SI]
|
||||
= build_function_type_list (intSI_type_node,
|
||||
intSI_type_node, intSI_type_node,
|
||||
intSI_type_node, NULL_TREE);
|
||||
|
||||
types[MIPS_DI_FTYPE_DI_USI_USI]
|
||||
= build_function_type_list (intDI_type_node,
|
||||
intDI_type_node,
|
||||
unsigned_intSI_type_node,
|
||||
unsigned_intSI_type_node, NULL_TREE);
|
||||
|
||||
types[MIPS_DI_FTYPE_SI_SI]
|
||||
= build_function_type_list (intDI_type_node,
|
||||
intSI_type_node, intSI_type_node,
|
||||
NULL_TREE);
|
||||
|
||||
types[MIPS_DI_FTYPE_USI_USI]
|
||||
= build_function_type_list (intDI_type_node,
|
||||
unsigned_intSI_type_node,
|
||||
unsigned_intSI_type_node, NULL_TREE);
|
||||
|
||||
types[MIPS_V2HI_FTYPE_SI_SI_SI]
|
||||
= build_function_type_list (V2HI_type_node,
|
||||
intSI_type_node, intSI_type_node,
|
||||
intSI_type_node, NULL_TREE);
|
||||
|
||||
}
|
||||
}
|
||||
|
||||
/* Iterate through all of the bdesc arrays, initializing all of the
|
||||
|
|
@ -10549,7 +10660,8 @@ mips_init_builtins (void)
|
|||
offset = 0;
|
||||
for (m = bdesc_arrays; m < &bdesc_arrays[ARRAY_SIZE (bdesc_arrays)]; m++)
|
||||
{
|
||||
if (m->proc == PROCESSOR_MAX || (m->proc == mips_arch))
|
||||
if ((m->proc == PROCESSOR_MAX || (m->proc == mips_arch))
|
||||
&& (m->unsupported_target_flags & target_flags) == 0)
|
||||
for (d = m->bdesc; d < &m->bdesc[m->size]; d++)
|
||||
if ((d->target_flags & target_flags) == d->target_flags)
|
||||
add_builtin_function (d->name, types[d->function_type],
|
||||
|
|
|
|||
|
|
@ -340,6 +340,9 @@ extern const struct mips_rtx_cost_data *mips_cost;
|
|||
if (TARGET_DSP) \
|
||||
builtin_define ("__mips_dsp"); \
|
||||
\
|
||||
if (TARGET_DSPR2) \
|
||||
builtin_define ("__mips_dspr2"); \
|
||||
\
|
||||
MIPS_CPP_SET_PROCESSOR ("_MIPS_ARCH", mips_arch_info); \
|
||||
MIPS_CPP_SET_PROCESSOR ("_MIPS_TUNE", mips_tune_info); \
|
||||
\
|
||||
|
|
@ -820,6 +823,7 @@ extern const struct mips_rtx_cost_data *mips_cost;
|
|||
%{mips16:%{!mno-mips16:-mips16}} %{mno-mips16:-no-mips16} \
|
||||
%{mips3d:-mips3d} \
|
||||
%{mdsp} \
|
||||
%{mdspr2} \
|
||||
%{mfix-vr4120} %{mfix-vr4130} \
|
||||
%(subtarget_asm_optimizing_spec) \
|
||||
%(subtarget_asm_debugging_spec) \
|
||||
|
|
|
|||
|
|
@ -147,6 +147,57 @@
|
|||
(UNSPEC_MTHLIP 365)
|
||||
(UNSPEC_WRDSP 366)
|
||||
(UNSPEC_RDDSP 367)
|
||||
|
||||
;; MIPS DSP ASE REV 2 Revision 0.02 11/24/2006
|
||||
(UNSPEC_ABSQ_S_QB 400)
|
||||
(UNSPEC_ADDU_PH 401)
|
||||
(UNSPEC_ADDU_S_PH 402)
|
||||
(UNSPEC_ADDUH_QB 403)
|
||||
(UNSPEC_ADDUH_R_QB 404)
|
||||
(UNSPEC_APPEND 405)
|
||||
(UNSPEC_BALIGN 406)
|
||||
(UNSPEC_CMPGDU_EQ_QB 407)
|
||||
(UNSPEC_CMPGDU_LT_QB 408)
|
||||
(UNSPEC_CMPGDU_LE_QB 409)
|
||||
(UNSPEC_DPA_W_PH 410)
|
||||
(UNSPEC_DPS_W_PH 411)
|
||||
(UNSPEC_MADD 412)
|
||||
(UNSPEC_MADDU 413)
|
||||
(UNSPEC_MSUB 414)
|
||||
(UNSPEC_MSUBU 415)
|
||||
(UNSPEC_MUL_PH 416)
|
||||
(UNSPEC_MUL_S_PH 417)
|
||||
(UNSPEC_MULQ_RS_W 418)
|
||||
(UNSPEC_MULQ_S_PH 419)
|
||||
(UNSPEC_MULQ_S_W 420)
|
||||
(UNSPEC_MULSA_W_PH 421)
|
||||
(UNSPEC_MULT 422)
|
||||
(UNSPEC_MULTU 423)
|
||||
(UNSPEC_PRECR_QB_PH 424)
|
||||
(UNSPEC_PRECR_SRA_PH_W 425)
|
||||
(UNSPEC_PRECR_SRA_R_PH_W 426)
|
||||
(UNSPEC_PREPEND 427)
|
||||
(UNSPEC_SHRA_QB 428)
|
||||
(UNSPEC_SHRA_R_QB 429)
|
||||
(UNSPEC_SHRL_PH 430)
|
||||
(UNSPEC_SUBU_PH 431)
|
||||
(UNSPEC_SUBU_S_PH 432)
|
||||
(UNSPEC_SUBUH_QB 433)
|
||||
(UNSPEC_SUBUH_R_QB 434)
|
||||
(UNSPEC_ADDQH_PH 435)
|
||||
(UNSPEC_ADDQH_R_PH 436)
|
||||
(UNSPEC_ADDQH_W 437)
|
||||
(UNSPEC_ADDQH_R_W 438)
|
||||
(UNSPEC_SUBQH_PH 439)
|
||||
(UNSPEC_SUBQH_R_PH 440)
|
||||
(UNSPEC_SUBQH_W 441)
|
||||
(UNSPEC_SUBQH_R_W 442)
|
||||
(UNSPEC_DPAX_W_PH 443)
|
||||
(UNSPEC_DPSX_W_PH 444)
|
||||
(UNSPEC_DPAQX_S_W_PH 445)
|
||||
(UNSPEC_DPAQX_SA_W_PH 446)
|
||||
(UNSPEC_DPSQX_S_W_PH 447)
|
||||
(UNSPEC_DPSQX_SA_W_PH 448)
|
||||
]
|
||||
)
|
||||
|
||||
|
|
@ -1505,7 +1556,7 @@
|
|||
[(set (match_operand:DI 0 "register_operand" "=x")
|
||||
(mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
|
||||
(any_extend:DI (match_operand:SI 2 "register_operand" "d"))))]
|
||||
"!TARGET_64BIT && !TARGET_FIX_R4000"
|
||||
"!TARGET_64BIT && !TARGET_FIX_R4000 && !TARGET_DSPR2"
|
||||
"mult<u>\t%1,%2"
|
||||
[(set_attr "type" "imul")
|
||||
(set_attr "mode" "SI")])
|
||||
|
|
@ -5514,3 +5565,7 @@
|
|||
; The MIPS DSP Instructions.
|
||||
|
||||
(include "mips-dsp.md")
|
||||
|
||||
; The MIPS DSP REV 2 Instructions.
|
||||
|
||||
(include "mips-dspr2.md")
|
||||
|
|
|
|||
|
|
@ -59,6 +59,10 @@ mdsp
|
|||
Target Report Mask(DSP)
|
||||
Use MIPS-DSP instructions
|
||||
|
||||
mdspr2
|
||||
Target Report Mask(DSPR2)
|
||||
Use MIPS-DSP REV 2 instructions
|
||||
|
||||
mdebug
|
||||
Target Var(TARGET_DEBUG_MODE) Undocumented
|
||||
|
||||
|
|
|
|||
|
|
@ -7403,25 +7403,36 @@ v2si __builtin_ia32_pswapdsi (v2si)
|
|||
The MIPS DSP Application-Specific Extension (ASE) includes new
|
||||
instructions that are designed to improve the performance of DSP and
|
||||
media applications. It provides instructions that operate on packed
|
||||
8-bit integer data, Q15 fractional data and Q31 fractional data.
|
||||
8-bit/16-bit integer data, Q7, Q15 and Q31 fractional data.
|
||||
|
||||
GCC supports MIPS DSP operations using both the generic
|
||||
vector extensions (@pxref{Vector Extensions}) and a collection of
|
||||
MIPS-specific built-in functions. Both kinds of support are
|
||||
enabled by the @option{-mdsp} command-line option.
|
||||
|
||||
Revision 2 of the ASE was introduced in the second half of 2006.
|
||||
This revision adds extra instructions to the original ASE, but is
|
||||
otherwise backwards-compatible with it. You can select revision 2
|
||||
using the command-line option @option{-mdspr2}; this option implies
|
||||
@option{-mdsp}.
|
||||
|
||||
At present, GCC only provides support for operations on 32-bit
|
||||
vectors. The vector type associated with 8-bit integer data is
|
||||
usually called @code{v4i8} and the vector type associated with Q15 is
|
||||
usually called @code{v2q15}. They can be defined in C as follows:
|
||||
usually called @code{v4i8}, the vector type associated with Q7
|
||||
is usually called @code{v4q7}, the vector type associated with 16-bit
|
||||
integer data is usually called @code{v2i16}, and the vector type
|
||||
associated with Q15 is usually called @code{v2q15}. They can be
|
||||
defined in C as follows:
|
||||
|
||||
@smallexample
|
||||
typedef char v4i8 __attribute__ ((vector_size(4)));
|
||||
typedef signed char v4i8 __attribute__ ((vector_size(4)));
|
||||
typedef signed char v4q7 __attribute__ ((vector_size(4)));
|
||||
typedef short v2i16 __attribute__ ((vector_size(4)));
|
||||
typedef short v2q15 __attribute__ ((vector_size(4)));
|
||||
@end smallexample
|
||||
|
||||
@code{v4i8} and @code{v2q15} values are initialized in the same way as
|
||||
aggregates. For example:
|
||||
@code{v4i8}, @code{v4q7}, @code{v2i16} and @code{v2q15} values are
|
||||
initialized in the same way as aggregates. For example:
|
||||
|
||||
@smallexample
|
||||
v4i8 a = @{1, 2, 3, 4@};
|
||||
|
|
@ -7440,9 +7451,10 @@ order applies to big-endian targets. For example, the code above will
|
|||
set the lowest byte of @code{a} to @code{1} on little-endian targets
|
||||
and @code{4} on big-endian targets.
|
||||
|
||||
@emph{Note:} Q15 and Q31 values must be initialized with their integer
|
||||
@emph{Note:} Q7, Q15 and Q31 values must be initialized with their integer
|
||||
representation. As shown in this example, the integer representation
|
||||
of a Q15 value can be obtained by multiplying the fractional value by
|
||||
of a Q7 value can be obtained by multiplying the fractional value by
|
||||
@code{0x1.0p7}. The equivalent for Q15 values is to multiply by
|
||||
@code{0x1.0p15}. The equivalent for Q31 values is to multiply by
|
||||
@code{0x1.0p31}.
|
||||
|
||||
|
|
@ -7458,12 +7470,22 @@ and @code{c} and @code{d} are @code{v2q15} values.
|
|||
@item @code{c - d} @tab @code{subq.ph}
|
||||
@end multitable
|
||||
|
||||
The table below lists the @code{v2i16} operation for which
|
||||
hardware support exists for the DSP ASE REV 2. @code{e} and @code{f} are
|
||||
@code{v2i16} values.
|
||||
|
||||
@multitable @columnfractions .50 .50
|
||||
@item C code @tab MIPS instruction
|
||||
@item @code{e * f} @tab @code{mul.ph}
|
||||
@end multitable
|
||||
|
||||
It is easier to describe the DSP built-in functions if we first define
|
||||
the following types:
|
||||
|
||||
@smallexample
|
||||
typedef int q31;
|
||||
typedef int i32;
|
||||
typedef unsigned int ui32;
|
||||
typedef long long a64;
|
||||
@end smallexample
|
||||
|
||||
|
|
@ -7480,6 +7502,7 @@ numbers and register operands, or accept immediate numbers only. The
|
|||
immediate parameters are listed as follows.
|
||||
|
||||
@smallexample
|
||||
imm0_3: 0 to 3.
|
||||
imm0_7: 0 to 7.
|
||||
imm0_15: 0 to 15.
|
||||
imm0_31: 0 to 31.
|
||||
|
|
@ -7599,6 +7622,66 @@ i32 __builtin_mips_lwx (void *, i32)
|
|||
i32 __builtin_mips_bposge32 (void)
|
||||
@end smallexample
|
||||
|
||||
The following built-in functions map directly to a particular MIPS DSP REV 2
|
||||
instruction. Please refer to the architecture specification
|
||||
for details on what each instruction does.
|
||||
|
||||
@smallexample
|
||||
v4q7 __builtin_mips_absq_s_qb (v4q7);
|
||||
v2i16 __builtin_mips_addu_ph (v2i16, v2i16);
|
||||
v2i16 __builtin_mips_addu_s_ph (v2i16, v2i16);
|
||||
v4i8 __builtin_mips_adduh_qb (v4i8, v4i8);
|
||||
v4i8 __builtin_mips_adduh_r_qb (v4i8, v4i8);
|
||||
i32 __builtin_mips_append (i32, i32, imm0_31);
|
||||
i32 __builtin_mips_balign (i32, i32, imm0_3);
|
||||
i32 __builtin_mips_cmpgdu_eq_qb (v4i8, v4i8);
|
||||
i32 __builtin_mips_cmpgdu_lt_qb (v4i8, v4i8);
|
||||
i32 __builtin_mips_cmpgdu_le_qb (v4i8, v4i8);
|
||||
a64 __builtin_mips_dpa_w_ph (a64, v2i16, v2i16);
|
||||
a64 __builtin_mips_dps_w_ph (a64, v2i16, v2i16);
|
||||
a64 __builtin_mips_madd (a64, i32, i32);
|
||||
a64 __builtin_mips_maddu (a64, ui32, ui32);
|
||||
a64 __builtin_mips_msub (a64, i32, i32);
|
||||
a64 __builtin_mips_msubu (a64, ui32, ui32);
|
||||
v2i16 __builtin_mips_mul_ph (v2i16, v2i16);
|
||||
v2i16 __builtin_mips_mul_s_ph (v2i16, v2i16);
|
||||
q31 __builtin_mips_mulq_rs_w (q31, q31);
|
||||
v2q15 __builtin_mips_mulq_s_ph (v2q15, v2q15);
|
||||
q31 __builtin_mips_mulq_s_w (q31, q31);
|
||||
a64 __builtin_mips_mulsa_w_ph (a64, v2i16, v2i16);
|
||||
a64 __builtin_mips_mult (i32, i32);
|
||||
a64 __builtin_mips_multu (ui32, ui32);
|
||||
v4i8 __builtin_mips_precr_qb_ph (v2i16, v2i16);
|
||||
v2i16 __builtin_mips_precr_sra_ph_w (i32, i32, imm0_31);
|
||||
v2i16 __builtin_mips_precr_sra_r_ph_w (i32, i32, imm0_31);
|
||||
i32 __builtin_mips_prepend (i32, i32, imm0_31);
|
||||
v4i8 __builtin_mips_shra_qb (v4i8, imm0_7);
|
||||
v4i8 __builtin_mips_shra_r_qb (v4i8, imm0_7);
|
||||
v4i8 __builtin_mips_shra_qb (v4i8, i32);
|
||||
v4i8 __builtin_mips_shra_r_qb (v4i8, i32);
|
||||
v2i16 __builtin_mips_shrl_ph (v2i16, imm0_15);
|
||||
v2i16 __builtin_mips_shrl_ph (v2i16, i32);
|
||||
v2i16 __builtin_mips_subu_ph (v2i16, v2i16);
|
||||
v2i16 __builtin_mips_subu_s_ph (v2i16, v2i16);
|
||||
v4i8 __builtin_mips_subuh_qb (v4i8, v4i8);
|
||||
v4i8 __builtin_mips_subuh_r_qb (v4i8, v4i8);
|
||||
v2q15 __builtin_mips_addqh_ph (v2q15, v2q15);
|
||||
v2q15 __builtin_mips_addqh_r_ph (v2q15, v2q15);
|
||||
q31 __builtin_mips_addqh_w (q31, q31);
|
||||
q31 __builtin_mips_addqh_r_w (q31, q31);
|
||||
v2q15 __builtin_mips_subqh_ph (v2q15, v2q15);
|
||||
v2q15 __builtin_mips_subqh_r_ph (v2q15, v2q15);
|
||||
q31 __builtin_mips_subqh_w (q31, q31);
|
||||
q31 __builtin_mips_subqh_r_w (q31, q31);
|
||||
a64 __builtin_mips_dpax_w_ph (a64, v2i16, v2i16);
|
||||
a64 __builtin_mips_dpsx_w_ph (a64, v2i16, v2i16);
|
||||
a64 __builtin_mips_dpaqx_s_w_ph (a64, v2q15, v2q15);
|
||||
a64 __builtin_mips_dpaqx_sa_w_ph (a64, v2q15, v2q15);
|
||||
a64 __builtin_mips_dpsqx_s_w_ph (a64, v2q15, v2q15);
|
||||
a64 __builtin_mips_dpsqx_sa_w_ph (a64, v2q15, v2q15);
|
||||
@end smallexample
|
||||
|
||||
|
||||
@node MIPS Paired-Single Support
|
||||
@subsection MIPS Paired-Single Support
|
||||
|
||||
|
|
|
|||
|
|
@ -613,7 +613,7 @@ Objective-C and Objective-C++ Dialects}.
|
|||
-mips16 -mno-mips16 -mabi=@var{abi} -mabicalls -mno-abicalls @gol
|
||||
-mshared -mno-shared -mxgot -mno-xgot -mgp32 -mgp64 @gol
|
||||
-mfp32 -mfp64 -mhard-float -msoft-float @gol
|
||||
-msingle-float -mdouble-float -mdsp -mpaired-single -mips3d @gol
|
||||
-msingle-float -mdouble-float -mdsp -mdspr2 -mpaired-single -mips3d @gol
|
||||
-mlong64 -mlong32 -msym32 -mno-sym32 @gol
|
||||
-G@var{num} -membedded-data -mno-embedded-data @gol
|
||||
-muninit-const-in-rodata -mno-uninit-const-in-rodata @gol
|
||||
|
|
@ -11318,6 +11318,13 @@ operations. This is the default.
|
|||
@opindex mno-dsp
|
||||
Use (do not use) the MIPS DSP ASE. @xref{MIPS DSP Built-in Functions}.
|
||||
|
||||
@itemx -mdspr2
|
||||
@itemx -mno-dspr2
|
||||
@opindex mdspr2
|
||||
@opindex mno-dspr2
|
||||
Use (do not use) the MIPS DSP ASE REV 2. @xref{MIPS DSP Built-in Functions}.
|
||||
The option @option{-mdspr2} implies @option{-mdsp}.
|
||||
|
||||
@itemx -mpaired-single
|
||||
@itemx -mno-paired-single
|
||||
@opindex mpaired-single
|
||||
|
|
|
|||
Loading…
Reference in New Issue