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re PR target/83467 (ICE: in assign_by_spills, at lra-assigns.c:1476: unable to find a register to spill with -flive-range-shrinkage -m8bit-idiv) 

PR target/83467
	* config/i386/i386.md (*ashl<mode>3_mask): Add operand
	constraints to operand 2.
	(*<shift_insn><mode>3_mask): Ditto.
	(*<rotate_insn><mode>3_mask): Ditto.

testsuite/ChangeLog:

	PR target/83467
	* gcc.target/i386/pr83467-1.c: New test.
	* gcc.target/i386/pr83467-2.c: Ditto.

From-SVN: r255956
This commit is contained in:
Uros Bizjak 2017-12-21 21:48:34 +01:00
parent 44612ae164
commit 32a3966ecd
5 changed files with 60 additions and 13 deletions
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18
gcc/ChangeLog
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@ -1,3 +1,11 @@
2017-12-21 Uros Bizjak <ubizjak@gmail.com>
PR target/83467
* config/i386/i386.md (*ashl<mode>3_mask): Add operand
constraints to operand 2.
(*<shift_insn><mode>3_mask): Ditto.
(*<rotate_insn><mode>3_mask): Ditto.
2017-12-19 Bin Cheng <bin.cheng@arm.com>
Backport from mainline
@ -121,7 +129,7 @@
mode for MULT rather than the shift's mode.
2017-11-24 Jakub Jelinek <jakub@redhat.com>
PR sanitizer/83014
* ubsan.c (ubsan_type_descriptor): Use pp_unsigned_wide_integer
instead of pp_printf with HOST_WIDE_INT_PRINT_DEC. Avoid calling
@ -179,7 +187,7 @@
NOPs generated by folding for removal.
2017-12-15 Richard Biener <rguenther@suse.de>
Backport from mainline
2017-09-05 Richard Biener <rguenther@suse.de>
@ -306,7 +314,7 @@
Backport from mainline
2017-05-08 Max Filippov <jcmvbkbc@gmail.com>
* config/xtensa/xtensa-protos.h
(xtensa_initial_elimination_offset): New declaration.
(xtensa_initial_elimination_offset): New declaration.
* config/xtensa/xtensa.c (xtensa_initial_elimination_offset):
New function. Move its body from the INITIAL_ELIMINATION_OFFSET
macro definition, add case for FRAME_POINTER_REGNUM when
@ -350,7 +358,7 @@
* config/i386/i386.h: (host_detect_local_cpu): New define.
(TARGET_EMIT_VZEROUPPER): New.
* config/i386/x86-tune.def: Add X86_TUNE_EMIT_VZEROUPPER
2017-12-01 Segher Boessenkool <segher@kernel.crashing.org>
Backport from mainline
@ -510,7 +518,7 @@
Revert
2017-11-21 Martin Liska <mliska@suse.cz>
Backport from mainline
2017-11-21 Martin Liska <mliska@suse.cz>

12
gcc/config/i386/i386.md
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@ -9641,7 +9641,7 @@
(match_operand:SWI48 1 "nonimmediate_operand")
(subreg:QI
(and:SI
(match_operand:SI 2 "register_operand")
(match_operand:SI 2 "register_operand" "c,r")
(match_operand:SI 3 "const_int_operand")) 0)))
(clobber (reg:CC FLAGS_REG))]
"ix86_binary_operator_ok (ASHIFT, <MODE>mode, operands)
@ -9655,7 +9655,8 @@
(ashift:SWI48 (match_dup 1)
(match_dup 2)))
(clobber (reg:CC FLAGS_REG))])]
"operands[2] = gen_lowpart (QImode, operands[2]);")
"operands[2] = gen_lowpart (QImode, operands[2]);"
[(set_attr "isa" "*,bmi2")])
(define_insn "*bmi2_ashl<mode>3_1"
[(set (match_operand:SWI48 0 "register_operand" "=r")
@ -10141,7 +10142,7 @@
(match_operand:SWI48 1 "nonimmediate_operand")
(subreg:QI
(and:SI
(match_operand:SI 2 "register_operand")
(match_operand:SI 2 "register_operand" "c,r")
(match_operand:SI 3 "const_int_operand")) 0)))
(clobber (reg:CC FLAGS_REG))]
"ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)
@ -10155,7 +10156,8 @@
(any_shiftrt:SWI48 (match_dup 1)
(match_dup 2)))
(clobber (reg:CC FLAGS_REG))])]
"operands[2] = gen_lowpart (QImode, operands[2]);")
"operands[2] = gen_lowpart (QImode, operands[2]);"
[(set_attr "isa" "*,bmi2")])
(define_insn_and_split "*<shift_insn><mode>3_doubleword"
[(set (match_operand:DWI 0 "register_operand" "=&r")
@ -10600,7 +10602,7 @@
(match_operand:SWI48 1 "nonimmediate_operand")
(subreg:QI
(and:SI
(match_operand:SI 2 "register_operand")
(match_operand:SI 2 "register_operand" "c")
(match_operand:SI 3 "const_int_operand")) 0)))
(clobber (reg:CC FLAGS_REG))]
"ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)

12
gcc/testsuite/ChangeLog
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@ -1,3 +1,9 @@
2017-12-21 Uros Bizjak <ubizjak@gmail.com>
PR target/83467
* gcc.target/i386/pr83467-1.c: New test.
* gcc.target/i386/pr83467-2.c: Ditto.
2017-12-21 Thomas Koenig <tkoenig@gcc.gnu.org>
Backport from trunk
@ -145,7 +151,7 @@
* gcc.target/arm/armv8_2-fp16-move-2.c: Remove dg-add-options.
2017-12-15 Richard Biener <rguenther@suse.de>
Backport from mainline
2017-09-05 Richard Biener <rguenther@suse.de>
@ -1144,8 +1150,8 @@
2017-06-21 Marc Glisse <marc.glisse@inria.fr>
* gcc.dg/tree-ssa/addadd.c: Un-XFAIL.
* gcc.dg/tree-ssa/addadd-2.c: New file.
* gcc.dg/tree-ssa/addadd.c: Un-XFAIL.
* gcc.dg/tree-ssa/addadd-2.c: New file.
2016-07-25 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

18
gcc/testsuite/gcc.target/i386/pr83467-1.c Normal file
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@ -0,0 +1,18 @@
/* { dg-do compile } */
/* { dg-options "-O2 -flive-range-shrinkage -m8bit-idiv" } */
/* { dg-require-effective-target int128 } */
unsigned a;
__int128
b (unsigned c, short d, int e, long f, unsigned __int128 g, char h,
int i, __int128 j)
{
j %= 5;
c *= i;
e = e >> (g & 31);
h &= e /= d;
g <<= 0 <= 0;
g &= h < j;
return c + d + f + g + h + i + a + j;
}

13
gcc/testsuite/gcc.target/i386/pr83467-2.c Normal file
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@ -0,0 +1,13 @@
/* { dg-do compile } */
/* { dg-options "-O2 -flive-range-shrinkage" } */
/* { dg-require-effective-target int128 } */
int
a (int b, short c, int d, long e, __int128 f, short g, long h, __int128 i)
{
d <<= f & 31;
f >>= 127;
g *= d > c;
f >>= g;
return b + e + f + h + i;
}