re PR target/56028 (Splitting a 64-bit volatile store)
PR target/56028 * config/i386/i386.md (*movti_internal_rex64): Change (o,riF) alternative to (o,r). (*movdi_internal_rex64): Remove (!o,n) alternative. (DImode immediate->memory splitter): Remove. (DImode immediate->memory peephole2): Remove. (movtf): Enable for TARGET_64BIT || TARGET_SSE. (*movtf_internal_rex64): Rename from *movtf_internal. Change (!o,F*r) alternative to (!o,*r). (*movtf_internal_sse): New pattern. (*movxf_internal_rex64): New pattern. (*movxf_internal): Disable for TARGET_64BIT. (*movdf_internal_rex64): Remove (!o,F) alternative. testsuite/ChangeLog: 2012-01-22 Uros Bizjak <ubizjak@gmail.com> PR target/56028 * gcc.target/i386/pr56028.c: New test. From-SVN: r195386
This commit is contained in:
Uros Bizjak
Uros Bizjak
parent
0a18c815f9
commit
32fc5b8a4b
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@ -1,3 +1,19 @@
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2012-01-22 Uros Bizjak <ubizjak@gmail.com>
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PR target/56028
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* config/i386/i386.md (*movti_internal_rex64): Change (o,riF)
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alternative to (o,r).
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(*movdi_internal_rex64): Remove (!o,n) alternative.
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(DImode immediate->memory splitter): Remove.
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(DImode immediate->memory peephole2): Remove.
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(movtf): Enable for TARGET_64BIT || TARGET_SSE.
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(*movtf_internal_rex64): Rename from *movtf_internal. Change (!o,F*r)
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alternative to (!o,*r).
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(*movtf_internal_sse): New pattern.
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(*movxf_internal_rex64): New pattern.
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(*movxf_internal): Disable for TARGET_64BIT.
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(*movdf_internal_rex64): Remove (!o,F) alternative.
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2013-01-22 Jakub Jelinek <jakub@redhat.com>
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PR middle-end/56074
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@ -1757,8 +1757,8 @@
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(const_string "OI")))])
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(define_insn "*movti_internal_rex64"
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[(set (match_operand:TI 0 "nonimmediate_operand" "=!r ,o ,x,x ,m")
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(match_operand:TI 1 "general_operand" "riFo,riF,C,xm,x"))]
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[(set (match_operand:TI 0 "nonimmediate_operand" "=!r ,o,x,x ,m")
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(match_operand:TI 1 "general_operand" "riFo,r,C,xm,x"))]
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"TARGET_64BIT && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
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{
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switch (which_alternative)
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@ -1867,9 +1867,9 @@
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(define_insn "*movdi_internal_rex64"
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[(set (match_operand:DI 0 "nonimmediate_operand"
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"=r,r ,r,m ,!o,*y,m*y,?*y,?r ,?*Ym,*x,m ,*x,*x,?r ,?*Yi,?*x,?*Ym")
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"=r,r ,r,m ,*y,m*y,?*y,?r ,?*Ym,*x,m ,*x,*x,?r ,?*Yi,?*x,?*Ym")
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(match_operand:DI 1 "general_operand"
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"Z ,rem,i,re,n ,C ,*y ,m ,*Ym,r ,C ,*x,*x,m ,*Yi,r ,*Ym,*x"))]
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"Z ,rem,i,re,C ,*y ,m ,*Ym,r ,C ,*x,*x,m ,*Yi,r ,*Ym,*x"))]
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"TARGET_64BIT && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
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{
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switch (get_attr_type (insn))
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@ -1905,9 +1905,6 @@
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case TYPE_MMX:
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return "pxor\t%0, %0";
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case TYPE_MULTI:
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return "#";
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case TYPE_LEA:
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return "lea{q}\t{%E1, %0|%0, %E1}";
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@ -1925,16 +1922,14 @@
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}
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[(set (attr "type")
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(cond [(eq_attr "alternative" "4")
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(const_string "multi")
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(eq_attr "alternative" "5")
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(const_string "mmx")
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(eq_attr "alternative" "6,7,8,9")
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(eq_attr "alternative" "5,6,7,8")
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(const_string "mmxmov")
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(eq_attr "alternative" "10")
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(eq_attr "alternative" "9")
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(const_string "sselog1")
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(eq_attr "alternative" "11,12,13,14,15")
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(eq_attr "alternative" "10,11,12,13,14")
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(const_string "ssemov")
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(eq_attr "alternative" "16,17")
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(eq_attr "alternative" "15,16")
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(const_string "ssecvt")
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(match_operand 1 "pic_32bit_operand")
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(const_string "lea")
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@ -1951,21 +1946,21 @@
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(const_string "8")
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(const_string "*")))
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(set (attr "prefix_rex")
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(if_then_else (eq_attr "alternative" "8,9")
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(if_then_else (eq_attr "alternative" "7,8")
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(const_string "1")
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(const_string "*")))
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(set (attr "prefix_data16")
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(if_then_else (eq_attr "alternative" "11")
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(if_then_else (eq_attr "alternative" "10")
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(const_string "1")
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(const_string "*")))
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(set (attr "prefix")
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(if_then_else (eq_attr "alternative" "10,11,12,13,14,15")
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(if_then_else (eq_attr "alternative" "9,10,11,12,13,14")
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(const_string "maybe_vex")
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(const_string "orig")))
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(set (attr "mode")
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(cond [(eq_attr "alternative" "0,4")
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(cond [(eq_attr "alternative" "0")
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(const_string "SI")
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(eq_attr "alternative" "10,12")
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(eq_attr "alternative" "9,11")
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(cond [(match_test "TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL")
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(const_string "V4SF")
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(match_test "TARGET_AVX")
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@ -2011,41 +2006,6 @@
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DONE;
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})
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;; Convert impossible stores of immediate to existing instructions.
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;; First try to get scratch register and go through it. In case this
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;; fails, move by 32bit parts.
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(define_peephole2
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[(match_scratch:DI 2 "r")
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(set (match_operand:DI 0 "memory_operand")
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(match_operand:DI 1 "immediate_operand"))]
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"TARGET_64BIT && !symbolic_operand (operands[1], DImode)
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&& !x86_64_immediate_operand (operands[1], DImode)"
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[(set (match_dup 2) (match_dup 1))
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(set (match_dup 0) (match_dup 2))])
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;; We need to define this as both peepholer and splitter for case
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;; peephole2 pass is not run.
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;; "&& 1" is needed to keep it from matching the previous pattern.
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(define_peephole2
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[(set (match_operand:DI 0 "memory_operand")
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(match_operand:DI 1 "immediate_operand"))]
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"TARGET_64BIT && !symbolic_operand (operands[1], DImode)
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&& !x86_64_immediate_operand (operands[1], DImode) && 1"
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[(set (match_dup 2) (match_dup 3))
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(set (match_dup 4) (match_dup 5))]
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"split_double_mode (DImode, &operands[0], 2, &operands[2], &operands[4]);")
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(define_split
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[(set (match_operand:DI 0 "memory_operand")
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(match_operand:DI 1 "immediate_operand"))]
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"TARGET_64BIT && ((optimize > 0 && flag_peephole2)
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? epilogue_completed : reload_completed)
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&& !symbolic_operand (operands[1], DImode)
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&& !x86_64_immediate_operand (operands[1], DImode)"
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[(set (match_dup 2) (match_dup 3))
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(set (match_dup 4) (match_dup 5))]
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"split_double_mode (DImode, &operands[0], 2, &operands[2], &operands[4]);")
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(define_insn "*movdi_internal"
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[(set (match_operand:DI 0 "nonimmediate_operand"
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"=r ,o ,*y,m*y,*y,*x,m ,*x,*x,*x,m ,*x,*x,?*x,?*Ym")
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@ -2773,7 +2733,7 @@
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(define_expand "movtf"
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[(set (match_operand:TF 0 "nonimmediate_operand")
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(match_operand:TF 1 "nonimmediate_operand"))]
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"TARGET_SSE"
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"TARGET_64BIT || TARGET_SSE"
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{
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ix86_expand_move (TFmode, operands);
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DONE;
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@ -2785,11 +2745,10 @@
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""
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"ix86_expand_move (<MODE>mode, operands); DONE;")
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(define_insn "*movtf_internal"
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(define_insn "*movtf_internal_rex64"
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[(set (match_operand:TF 0 "nonimmediate_operand" "=x,x ,m,?*r ,!o")
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(match_operand:TF 1 "general_operand" "C ,xm,x,*roF,F*r"))]
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"TARGET_SSE
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&& !(MEM_P (operands[0]) && MEM_P (operands[1]))
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(match_operand:TF 1 "general_operand" "C ,xm,x,*roF,*r"))]
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"TARGET_64BIT && !(MEM_P (operands[0]) && MEM_P (operands[1]))
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&& (!can_create_pseudo_p ()
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|| (ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_LARGE)
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|| GET_CODE (operands[1]) != CONST_DOUBLE
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@ -2849,11 +2808,101 @@
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]
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(const_string "TI")))])
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(define_insn "*movtf_internal_sse"
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[(set (match_operand:TF 0 "nonimmediate_operand" "=x,x ,m")
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(match_operand:TF 1 "general_operand" "C ,xm,x"))]
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"TARGET_SSE && !TARGET_64BIT
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&& !(MEM_P (operands[0]) && MEM_P (operands[1]))
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&& (!can_create_pseudo_p ()
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|| (ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_LARGE)
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|| GET_CODE (operands[1]) != CONST_DOUBLE
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|| (optimize_function_for_size_p (cfun)
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&& standard_sse_constant_p (operands[1])
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&& !memory_operand (operands[0], TFmode))
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|| (!TARGET_MEMORY_MISMATCH_STALL
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&& memory_operand (operands[0], TFmode)))"
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{
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switch (which_alternative)
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{
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case 0:
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return standard_sse_constant_opcode (insn, operands[1]);
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case 1:
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case 2:
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/* Handle misaligned load/store since we
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don't have movmisaligntf pattern. */
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if (misaligned_operand (operands[0], TFmode)
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|| misaligned_operand (operands[1], TFmode))
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{
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if (get_attr_mode (insn) == MODE_V4SF)
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return "%vmovups\t{%1, %0|%0, %1}";
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else
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return "%vmovdqu\t{%1, %0|%0, %1}";
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}
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else
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{
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if (get_attr_mode (insn) == MODE_V4SF)
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return "%vmovaps\t{%1, %0|%0, %1}";
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else
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return "%vmovdqa\t{%1, %0|%0, %1}";
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}
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default:
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gcc_unreachable ();
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}
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}
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[(set_attr "type" "sselog1,ssemov,ssemov")
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(set_attr "prefix" "maybe_vex")
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(set (attr "mode")
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(cond [(match_test "TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL")
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(const_string "V4SF")
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(and (eq_attr "alternative" "2")
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(match_test "TARGET_SSE_TYPELESS_STORES"))
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(const_string "V4SF")
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(match_test "TARGET_AVX")
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(const_string "TI")
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(ior (not (match_test "TARGET_SSE2"))
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(match_test "optimize_function_for_size_p (cfun)"))
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(const_string "V4SF")
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]
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(const_string "TI")))])
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(define_insn "*movxf_internal_rex64"
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[(set (match_operand:XF 0 "nonimmediate_operand" "=f,m,f,?Yx*r ,!o")
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(match_operand:XF 1 "general_operand" "fm,f,G,Yx*roF,Yx*r"))]
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"TARGET_64BIT && !(MEM_P (operands[0]) && MEM_P (operands[1]))
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&& (!can_create_pseudo_p ()
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|| (ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_LARGE)
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|| GET_CODE (operands[1]) != CONST_DOUBLE
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|| (optimize_function_for_size_p (cfun)
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&& standard_80387_constant_p (operands[1]) > 0
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&& !memory_operand (operands[0], XFmode))
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|| (!TARGET_MEMORY_MISMATCH_STALL
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&& memory_operand (operands[0], XFmode)))"
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{
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switch (which_alternative)
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{
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case 0:
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case 1:
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return output_387_reg_move (insn, operands);
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case 2:
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return standard_80387_constant_opcode (operands[1]);
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case 3:
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case 4:
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return "#";
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default:
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gcc_unreachable ();
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}
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}
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[(set_attr "type" "fmov,fmov,fmov,multi,multi")
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(set_attr "mode" "XF,XF,XF,SI,SI")])
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;; Possible store forwarding (partial memory) stall in alternative 4.
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(define_insn "*movxf_internal"
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[(set (match_operand:XF 0 "nonimmediate_operand" "=f,m,f,?Yx*r ,!o")
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(match_operand:XF 1 "general_operand" "fm,f,G,Yx*roF,FYx*r"))]
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"!(MEM_P (operands[0]) && MEM_P (operands[1]))
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"!TARGET_64BIT && !(MEM_P (operands[0]) && MEM_P (operands[1]))
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&& (!can_create_pseudo_p ()
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|| (ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_LARGE)
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|| GET_CODE (operands[1]) != CONST_DOUBLE
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@ -2885,9 +2934,9 @@
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(define_insn "*movdf_internal_rex64"
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[(set (match_operand:DF 0 "nonimmediate_operand"
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"=f,m,f,?r,?m,?r,!o,x,x,x,m,Yi,r ")
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"=f,m,f,?r,?m,?r,x,x,x,m,Yi,r ")
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(match_operand:DF 1 "general_operand"
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"fm,f,G,rm,r ,F ,F ,C,x,m,x,r ,Yi"))]
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"fm,f,G,rm,r ,F ,C,x,m,x,r ,Yi"))]
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"TARGET_64BIT && !(MEM_P (operands[0]) && MEM_P (operands[1]))
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&& (!can_create_pseudo_p ()
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|| (ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_LARGE)
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@ -2916,14 +2965,11 @@
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return "movabs{q}\t{%1, %0|%0, %1}";
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case 6:
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return "#";
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case 7:
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return standard_sse_constant_opcode (insn, operands[1]);
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case 7:
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case 8:
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case 9:
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case 10:
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switch (get_attr_mode (insn))
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{
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case MODE_V2DF:
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@ -2945,8 +2991,8 @@
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gcc_unreachable ();
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}
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case 10:
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case 11:
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case 12:
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/* Handle broken assemblers that require movd instead of movq. */
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return "%vmovd\t{%1, %0|%0, %1}";
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@ -2960,8 +3006,6 @@
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(eq_attr "alternative" "3,4,5")
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(const_string "imov")
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(eq_attr "alternative" "6")
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(const_string "multi")
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(eq_attr "alternative" "7")
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(const_string "sselog1")
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]
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(const_string "ssemov")))
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@ -2976,7 +3020,7 @@
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(const_string "8")
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(const_string "*")))
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(set (attr "prefix")
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(if_then_else (eq_attr "alternative" "0,1,2,3,4,5,6")
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(if_then_else (eq_attr "alternative" "0,1,2,3,4,5")
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(const_string "orig")
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(const_string "maybe_vex")))
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(set (attr "prefix_data16")
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@ -2986,11 +3030,11 @@
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(set (attr "mode")
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(cond [(eq_attr "alternative" "0,1,2")
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(const_string "DF")
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(eq_attr "alternative" "3,4,5,6,11,12")
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(eq_attr "alternative" "3,4,5,10,11")
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(const_string "DI")
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/* xorps is one byte shorter for !TARGET_AVX. */
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(eq_attr "alternative" "7")
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(eq_attr "alternative" "6")
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(cond [(match_test "TARGET_AVX")
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(const_string "V2DF")
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(match_test "optimize_function_for_size_p (cfun)")
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@ -3005,7 +3049,7 @@
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chains, otherwise use short move to avoid extra work.
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movaps encodes one byte shorter for !TARGET_AVX. */
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(eq_attr "alternative" "8")
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(eq_attr "alternative" "7")
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(cond [(match_test "TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL")
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(const_string "V4SF")
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(match_test "TARGET_SSE_PARTIAL_REG_DEPENDENCY")
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|
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@ -3019,7 +3063,7 @@
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/* For architectures resolving dependencies on register
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parts we may avoid extra work to zero out upper part
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of register. */
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(eq_attr "alternative" "9")
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(eq_attr "alternative" "8")
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(if_then_else
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(match_test "TARGET_SSE_SPLIT_REGS")
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(const_string "V1DF")
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|
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|
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@ -1,3 +1,8 @@
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2012-01-22 Uros Bizjak <ubizjak@gmail.com>
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|
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PR target/56028
|
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* gcc.target/i386/pr56028.c: New test.
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2013-01-22 Jakub Jelinek <jakub@redhat.com>
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PR target/55686
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|
|
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|||
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|
@ -0,0 +1,54 @@
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/* { dg-do compile { target { ! { ia32 } } } } */
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/* { dg-options "-O2" } */
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volatile int a, b, c, d, e, f, g, h, i, j, k, l, m, n, o, p;
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volatile long long y;
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void
|
||||
test ()
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{
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int a_ = a;
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||||
int b_ = b;
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||||
int c_ = c;
|
||||
int d_ = d;
|
||||
int e_ = e;
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int f_ = f;
|
||||
int g_ = g;
|
||||
int h_ = h;
|
||||
int i_ = i;
|
||||
int j_ = j;
|
||||
int k_ = k;
|
||||
int l_ = l;
|
||||
int m_ = m;
|
||||
int n_ = n;
|
||||
int o_ = o;
|
||||
int p_ = p;
|
||||
|
||||
int z;
|
||||
|
||||
for (z = 0; z < 1000; z++)
|
||||
{
|
||||
y = 0x100000002ll;
|
||||
y = 0x300000004ll;
|
||||
}
|
||||
|
||||
a = a_;
|
||||
b = b_;
|
||||
c = c_;
|
||||
d = d_;
|
||||
e = e_;
|
||||
f = f_;
|
||||
g = g_;
|
||||
h = h_;
|
||||
i = i_;
|
||||
j = j_;
|
||||
k = k_;
|
||||
l = l_;
|
||||
m = m_;
|
||||
n = n_;
|
||||
o = o_;
|
||||
p = p_;
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler-times "movabs" 2 } } */
|
||||
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