avr-protos.h (avr_out_sbxx_branch): Declare.
* config/avr/avr-protos.h (avr_out_sbxx_branch): Declare. * config/avr/avr.c (jump_over_one_insn_p): Take length of the branch insn into account, do not assume 1. (avr_out_sbxx_branch): New function. Optimize cases of skipping over single word insn. Handle upper half of I/O space too. * config/avr/avr.md (*sbrx_branch): Use it. (*sbrx_and_branchhi, *sbrx_and_branchsi): Likewise. (*sbix_branch, *sbix_branch_bit7): Likewise. (*sbix_branch_tmp, *sbix_branch_tmp_bit7): New. Use RTL peepholes to optimize register operand sign tests. From-SVN: r53906
This commit is contained in:
parent
9059e33cbb
commit
331ca3501d
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@ -25,6 +25,19 @@
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(_cpp_parse_expr, reduce): Update to handle two-integers.
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* cpplib.c (_cpp_test_assertion): Back up on CPP_EOF.
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2002-05-26 Marek Michalkiewicz <marekm@amelek.gda.pl>
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* config/avr/avr-protos.h (avr_out_sbxx_branch): Declare.
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* config/avr/avr.c (jump_over_one_insn_p): Take length of the
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branch insn into account, do not assume 1.
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(avr_out_sbxx_branch): New function. Optimize cases of skipping
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over single word insn. Handle upper half of I/O space too.
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* config/avr/avr.md (*sbrx_branch): Use it.
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(*sbrx_and_branchhi, *sbrx_and_branchsi): Likewise.
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(*sbix_branch, *sbix_branch_bit7): Likewise.
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(*sbix_branch_tmp, *sbix_branch_tmp_bit7): New.
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Use RTL peepholes to optimize register operand sign tests.
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2002-05-26 Marek Michalkiewicz <marekm@amelek.gda.pl>
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* config/avr/avr.c (avr_asm_only_p): New variable.
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@ -98,6 +98,7 @@ extern const char * lshrsi3_out PARAMS ((rtx insn, rtx operands[], int *len));
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extern void avr_output_bld PARAMS ((rtx operands[], int bit_nr));
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extern void avr_output_addr_vec_elt PARAMS ((FILE *stream, int value));
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extern const char *avr_out_sbxx_branch PARAMS ((rtx insn, rtx operands[]));
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extern enum reg_class preferred_reload_class PARAMS ((rtx x,
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enum reg_class class));
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@ -5233,7 +5233,7 @@ jump_over_one_insn_p (insn, dest)
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: dest);
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int jump_addr = INSN_ADDRESSES (INSN_UID (insn));
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int dest_addr = INSN_ADDRESSES (uid);
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return dest_addr - jump_addr == 2;
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return dest_addr - jump_addr == get_attr_length (insn) + 1;
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}
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/* Returns 1 if a value of mode MODE can be stored starting with hard
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@ -5451,3 +5451,76 @@ avr_peep2_scratch_safe (scratch)
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}
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return 1;
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}
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/* Output a branch that tests a single bit of a register (QI, HI or SImode)
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or memory location in the I/O space (QImode only).
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Operand 0: comparison operator (must be EQ or NE, compare bit to zero).
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Operand 1: register operand to test, or CONST_INT memory address.
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Operand 2: bit number (for QImode operand) or mask (HImode, SImode).
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Operand 3: label to jump to if the test is true. */
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const char *
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avr_out_sbxx_branch (insn, operands)
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rtx insn;
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rtx operands[];
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{
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enum rtx_code comp = GET_CODE (operands[0]);
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int long_jump = (get_attr_length (insn) >= 4);
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int reverse = long_jump || jump_over_one_insn_p (insn, operands[3]);
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if (comp == GE)
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comp = EQ;
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else if (comp == LT)
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comp = NE;
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if (reverse)
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comp = reverse_condition (comp);
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if (GET_CODE (operands[1]) == CONST_INT)
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{
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if (INTVAL (operands[1]) < 0x40)
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{
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if (comp == EQ)
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output_asm_insn (AS2 (sbis,%1-0x20,%2), operands);
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else
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output_asm_insn (AS2 (sbic,%1-0x20,%2), operands);
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}
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else
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{
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output_asm_insn (AS2 (in,__tmp_reg__,%1-0x20), operands);
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if (comp == EQ)
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output_asm_insn (AS2 (sbrs,__tmp_reg__,%2), operands);
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else
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output_asm_insn (AS2 (sbrc,__tmp_reg__,%2), operands);
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}
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}
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else /* GET_CODE (operands[1]) == REG */
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{
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if (GET_MODE (operands[1]) == QImode)
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{
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if (comp == EQ)
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output_asm_insn (AS2 (sbrs,%1,%2), operands);
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else
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output_asm_insn (AS2 (sbrc,%1,%2), operands);
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}
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else /* HImode or SImode */
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{
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static char buf[] = "sbrc %A1,0";
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int bit_nr = exact_log2 (INTVAL (operands[2])
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& GET_MODE_MASK (GET_MODE (operands[1])));
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buf[3] = (comp == EQ) ? 's' : 'c';
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buf[6] = 'A' + (bit_nr >> 3);
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buf[9] = '0' + (bit_nr & 7);
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output_asm_insn (buf, operands);
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}
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}
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if (long_jump)
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return (AS1 (rjmp,_PC_+4) CR_TAB
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AS1 (jmp,%3));
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if (!reverse)
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return AS1 (rjmp,%3);
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return "";
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}
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@ -1850,6 +1850,7 @@
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""
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"")
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;; Test a single bit in a QI/HI/SImode register.
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(define_insn "*sbrx_branch"
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[(set (pc)
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(if_then_else
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@ -1857,61 +1858,12 @@
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[(zero_extract
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(match_operand:QI 1 "register_operand" "r")
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(const_int 1)
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(match_operand 2 "immediate_operand" "n"))
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(match_operand 2 "const_int_operand" "n"))
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(const_int 0)])
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(label_ref (match_operand 3 "" ""))
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(pc)))]
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"(GET_CODE (operands[0]) == EQ || GET_CODE (operands[0]) == NE)"
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"* {
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int comp = ((get_attr_length (insn) == 4)
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? reverse_condition (GET_CODE (operands[0]))
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: GET_CODE (operands[0]));
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if (comp == EQ)
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output_asm_insn (AS2 (sbrs,%1,%2), operands);
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else
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output_asm_insn (AS2 (sbrc,%1,%2), operands);
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if (get_attr_length (insn) != 4)
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return AS1 (rjmp,%3);
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return (AS1 (rjmp,_PC_+4) CR_TAB
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AS1 (jmp,%3));
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}"
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[(set (attr "length")
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(if_then_else (and (ge (minus (pc) (match_dup 3)) (const_int -2046))
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(le (minus (pc) (match_dup 3)) (const_int 2046)))
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(const_int 2)
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(if_then_else (eq_attr "mcu_mega" "no")
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(const_int 2)
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(const_int 4))))
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(set_attr "cc" "clobber")])
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(define_insn "*sbrx_and_branchsi"
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[(set (pc)
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(if_then_else
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(match_operator 0 "comparison_operator"
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[(and:SI
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(match_operand:SI 1 "register_operand" "r")
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(match_operand:SI 2 "immediate_operand" "n"))
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(const_int 0)])
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(label_ref (match_operand 3 "" ""))
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(pc)))]
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"(GET_CODE (operands[0]) == EQ || GET_CODE (operands[0]) == NE)
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&& mask_one_bit_p(INTVAL (operands[2]))"
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"* {
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int comp = ((get_attr_length (insn) == 4)
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? reverse_condition (GET_CODE (operands[0]))
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: GET_CODE (operands[0]));
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int bit = mask_one_bit_p(INTVAL (operands[2])) - 1;
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static char buf[] = \"sbrc %A1,0\";
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buf[3] = (comp == EQ ? 's' : 'c');
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buf[6] = bit / 8 + 'A';
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buf[9] = bit % 8 + '0';
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output_asm_insn (buf, operands);
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if (get_attr_length (insn) != 4)
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return AS1 (rjmp,%3);
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return (AS1 (rjmp,_PC_+4) CR_TAB
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AS1 (jmp,%3));
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}"
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"GET_CODE (operands[0]) == EQ || GET_CODE (operands[0]) == NE"
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"* return avr_out_sbxx_branch (insn, operands);"
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[(set (attr "length")
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(if_then_else (and (ge (minus (pc) (match_dup 3)) (const_int -2046))
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(le (minus (pc) (match_dup 3)) (const_int 2046)))
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(match_operator 0 "comparison_operator"
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[(and:HI
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(match_operand:HI 1 "register_operand" "r")
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(match_operand:HI 2 "immediate_operand" "n"))
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(match_operand:HI 2 "const_int_operand" "n"))
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(const_int 0)])
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(label_ref (match_operand 3 "" ""))
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(pc)))]
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"(GET_CODE (operands[0]) == EQ || GET_CODE (operands[0]) == NE)
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&& mask_one_bit_p(INTVAL (operands[2]))"
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"* {
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int comp = ((get_attr_length (insn) == 4)
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? reverse_condition (GET_CODE (operands[0]))
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: GET_CODE (operands[0]));
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int bit = mask_one_bit_p(INTVAL (operands[2])) - 1;
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static char buf[] = \"sbrc %A1,0\";
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buf[3] = (comp == EQ ? 's' : 'c');
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buf[6] = bit / 8 + 'A';
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buf[9] = bit % 8 + '0';
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output_asm_insn (buf, operands);
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if (get_attr_length (insn) != 4)
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return AS1 (rjmp,%3);
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return (AS1 (rjmp,_PC_+4) CR_TAB
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AS1 (jmp,%3));
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}"
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&& exact_log2 (INTVAL (operands[2]) & 0xffff) >= 0"
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"* return avr_out_sbxx_branch (insn, operands);"
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[(set (attr "length")
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(if_then_else (and (ge (minus (pc) (match_dup 3)) (const_int -2046))
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(le (minus (pc) (match_dup 3)) (const_int 2046)))
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@ -1958,6 +1895,105 @@
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(const_int 4))))
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(set_attr "cc" "clobber")])
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(define_insn "*sbrx_and_branchsi"
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[(set (pc)
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(if_then_else
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(match_operator 0 "comparison_operator"
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[(and:SI
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(match_operand:SI 1 "register_operand" "r")
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(match_operand:SI 2 "const_int_operand" "n"))
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(const_int 0)])
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(label_ref (match_operand 3 "" ""))
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(pc)))]
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"(GET_CODE (operands[0]) == EQ || GET_CODE (operands[0]) == NE)
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&& exact_log2 (INTVAL (operands[2]) & 0xffffffff) >= 0"
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"* return avr_out_sbxx_branch (insn, operands);"
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[(set (attr "length")
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(if_then_else (and (ge (minus (pc) (match_dup 3)) (const_int -2046))
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(le (minus (pc) (match_dup 3)) (const_int 2046)))
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(const_int 2)
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(if_then_else (eq_attr "mcu_mega" "no")
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(const_int 2)
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(const_int 4))))
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(set_attr "cc" "clobber")])
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;; Convert sign tests to bit 7/15/31 tests that match the above insns.
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(define_peephole2
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[(set (cc0) (match_operand:QI 0 "register_operand" ""))
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(set (pc) (if_then_else (ge (cc0) (const_int 0))
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(label_ref (match_operand 1 "" ""))
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(pc)))]
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""
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[(set (pc) (if_then_else (eq (zero_extract (match_dup 0)
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(const_int 1)
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(const_int 7))
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(const_int 0))
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(label_ref (match_dup 1))
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(pc)))]
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"")
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(define_peephole2
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[(set (cc0) (match_operand:QI 0 "register_operand" ""))
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(set (pc) (if_then_else (lt (cc0) (const_int 0))
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(label_ref (match_operand 1 "" ""))
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(pc)))]
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""
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[(set (pc) (if_then_else (ne (zero_extract (match_dup 0)
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(const_int 1)
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(const_int 7))
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(const_int 0))
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(label_ref (match_dup 1))
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(pc)))]
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"")
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(define_peephole2
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[(set (cc0) (match_operand:HI 0 "register_operand" ""))
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(set (pc) (if_then_else (ge (cc0) (const_int 0))
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(label_ref (match_operand 1 "" ""))
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(pc)))]
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""
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[(set (pc) (if_then_else (eq (and:HI (match_dup 0) (const_int -32768))
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(const_int 0))
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(label_ref (match_dup 1))
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(pc)))]
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"")
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(define_peephole2
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[(set (cc0) (match_operand:HI 0 "register_operand" ""))
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(set (pc) (if_then_else (lt (cc0) (const_int 0))
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(label_ref (match_operand 1 "" ""))
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(pc)))]
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""
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[(set (pc) (if_then_else (ne (and:HI (match_dup 0) (const_int -32768))
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(const_int 0))
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(label_ref (match_dup 1))
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(pc)))]
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"")
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(define_peephole2
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[(set (cc0) (match_operand:SI 0 "register_operand" ""))
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(set (pc) (if_then_else (ge (cc0) (const_int 0))
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(label_ref (match_operand 1 "" ""))
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(pc)))]
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""
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[(set (pc) (if_then_else (eq (and:SI (match_dup 0) (match_dup 2))
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(const_int 0))
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(label_ref (match_dup 1))
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(pc)))]
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"operands[2] = GEN_INT (0x80000000);")
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(define_peephole2
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[(set (cc0) (match_operand:SI 0 "register_operand" ""))
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(set (pc) (if_then_else (lt (cc0) (const_int 0))
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(label_ref (match_operand 1 "" ""))
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(pc)))]
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""
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[(set (pc) (if_then_else (ne (and:SI (match_dup 0) (match_dup 2))
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(const_int 0))
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(label_ref (match_dup 1))
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(pc)))]
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"operands[2] = GEN_INT (0x80000000);")
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;; ************************************************************************
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;; Implementation of conditional jumps here.
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;; Compare with 0 (test) jumps
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|
@ -2258,6 +2294,7 @@
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[(set_attr "length" "1")
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(set_attr "cc" "none")])
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;; Lower half of the I/O space - use sbic/sbis directly.
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(define_insn "*sbix_branch"
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[(set (pc)
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(if_then_else
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|
@ -2271,21 +2308,7 @@
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(pc)))]
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"(GET_CODE (operands[0]) == EQ || GET_CODE (operands[0]) == NE)
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&& avr_io_address_p (operands[1], 1 + 0x20)"
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{
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enum rtx_code comp = GET_CODE (operands[0]);
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int reverse = (get_attr_length (insn) == 4);
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if (reverse)
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comp = reverse_condition (comp);
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if (comp == EQ)
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output_asm_insn (AS2 (sbis,%1-0x20,%2), operands);
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else
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output_asm_insn (AS2 (sbic,%1-0x20,%2), operands);
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if (!reverse)
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return AS1 (rjmp,%3);
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return (AS1 (rjmp,_PC_+4) CR_TAB
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AS1 (jmp,%3));
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}
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"* return avr_out_sbxx_branch (insn, operands);"
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[(set (attr "length")
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(if_then_else (and (ge (minus (pc) (match_dup 3)) (const_int -2046))
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(le (minus (pc) (match_dup 3)) (const_int 2046)))
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|
@ -2307,19 +2330,9 @@
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"(GET_CODE (operands[0]) == GE || GET_CODE (operands[0]) == LT)
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&& avr_io_address_p (operands[1], 1 + 0x20)"
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{
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enum rtx_code comp = GET_CODE (operands[0]);
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int reverse = (get_attr_length (insn) == 4);
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if (reverse)
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comp = reverse_condition (comp);
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if (comp == GE)
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output_asm_insn (AS2 (sbis,%1-0x20,7), operands);
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else
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output_asm_insn (AS2 (sbic,%1-0x20,7), operands);
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if (!reverse)
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return AS1 (rjmp,%2);
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return (AS1 (rjmp,_PC_+4) CR_TAB
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AS1 (jmp,%2));
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operands[3] = operands[2];
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operands[2] = GEN_INT (7);
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return avr_out_sbxx_branch (insn, operands);
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}
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[(set (attr "length")
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(if_then_else (and (ge (minus (pc) (match_dup 2)) (const_int -2046))
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|
@ -2330,6 +2343,54 @@
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(const_int 4))))
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(set_attr "cc" "clobber")])
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|
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;; Upper half of the I/O space - read port to __tmp_reg__ and use sbrc/sbrs.
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(define_insn "*sbix_branch_tmp"
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[(set (pc)
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(if_then_else
|
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(match_operator 0 "comparison_operator"
|
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[(zero_extract
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(mem:QI (match_operand 1 "const_int_operand" "n"))
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(const_int 1)
|
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(match_operand 2 "const_int_operand" "n"))
|
||||
(const_int 0)])
|
||||
(label_ref (match_operand 3 "" ""))
|
||||
(pc)))]
|
||||
"(GET_CODE (operands[0]) == EQ || GET_CODE (operands[0]) == NE)
|
||||
&& avr_io_address_p (operands[1], 1) && INTVAL (operands[1]) >= 0x40"
|
||||
"* return avr_out_sbxx_branch (insn, operands);"
|
||||
[(set (attr "length")
|
||||
(if_then_else (and (ge (minus (pc) (match_dup 3)) (const_int -2046))
|
||||
(le (minus (pc) (match_dup 3)) (const_int 2045)))
|
||||
(const_int 3)
|
||||
(if_then_else (eq_attr "mcu_mega" "no")
|
||||
(const_int 3)
|
||||
(const_int 5))))
|
||||
(set_attr "cc" "clobber")])
|
||||
|
||||
(define_insn "*sbix_branch_tmp_bit7"
|
||||
[(set (pc)
|
||||
(if_then_else
|
||||
(match_operator 0 "comparison_operator"
|
||||
[(mem:QI (match_operand 1 "const_int_operand" "n"))
|
||||
(const_int 0)])
|
||||
(label_ref (match_operand 2 "" ""))
|
||||
(pc)))]
|
||||
"(GET_CODE (operands[0]) == GE || GET_CODE (operands[0]) == LT)
|
||||
&& avr_io_address_p (operands[1], 1) && INTVAL (operands[1]) >= 0x40"
|
||||
{
|
||||
operands[3] = operands[2];
|
||||
operands[2] = GEN_INT (7);
|
||||
return avr_out_sbxx_branch (insn, operands);
|
||||
}
|
||||
[(set (attr "length")
|
||||
(if_then_else (and (ge (minus (pc) (match_dup 2)) (const_int -2046))
|
||||
(le (minus (pc) (match_dup 2)) (const_int 2045)))
|
||||
(const_int 3)
|
||||
(if_then_else (eq_attr "mcu_mega" "no")
|
||||
(const_int 3)
|
||||
(const_int 5))))
|
||||
(set_attr "cc" "clobber")])
|
||||
|
||||
;; ************************* Peepholes ********************************
|
||||
|
||||
(define_peephole
|
||||
|
@ -2430,60 +2491,6 @@
|
|||
return (AS1 (brcs,_PC_+4) CR_TAB
|
||||
AS1 (jmp,%1));
|
||||
}")
|
||||
|
||||
(define_peephole
|
||||
[(set (cc0) (match_operand:QI 0 "register_operand" ""))
|
||||
(set (pc)
|
||||
(if_then_else (lt (cc0) (const_int 0))
|
||||
(label_ref (match_operand 1 "" ""))
|
||||
(pc)))]
|
||||
"jump_over_one_insn_p (insn, operands[1])"
|
||||
"sbrs %0,7")
|
||||
|
||||
(define_peephole
|
||||
[(set (cc0) (match_operand:QI 0 "register_operand" ""))
|
||||
(set (pc)
|
||||
(if_then_else (ge (cc0) (const_int 0))
|
||||
(label_ref (match_operand 1 "" ""))
|
||||
(pc)))]
|
||||
"jump_over_one_insn_p (insn, operands[1])"
|
||||
"sbrc %0,7")
|
||||
|
||||
(define_peephole
|
||||
[(set (cc0) (match_operand:HI 0 "register_operand" ""))
|
||||
(set (pc)
|
||||
(if_then_else (lt (cc0) (const_int 0))
|
||||
(label_ref (match_operand 1 "" ""))
|
||||
(pc)))]
|
||||
"jump_over_one_insn_p (insn, operands[1])"
|
||||
"sbrs %B0,7")
|
||||
|
||||
(define_peephole
|
||||
[(set (cc0) (match_operand:HI 0 "register_operand" ""))
|
||||
(set (pc)
|
||||
(if_then_else (ge (cc0) (const_int 0))
|
||||
(label_ref (match_operand 1 "" ""))
|
||||
(pc)))]
|
||||
"jump_over_one_insn_p (insn, operands[1])"
|
||||
"sbrc %B0,7")
|
||||
|
||||
(define_peephole
|
||||
[(set (cc0) (match_operand:SI 0 "register_operand" ""))
|
||||
(set (pc)
|
||||
(if_then_else (lt (cc0) (const_int 0))
|
||||
(label_ref (match_operand 1 "" ""))
|
||||
(pc)))]
|
||||
"jump_over_one_insn_p (insn, operands[1])"
|
||||
"sbrs %D0,7")
|
||||
|
||||
(define_peephole
|
||||
[(set (cc0) (match_operand:SI 0 "register_operand" ""))
|
||||
(set (pc)
|
||||
(if_then_else (ge (cc0) (const_int 0))
|
||||
(label_ref (match_operand 1 "" ""))
|
||||
(pc)))]
|
||||
"jump_over_one_insn_p (insn, operands[1])"
|
||||
"sbrc %D0,7")
|
||||
|
||||
(define_peephole
|
||||
[(set (cc0) (match_operand:QI 0 "register_operand" ""))
|
||||
|
|
Loading…
Reference in New Issue