mmx.md: Remove double backslashes from asm templates.
* config/i386/mmx.md: Remove double backslashes from asm templates. (*addv2sf3): Rename from mmx_addv2sf3 insn pattern. (mmx_addv2sf3): New expander. Use ix86_fixup_binary_operands_no_copy to handle nonimmediate operands. (*mulv2sf3): Rename from mmx_mulv2sf3 insn pattern. (mmx_mulv2sf3): New expander. Use ix86_fixup_binary_operands_no_copy to handle nonimmediate operands. (*<code>v2sf3_finite): New insn pattern. (*<code>v2sf3): Rename from mmx_<code>v2sf3 insn pattern. (mmx_<code>v2sf3): New expander. Use ix86_fixup_binary_operands_no_copy to handle nonimmediate operands. (mmx_<plusminus_insn><mode>3): New expander. Use ix86_fixup_binary_operands_no_copy to handle nonimmediate operands. (*<plusminus_insn><mode>3): New insn pattern. (mmx_add<mode>3): Removed. (mmx_ssadd<mode>3): Ditto. (mmx_usadd<mode>3): Ditto. (mmx_sub<mode>3): Ditto. (mmx_sssub<mode>3): Ditto. (mmx_ussub<mode>3): Ditto. (*mulv4hi3): Rename from mmx_mulv4hi3 insn pattern. (mmx_mulv4hi3): New expander. Use ix86_fixup_binary_operands_no_copy to handle nonimmediate operands. (*smulv4hi3_highpart): Rename from mmx_smulv4hi3_highpart insn pattern. (mmx_smulv4hi3_highpart): New expander. Use ix86_fixup_binary_operands_no_copy to handle nonimmediate operands. (*umulv4hi3_highpart): Rename from mmx_umulv4hi3_highpart insn pattern. (mmx_umulv4hi3_highpart): New expander. Use ix86_fixup_binary_operands_no_copy to handle nonimmediate operands. (*<code>v4hi3): Rename from mmx_<code>v4hi3 insn pattern. (mmx_<code>v4hi3): New expander. Use ix86_fixup_binary_operands_no_copy to handle nonimmediate operands. (*<code>v8qi3): Rename from mmx_<code>v8qi3 insn pattern. (mmx_<code>v8qi3): New expander. Use ix86_fixup_binary_operands_no_copy to handle nonimmediate operands. (*<code><mode>3): Rename from mmx_<code><mode>3 insn pattern. (mmx_<code><mode>3): New expander. Use ix86_fixup_binary_operands_no_copy to handle nonimmediate operands. From-SVN: r134976
This commit is contained in:
Uros Bizjak
parent
3716f2332c
commit
333d8f61a2
@ -1,3 +1,46 @@
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2008-05-06 Uros Bizjak <ubizjak@gmail.com>
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* config/i386/mmx.md: Remove double backslashes from asm templates.
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(*addv2sf3): Rename from mmx_addv2sf3 insn pattern.
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(mmx_addv2sf3): New expander. Use ix86_fixup_binary_operands_no_copy
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to handle nonimmediate operands.
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(*mulv2sf3): Rename from mmx_mulv2sf3 insn pattern.
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(mmx_mulv2sf3): New expander. Use ix86_fixup_binary_operands_no_copy
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to handle nonimmediate operands.
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(*<code>v2sf3_finite): New insn pattern.
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(*<code>v2sf3): Rename from mmx_<code>v2sf3 insn pattern.
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(mmx_<code>v2sf3): New expander. Use
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ix86_fixup_binary_operands_no_copy to handle nonimmediate operands.
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(mmx_<plusminus_insn><mode>3): New expander. Use
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ix86_fixup_binary_operands_no_copy to handle nonimmediate operands.
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(*<plusminus_insn><mode>3): New insn pattern.
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(mmx_add<mode>3): Removed.
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(mmx_ssadd<mode>3): Ditto.
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(mmx_usadd<mode>3): Ditto.
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(mmx_sub<mode>3): Ditto.
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(mmx_sssub<mode>3): Ditto.
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(mmx_ussub<mode>3): Ditto.
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(*mulv4hi3): Rename from mmx_mulv4hi3 insn pattern.
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(mmx_mulv4hi3): New expander. Use ix86_fixup_binary_operands_no_copy
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to handle nonimmediate operands.
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(*smulv4hi3_highpart): Rename from mmx_smulv4hi3_highpart
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insn pattern.
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(mmx_smulv4hi3_highpart): New expander. Use
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ix86_fixup_binary_operands_no_copy to handle nonimmediate operands.
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(*umulv4hi3_highpart): Rename from mmx_umulv4hi3_highpart
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insn pattern.
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(mmx_umulv4hi3_highpart): New expander. Use
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ix86_fixup_binary_operands_no_copy to handle nonimmediate operands.
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(*<code>v4hi3): Rename from mmx_<code>v4hi3 insn pattern.
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(mmx_<code>v4hi3): New expander. Use
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ix86_fixup_binary_operands_no_copy to handle nonimmediate operands.
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(*<code>v8qi3): Rename from mmx_<code>v8qi3 insn pattern.
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(mmx_<code>v8qi3): New expander. Use
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ix86_fixup_binary_operands_no_copy to handle nonimmediate operands.
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(*<code><mode>3): Rename from mmx_<code><mode>3 insn pattern.
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(mmx_<code><mode>3): New expander. Use
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ix86_fixup_binary_operands_no_copy to handle nonimmediate operands.
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2008-05-05 Jan Hubicka <jh@suse.cz>
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PR tree-optimization/36118
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@ -6,8 +49,8 @@
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2008-05-05 Andrew Pinski <andrew_pinski@playstation.sony.com>
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PR middle-end/36141
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* tree-ssa-forwprop.c (forward_propagate_addr_expr_1): Don't create VCE
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for function decls.
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* tree-ssa-forwprop.c (forward_propagate_addr_expr_1): Don't create
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VCE for function decls.
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2008-05-05 H.J. Lu <hongjiu.lu@intel.com>
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@ -55,9 +98,9 @@
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Generalize UNUSED macro.
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(__gthread_once): Add.
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(__gthread_key_create): Add.
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(__gthread_key_delete): Add.
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(__gthread_key_delete): Add.
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(__gthread_getspecific): Add.
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(__gthread_setspecific): Add.
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(__gthread_setspecific): Add.
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2008-05-05 Andrew Pinski <Andrew.Pinski@playstation.sony.com>
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@ -1,5 +1,5 @@
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;; GCC machine description for MMX and 3dNOW! instructions
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;; Copyright (C) 2005, 2007
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;; Copyright (C) 2005, 2007, 2008
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;; Free Software Foundation, Inc.
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;;
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;; This file is part of GCC.
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@ -212,12 +212,20 @@
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;;
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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(define_insn "mmx_addv2sf3"
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(define_expand "mmx_addv2sf3"
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[(set (match_operand:V2SF 0 "register_operand" "")
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(plus:V2SF
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(match_operand:V2SF 1 "nonimmediate_operand" "")
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(match_operand:V2SF 2 "nonimmediate_operand" "")))]
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"TARGET_3DNOW"
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"ix86_fixup_binary_operands_no_copy (PLUS, V2SFmode, operands);")
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(define_insn "*addv2sf3"
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[(set (match_operand:V2SF 0 "register_operand" "=y")
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(plus:V2SF (match_operand:V2SF 1 "nonimmediate_operand" "%0")
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(match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
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"TARGET_3DNOW && ix86_binary_operator_ok (PLUS, V2SFmode, operands)"
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"pfadd\\t{%2, %0|%0, %2}"
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"pfadd\t{%2, %0|%0, %2}"
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[(set_attr "type" "mmxadd")
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(set_attr "mode" "V2SF")])
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@ -227,8 +235,8 @@
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(match_operand:V2SF 2 "nonimmediate_operand" "ym,0")))]
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"TARGET_3DNOW && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
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"@
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pfsub\\t{%2, %0|%0, %2}
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pfsubr\\t{%2, %0|%0, %2}"
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pfsub\t{%2, %0|%0, %2}
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pfsubr\t{%2, %0|%0, %2}"
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[(set_attr "type" "mmxadd")
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(set_attr "mode" "V2SF")])
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@ -239,22 +247,56 @@
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"TARGET_3DNOW && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
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"")
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(define_insn "mmx_mulv2sf3"
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(define_expand "mmx_mulv2sf3"
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[(set (match_operand:V2SF 0 "register_operand" "")
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(mult:V2SF (match_operand:V2SF 1 "nonimmediate_operand" "")
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(match_operand:V2SF 2 "nonimmediate_operand" "")))]
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"TARGET_3DNOW"
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"ix86_fixup_binary_operands_no_copy (MULT, V2SFmode, operands);")
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(define_insn "*mulv2sf3"
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[(set (match_operand:V2SF 0 "register_operand" "=y")
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(mult:V2SF (match_operand:V2SF 1 "nonimmediate_operand" "%0")
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(match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
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"TARGET_3DNOW && ix86_binary_operator_ok (MULT, V2SFmode, operands)"
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"pfmul\\t{%2, %0|%0, %2}"
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"pfmul\t{%2, %0|%0, %2}"
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[(set_attr "type" "mmxmul")
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(set_attr "mode" "V2SF")])
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(define_insn "mmx_<code>v2sf3"
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;; ??? For !flag_finite_math_only, the representation with SMIN/SMAX
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;; isn't really correct, as those rtl operators aren't defined when
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;; applied to NaNs. Hopefully the optimizers won't get too smart on us.
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(define_expand "mmx_<code>v2sf3"
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[(set (match_operand:V2SF 0 "register_operand" "")
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(smaxmin:V2SF
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(match_operand:V2SF 1 "nonimmediate_operand" "")
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(match_operand:V2SF 2 "nonimmediate_operand" "")))]
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"TARGET_3DNOW"
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{
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if (!flag_finite_math_only)
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operands[1] = force_reg (V2SFmode, operands[1]);
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ix86_fixup_binary_operands_no_copy (<CODE>, V2SFmode, operands);
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})
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(define_insn "*<code>v2sf3_finite"
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[(set (match_operand:V2SF 0 "register_operand" "=y")
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(smaxmin:V2SF
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(match_operand:V2SF 1 "nonimmediate_operand" "%0")
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(match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
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"TARGET_3DNOW && ix86_binary_operator_ok (SMAX, V2SFmode, operands)"
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"pf<maxminfprefix>\\t{%2, %0|%0, %2}"
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"TARGET_3DNOW && flag_finite_math_only
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&& ix86_binary_operator_ok (<CODE>, V2SFmode, operands)"
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"pf<maxminfprefix>\t{%2, %0|%0, %2}"
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[(set_attr "type" "mmxadd")
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(set_attr "mode" "V2SF")])
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(define_insn "*<code>v2sf3"
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[(set (match_operand:V2SF 0 "register_operand" "=y")
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(smaxmin:V2SF
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(match_operand:V2SF 1 "register_operand" "0")
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(match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
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"TARGET_3DNOW"
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"pf<maxminfprefix>\t{%2, %0|%0, %2}"
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[(set_attr "type" "mmxadd")
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(set_attr "mode" "V2SF")])
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@ -263,7 +305,7 @@
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(unspec:V2SF [(match_operand:V2SF 1 "nonimmediate_operand" "ym")]
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UNSPEC_PFRCP))]
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"TARGET_3DNOW"
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"pfrcp\\t{%1, %0|%0, %1}"
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"pfrcp\t{%1, %0|%0, %1}"
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[(set_attr "type" "mmx")
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(set_attr "mode" "V2SF")])
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@ -273,7 +315,7 @@
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(match_operand:V2SF 2 "nonimmediate_operand" "ym")]
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UNSPEC_PFRCPIT1))]
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"TARGET_3DNOW"
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"pfrcpit1\\t{%2, %0|%0, %2}"
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"pfrcpit1\t{%2, %0|%0, %2}"
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[(set_attr "type" "mmx")
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(set_attr "mode" "V2SF")])
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@ -283,7 +325,7 @@
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(match_operand:V2SF 2 "nonimmediate_operand" "ym")]
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UNSPEC_PFRCPIT2))]
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"TARGET_3DNOW"
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"pfrcpit2\\t{%2, %0|%0, %2}"
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"pfrcpit2\t{%2, %0|%0, %2}"
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[(set_attr "type" "mmx")
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(set_attr "mode" "V2SF")])
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@ -292,7 +334,7 @@
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(unspec:V2SF [(match_operand:V2SF 1 "nonimmediate_operand" "ym")]
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UNSPEC_PFRSQRT))]
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"TARGET_3DNOW"
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"pfrsqrt\\t{%1, %0|%0, %1}"
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"pfrsqrt\t{%1, %0|%0, %1}"
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[(set_attr "type" "mmx")
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(set_attr "mode" "V2SF")])
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@ -302,7 +344,7 @@
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(match_operand:V2SF 2 "nonimmediate_operand" "ym")]
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UNSPEC_PFRSQIT1))]
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"TARGET_3DNOW"
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"pfrsqit1\\t{%2, %0|%0, %2}"
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"pfrsqit1\t{%2, %0|%0, %2}"
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[(set_attr "type" "mmx")
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(set_attr "mode" "V2SF")])
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@ -320,7 +362,7 @@
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(parallel [(const_int 0)]))
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(vec_select:SF (match_dup 2) (parallel [(const_int 1)])))))]
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"TARGET_3DNOW"
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"pfacc\\t{%2, %0|%0, %2}"
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"pfacc\t{%2, %0|%0, %2}"
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[(set_attr "type" "mmxadd")
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(set_attr "mode" "V2SF")])
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@ -338,7 +380,7 @@
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(parallel [(const_int 0)]))
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(vec_select:SF (match_dup 2) (parallel [(const_int 1)])))))]
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"TARGET_3DNOW_A"
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"pfnacc\\t{%2, %0|%0, %2}"
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"pfnacc\t{%2, %0|%0, %2}"
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[(set_attr "type" "mmxadd")
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(set_attr "mode" "V2SF")])
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@ -351,7 +393,7 @@
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(minus:V2SF (match_dup 1) (match_dup 2))
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(const_int 1)))]
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"TARGET_3DNOW_A"
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"pfpnacc\\t{%2, %0|%0, %2}"
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"pfpnacc\t{%2, %0|%0, %2}"
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[(set_attr "type" "mmxadd")
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(set_attr "mode" "V2SF")])
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@ -366,7 +408,7 @@
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(gt:V2SI (match_operand:V2SF 1 "register_operand" "0")
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(match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
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"TARGET_3DNOW"
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"pfcmpgt\\t{%2, %0|%0, %2}"
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"pfcmpgt\t{%2, %0|%0, %2}"
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[(set_attr "type" "mmxcmp")
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(set_attr "mode" "V2SF")])
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@ -375,7 +417,7 @@
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(ge:V2SI (match_operand:V2SF 1 "register_operand" "0")
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(match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
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"TARGET_3DNOW"
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"pfcmpge\\t{%2, %0|%0, %2}"
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"pfcmpge\t{%2, %0|%0, %2}"
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[(set_attr "type" "mmxcmp")
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(set_attr "mode" "V2SF")])
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@ -384,7 +426,7 @@
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(eq:V2SI (match_operand:V2SF 1 "nonimmediate_operand" "%0")
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(match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
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"TARGET_3DNOW && ix86_binary_operator_ok (EQ, V2SFmode, operands)"
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"pfcmpeq\\t{%2, %0|%0, %2}"
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"pfcmpeq\t{%2, %0|%0, %2}"
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[(set_attr "type" "mmxcmp")
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(set_attr "mode" "V2SF")])
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@ -398,7 +440,7 @@
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[(set (match_operand:V2SI 0 "register_operand" "=y")
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(fix:V2SI (match_operand:V2SF 1 "nonimmediate_operand" "ym")))]
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"TARGET_3DNOW"
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"pf2id\\t{%1, %0|%0, %1}"
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"pf2id\t{%1, %0|%0, %1}"
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[(set_attr "type" "mmxcvt")
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(set_attr "mode" "V2SF")])
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@ -409,7 +451,7 @@
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(fix:V2SI
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(match_operand:V2SF 1 "nonimmediate_operand" "ym")))))]
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"TARGET_3DNOW_A"
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"pf2iw\\t{%1, %0|%0, %1}"
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"pf2iw\t{%1, %0|%0, %1}"
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[(set_attr "type" "mmxcvt")
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(set_attr "mode" "V2SF")])
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@ -420,7 +462,7 @@
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(truncate:V2HI
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(match_operand:V2SI 1 "nonimmediate_operand" "ym")))))]
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"TARGET_3DNOW_A"
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"pi2fw\\t{%1, %0|%0, %1}"
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"pi2fw\t{%1, %0|%0, %1}"
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[(set_attr "type" "mmxcvt")
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(set_attr "mode" "V2SF")])
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@ -428,7 +470,7 @@
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[(set (match_operand:V2SF 0 "register_operand" "=y")
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(float:V2SF (match_operand:V2SI 1 "nonimmediate_operand" "ym")))]
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"TARGET_3DNOW"
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"pi2fd\\t{%1, %0|%0, %1}"
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"pi2fd\t{%1, %0|%0, %1}"
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[(set_attr "type" "mmxcvt")
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(set_attr "mode" "V2SF")])
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@ -443,7 +485,7 @@
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(vec_select:V2SF (match_operand:V2SF 1 "nonimmediate_operand" "ym")
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(parallel [(const_int 1) (const_int 0)])))]
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"TARGET_3DNOW_A"
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"pswapd\\t{%1, %0|%0, %1}"
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"pswapd\t{%1, %0|%0, %1}"
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[(set_attr "type" "mmxcvt")
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(set_attr "mode" "V2SF")])
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@ -550,68 +592,51 @@
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;;
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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(define_insn "mmx_add<mode>3"
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(define_expand "mmx_<plusminus_insn><mode>3"
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[(set (match_operand:MMXMODEI8 0 "register_operand" "")
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(plusminus:MMXMODEI8
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(match_operand:MMXMODEI8 1 "nonimmediate_operand" "")
|
||||
(match_operand:MMXMODEI8 2 "nonimmediate_operand" "")))]
|
||||
"TARGET_MMX || (TARGET_SSE2 && <MODE>mode == V1DImode)"
|
||||
"ix86_fixup_binary_operands_no_copy (<CODE>, <MODE>mode, operands);")
|
||||
|
||||
(define_insn "*<plusminus_insn><mode>3"
|
||||
[(set (match_operand:MMXMODEI8 0 "register_operand" "=y")
|
||||
(plus:MMXMODEI8
|
||||
(match_operand:MMXMODEI8 1 "nonimmediate_operand" "%0")
|
||||
(plusminus:MMXMODEI8
|
||||
(match_operand:MMXMODEI8 1 "nonimmediate_operand" "<comm>0")
|
||||
(match_operand:MMXMODEI8 2 "nonimmediate_operand" "ym")))]
|
||||
"(TARGET_MMX || (TARGET_SSE2 && <MODE>mode == V1DImode))
|
||||
&& ix86_binary_operator_ok (PLUS, <MODE>mode, operands)"
|
||||
"padd<mmxvecsize>\t{%2, %0|%0, %2}"
|
||||
&& ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
|
||||
"p<plusminus_mnemonic><mmxvecsize>\t{%2, %0|%0, %2}"
|
||||
[(set_attr "type" "mmxadd")
|
||||
(set_attr "mode" "DI")])
|
||||
|
||||
(define_insn "mmx_ssadd<mode>3"
|
||||
[(set (match_operand:MMXMODE12 0 "register_operand" "=y")
|
||||
(ss_plus:MMXMODE12
|
||||
(match_operand:MMXMODE12 1 "nonimmediate_operand" "%0")
|
||||
(match_operand:MMXMODE12 2 "nonimmediate_operand" "ym")))]
|
||||
(define_expand "mmx_<plusminus_insn><mode>3"
|
||||
[(set (match_operand:MMXMODE12 0 "register_operand" "")
|
||||
(sat_plusminus:MMXMODE12
|
||||
(match_operand:MMXMODE12 1 "nonimmediate_operand" "")
|
||||
(match_operand:MMXMODE12 2 "nonimmediate_operand" "")))]
|
||||
"TARGET_MMX"
|
||||
"padds<mmxvecsize>\t{%2, %0|%0, %2}"
|
||||
[(set_attr "type" "mmxadd")
|
||||
(set_attr "mode" "DI")])
|
||||
"ix86_fixup_binary_operands_no_copy (<CODE>, <MODE>mode, operands);")
|
||||
|
||||
(define_insn "mmx_usadd<mode>3"
|
||||
(define_insn "*<plusminus_insn><mode>3"
|
||||
[(set (match_operand:MMXMODE12 0 "register_operand" "=y")
|
||||
(us_plus:MMXMODE12
|
||||
(match_operand:MMXMODE12 1 "nonimmediate_operand" "%0")
|
||||
(sat_plusminus:MMXMODE12
|
||||
(match_operand:MMXMODE12 1 "nonimmediate_operand" "<comm>0")
|
||||
(match_operand:MMXMODE12 2 "nonimmediate_operand" "ym")))]
|
||||
"TARGET_MMX && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
|
||||
"p<plusminus_mnemonic><mmxvecsize>\t{%2, %0|%0, %2}"
|
||||
[(set_attr "type" "mmxadd")
|
||||
(set_attr "mode" "DI")])
|
||||
|
||||
(define_expand "mmx_mulv4hi3"
|
||||
[(set (match_operand:V4HI 0 "register_operand" "")
|
||||
(mult:V4HI (match_operand:V4HI 1 "nonimmediate_operand" "")
|
||||
(match_operand:V4HI 2 "nonimmediate_operand" "")))]
|
||||
"TARGET_MMX"
|
||||
"paddus<mmxvecsize>\t{%2, %0|%0, %2}"
|
||||
[(set_attr "type" "mmxadd")
|
||||
(set_attr "mode" "DI")])
|
||||
"ix86_fixup_binary_operands_no_copy (MULT, V4HImode, operands);")
|
||||
|
||||
(define_insn "mmx_sub<mode>3"
|
||||
[(set (match_operand:MMXMODEI8 0 "register_operand" "=y")
|
||||
(minus:MMXMODEI8
|
||||
(match_operand:MMXMODEI8 1 "register_operand" "0")
|
||||
(match_operand:MMXMODEI8 2 "nonimmediate_operand" "ym")))]
|
||||
"(TARGET_MMX || (TARGET_SSE2 && <MODE>mode == V1DImode))"
|
||||
"psub<mmxvecsize>\t{%2, %0|%0, %2}"
|
||||
[(set_attr "type" "mmxadd")
|
||||
(set_attr "mode" "DI")])
|
||||
|
||||
(define_insn "mmx_sssub<mode>3"
|
||||
[(set (match_operand:MMXMODE12 0 "register_operand" "=y")
|
||||
(ss_minus:MMXMODE12
|
||||
(match_operand:MMXMODE12 1 "register_operand" "0")
|
||||
(match_operand:MMXMODE12 2 "nonimmediate_operand" "ym")))]
|
||||
"TARGET_MMX"
|
||||
"psubs<mmxvecsize>\t{%2, %0|%0, %2}"
|
||||
[(set_attr "type" "mmxadd")
|
||||
(set_attr "mode" "DI")])
|
||||
|
||||
(define_insn "mmx_ussub<mode>3"
|
||||
[(set (match_operand:MMXMODE12 0 "register_operand" "=y")
|
||||
(us_minus:MMXMODE12
|
||||
(match_operand:MMXMODE12 1 "register_operand" "0")
|
||||
(match_operand:MMXMODE12 2 "nonimmediate_operand" "ym")))]
|
||||
"TARGET_MMX"
|
||||
"psubus<mmxvecsize>\t{%2, %0|%0, %2}"
|
||||
[(set_attr "type" "mmxadd")
|
||||
(set_attr "mode" "DI")])
|
||||
|
||||
(define_insn "mmx_mulv4hi3"
|
||||
(define_insn "*mulv4hi3"
|
||||
[(set (match_operand:V4HI 0 "register_operand" "=y")
|
||||
(mult:V4HI (match_operand:V4HI 1 "nonimmediate_operand" "%0")
|
||||
(match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
|
||||
@ -620,28 +645,56 @@
|
||||
[(set_attr "type" "mmxmul")
|
||||
(set_attr "mode" "DI")])
|
||||
|
||||
(define_insn "mmx_smulv4hi3_highpart"
|
||||
(define_expand "mmx_smulv4hi3_highpart"
|
||||
[(set (match_operand:V4HI 0 "register_operand" "")
|
||||
(truncate:V4HI
|
||||
(lshiftrt:V4SI
|
||||
(mult:V4SI
|
||||
(sign_extend:V4SI
|
||||
(match_operand:V4HI 1 "nonimmediate_operand" ""))
|
||||
(sign_extend:V4SI
|
||||
(match_operand:V4HI 2 "nonimmediate_operand" "")))
|
||||
(const_int 16))))]
|
||||
"TARGET_MMX"
|
||||
"ix86_fixup_binary_operands_no_copy (MULT, V4HImode, operands);")
|
||||
|
||||
(define_insn "*smulv4hi3_highpart"
|
||||
[(set (match_operand:V4HI 0 "register_operand" "=y")
|
||||
(truncate:V4HI
|
||||
(lshiftrt:V4SI
|
||||
(mult:V4SI (sign_extend:V4SI
|
||||
(match_operand:V4HI 1 "nonimmediate_operand" "%0"))
|
||||
(sign_extend:V4SI
|
||||
(match_operand:V4HI 2 "nonimmediate_operand" "ym")))
|
||||
(const_int 16))))]
|
||||
(lshiftrt:V4SI
|
||||
(mult:V4SI
|
||||
(sign_extend:V4SI
|
||||
(match_operand:V4HI 1 "nonimmediate_operand" "%0"))
|
||||
(sign_extend:V4SI
|
||||
(match_operand:V4HI 2 "nonimmediate_operand" "ym")))
|
||||
(const_int 16))))]
|
||||
"TARGET_MMX && ix86_binary_operator_ok (MULT, V4HImode, operands)"
|
||||
"pmulhw\t{%2, %0|%0, %2}"
|
||||
[(set_attr "type" "mmxmul")
|
||||
(set_attr "mode" "DI")])
|
||||
|
||||
(define_insn "mmx_umulv4hi3_highpart"
|
||||
(define_expand "mmx_umulv4hi3_highpart"
|
||||
[(set (match_operand:V4HI 0 "register_operand" "")
|
||||
(truncate:V4HI
|
||||
(lshiftrt:V4SI
|
||||
(mult:V4SI
|
||||
(zero_extend:V4SI
|
||||
(match_operand:V4HI 1 "nonimmediate_operand" ""))
|
||||
(zero_extend:V4SI
|
||||
(match_operand:V4HI 2 "nonimmediate_operand" "")))
|
||||
(const_int 16))))]
|
||||
"TARGET_SSE || TARGET_3DNOW_A"
|
||||
"ix86_fixup_binary_operands_no_copy (MULT, V4HImode, operands);")
|
||||
|
||||
(define_insn "*umulv4hi3_highpart"
|
||||
[(set (match_operand:V4HI 0 "register_operand" "=y")
|
||||
(truncate:V4HI
|
||||
(lshiftrt:V4SI
|
||||
(mult:V4SI (zero_extend:V4SI
|
||||
(match_operand:V4HI 1 "nonimmediate_operand" "%0"))
|
||||
(zero_extend:V4SI
|
||||
(match_operand:V4HI 2 "nonimmediate_operand" "ym")))
|
||||
(lshiftrt:V4SI
|
||||
(mult:V4SI
|
||||
(zero_extend:V4SI
|
||||
(match_operand:V4HI 1 "nonimmediate_operand" "%0"))
|
||||
(zero_extend:V4SI
|
||||
(match_operand:V4HI 2 "nonimmediate_operand" "ym")))
|
||||
(const_int 16))))]
|
||||
"(TARGET_SSE || TARGET_3DNOW_A)
|
||||
&& ix86_binary_operator_ok (MULT, V4HImode, operands)"
|
||||
@ -687,7 +740,7 @@
|
||||
(const_int 32768) (const_int 32768)]))
|
||||
(const_int 16))))]
|
||||
"TARGET_3DNOW && ix86_binary_operator_ok (MULT, V4HImode, operands)"
|
||||
"pmulhrw\\t{%2, %0|%0, %2}"
|
||||
"pmulhrw\t{%2, %0|%0, %2}"
|
||||
[(set_attr "type" "mmxmul")
|
||||
(set_attr "mode" "DI")])
|
||||
|
||||
@ -707,24 +760,40 @@
|
||||
[(set_attr "type" "mmxmul")
|
||||
(set_attr "mode" "DI")])
|
||||
|
||||
(define_insn "mmx_<code>v4hi3"
|
||||
(define_expand "mmx_<code>v4hi3"
|
||||
[(set (match_operand:V4HI 0 "register_operand" "")
|
||||
(smaxmin:V4HI
|
||||
(match_operand:V4HI 1 "nonimmediate_operand" "")
|
||||
(match_operand:V4HI 2 "nonimmediate_operand" "")))]
|
||||
"TARGET_SSE || TARGET_3DNOW_A"
|
||||
"ix86_fixup_binary_operands_no_copy (<CODE>, V4HImode, operands);")
|
||||
|
||||
(define_insn "*<code>v4hi3"
|
||||
[(set (match_operand:V4HI 0 "register_operand" "=y")
|
||||
(smaxmin:V4HI
|
||||
(match_operand:V4HI 1 "nonimmediate_operand" "%0")
|
||||
(match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
|
||||
"(TARGET_SSE || TARGET_3DNOW_A)
|
||||
&& ix86_binary_operator_ok (SMAX, V4HImode, operands)"
|
||||
&& ix86_binary_operator_ok (<CODE>, V4HImode, operands)"
|
||||
"p<maxminiprefix>w\t{%2, %0|%0, %2}"
|
||||
[(set_attr "type" "mmxadd")
|
||||
(set_attr "mode" "DI")])
|
||||
|
||||
(define_insn "mmx_<code>v8qi3"
|
||||
(define_expand "mmx_<code>v8qi3"
|
||||
[(set (match_operand:V8QI 0 "register_operand" "")
|
||||
(umaxmin:V8QI
|
||||
(match_operand:V8QI 1 "nonimmediate_operand" "")
|
||||
(match_operand:V8QI 2 "nonimmediate_operand" "")))]
|
||||
"TARGET_SSE || TARGET_3DNOW_A"
|
||||
"ix86_fixup_binary_operands_no_copy (<CODE>, V8QImode, operands);")
|
||||
|
||||
(define_insn "*<code>v8qi3"
|
||||
[(set (match_operand:V8QI 0 "register_operand" "=y")
|
||||
(umaxmin:V8QI
|
||||
(match_operand:V8QI 1 "nonimmediate_operand" "%0")
|
||||
(match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
|
||||
"(TARGET_SSE || TARGET_3DNOW_A)
|
||||
&& ix86_binary_operator_ok (UMIN, V8QImode, operands)"
|
||||
&& ix86_binary_operator_ok (<CODE>, V8QImode, operands)"
|
||||
"p<maxminiprefix>b\t{%2, %0|%0, %2}"
|
||||
[(set_attr "type" "mmxadd")
|
||||
(set_attr "mode" "DI")])
|
||||
@ -801,7 +870,15 @@
|
||||
[(set_attr "type" "mmxadd")
|
||||
(set_attr "mode" "DI")])
|
||||
|
||||
(define_insn "mmx_<code><mode>3"
|
||||
(define_expand "mmx_<code><mode>3"
|
||||
[(set (match_operand:MMXMODEI 0 "register_operand" "")
|
||||
(plogic:MMXMODEI
|
||||
(match_operand:MMXMODEI 1 "nonimmediate_operand" "")
|
||||
(match_operand:MMXMODEI 2 "nonimmediate_operand" "")))]
|
||||
"TARGET_MMX"
|
||||
"ix86_fixup_binary_operands_no_copy (<CODE>, <MODE>mode, operands);")
|
||||
|
||||
(define_insn "*<code><mode>3"
|
||||
[(set (match_operand:MMXMODEI 0 "register_operand" "=y")
|
||||
(plogic:MMXMODEI
|
||||
(match_operand:MMXMODEI 1 "nonimmediate_operand" "%0")
|
||||
@ -1017,7 +1094,7 @@
|
||||
(match_operand:V2SI 1 "nonimmediate_operand" "ym")
|
||||
(parallel [(const_int 1) (const_int 0)])))]
|
||||
"TARGET_3DNOW_A"
|
||||
"pswapd\\t{%1, %0|%0, %1}"
|
||||
"pswapd\t{%1, %0|%0, %1}"
|
||||
[(set_attr "type" "mmxcvt")
|
||||
(set_attr "mode" "DI")])
|
||||
|
||||
@ -1221,7 +1298,7 @@
|
||||
if (TARGET_SSE || TARGET_3DNOW_A)
|
||||
return "pavgb\t{%2, %0|%0, %2}";
|
||||
else
|
||||
return "pavgusb\\t{%2, %0|%0, %2}";
|
||||
return "pavgusb\t{%2, %0|%0, %2}";
|
||||
}
|
||||
[(set_attr "type" "mmxshft")
|
||||
(set_attr "mode" "DI")])
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user