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mips.c (mips_gen_const_int_vector): Change type of last argument. 

gcc/
	* config/mips/mips.c (mips_gen_const_int_vector): Change type of last
	argument.
	* config/mips/mips-protos.h (mips_gen_const_int_vector): Likewise.

gcc/testsuite/
	* gcc.target/mips/msa-bclri.c: New test.

From-SVN: r245910
This commit is contained in:
Prachi Godbole 2017-03-06 10:08:51 +00:00 committed by Prachi Godbole
parent 8467170571
commit 334b3c4b84
5 changed files with 27 additions and 2 deletions
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6
gcc/ChangeLog
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@ -1,3 +1,9 @@
2017-03-06 Prachi Godbole <prachi.godbole@imgtec.com>
* config/mips/mips.c (mips_gen_const_int_vector): Change type of last
argument.
* config/mips/mips-protos.h (mips_gen_const_int_vector): Likewise.
2017-03-06 Richard Biener <rguenther@suse.de>
* lto-streamer.c (lto_check_version): Use %qs in diagnostics.

2
gcc/config/mips/mips-protos.h
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@ -294,7 +294,7 @@ extern bool mips_const_vector_shuffle_set_p (rtx, machine_mode);
extern bool mips_const_vector_bitimm_set_p (rtx, machine_mode);
extern bool mips_const_vector_bitimm_clr_p (rtx, machine_mode);
extern rtx mips_msa_vec_parallel_const_half (machine_mode, bool);
extern rtx mips_gen_const_int_vector (machine_mode, int);
extern rtx mips_gen_const_int_vector (machine_mode, HOST_WIDE_INT);
extern bool mips_secondary_memory_needed (enum reg_class, enum reg_class,
machine_mode);
extern bool mips_cannot_change_mode_class (machine_mode,

2
gcc/config/mips/mips.c
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@ -21630,7 +21630,7 @@ mips_expand_vi_broadcast (machine_mode vmode, rtx target, rtx elt)
/* Return a const_int vector of VAL with mode MODE. */
rtx
mips_gen_const_int_vector (machine_mode mode, int val)
mips_gen_const_int_vector (machine_mode mode, HOST_WIDE_INT val)
{
int nunits = GET_MODE_NUNITS (mode);
rtvec v = rtvec_alloc (nunits);

4
gcc/testsuite/ChangeLog
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@ -1,3 +1,7 @@
2017-03-06 Prachi Godbole <prachi.godbole@imgtec.com>
* gcc.target/mips/msa-bclri.c: New test.
2017-03-05 Paolo Carlini <paolo.carlini@oracle.com>
PR c++/70266

15
gcc/testsuite/gcc.target/mips/msa-bclri.c Normal file
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@ -0,0 +1,15 @@
/* { dg-do compile } */
/* { dg-options "-mno-mips16 -mfp64 -mhard-float -mmsa" } */
typedef long long v2i64 __attribute__ ((vector_size(16)));
/* Test MSA AND.d optimization: generate BCLRI.d instead, for immediate const
vector operand with only one bit clear. */
void
and_d_msa (v2i64 *vx, v2i64 *vy)
{
v2i64 and_vec = {0x7FFFFFFFFFFFFFFF, 0x7FFFFFFFFFFFFFFF};
*vy = (*vx) & and_vec;
}
/* { dg-final { scan-assembler "bclri.d" } } */