ia64.h (HARD_REGNO_NREGS): Return 1 for CCImode in general purpose registers.
* config/ia64/ia64.h (HARD_REGNO_NREGS): Return 1 for CCImode in general purpose registers. (HARD_REGNO_MODE_OK): Accept CCImode in general purpose registers. * config/ia64/ia64.md (*movcci): Change to named pattern. Deal with general purpose registers and memory operands. Add associated CCImode post-reload splitter. * config/ia64/div.md: Change BImode to CCImode throughout. From-SVN: r163630
This commit is contained in:
Eric Botcazou
Eric Botcazou
parent
98d4336049
commit
33620355cd
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@ -1,3 +1,13 @@
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2010-08-29 Eric Botcazou <ebotcazou@adacore.com>
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* config/ia64/ia64.h (HARD_REGNO_NREGS): Return 1 for CCImode in
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general purpose registers.
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(HARD_REGNO_MODE_OK): Accept CCImode in general purpose registers.
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* config/ia64/ia64.md (*movcci): Change to named pattern. Deal
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with general purpose registers and memory operands. Add associated
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CCImode post-reload splitter.
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* config/ia64/div.md: Change BImode to CCImode throughout.
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2010-08-28 Eric Botcazou <ebotcazou@adacore.com>
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* config/ia64/ia64.md (cstorebi4): Fix thinko.
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@ -37,7 +37,7 @@
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(define_insn "addrf3_cond"
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[(set (match_operand:RF 0 "fr_register_operand" "=f,f")
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(if_then_else:RF (ne:RF (match_operand:BI 1 "register_operand" "c,c")
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(if_then_else:RF (ne:RF (match_operand:CCI 1 "register_operand" "c,c")
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(const_int 0))
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(plus:RF
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(match_operand:RF 2 "fr_reg_or_fp01_operand" "fG,fG")
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@ -52,7 +52,7 @@
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(define_insn "subrf3_cond"
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[(set (match_operand:RF 0 "fr_register_operand" "=f,f")
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(if_then_else:RF (ne:RF (match_operand:BI 1 "register_operand" "c,c")
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(if_then_else:RF (ne:RF (match_operand:CCI 1 "register_operand" "c,c")
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(const_int 0))
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(minus:RF
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(match_operand:RF 2 "fr_reg_or_fp01_operand" "fG,fG")
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@ -67,7 +67,7 @@
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(define_insn "mulrf3_cond"
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[(set (match_operand:RF 0 "fr_register_operand" "=f,f")
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(if_then_else:RF (ne:RF (match_operand:BI 1 "register_operand" "c,c")
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(if_then_else:RF (ne:RF (match_operand:CCI 1 "register_operand" "c,c")
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(const_int 0))
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(mult:RF
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(match_operand:RF 2 "fr_reg_or_fp01_operand" "fG,fG")
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@ -84,7 +84,7 @@
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(define_insn "nmulrf3_cond"
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[(set (match_operand:RF 0 "fr_register_operand" "=f,f")
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(if_then_else:RF (ne:RF (match_operand:BI 1 "register_operand" "c,c")
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(if_then_else:RF (ne:RF (match_operand:CCI 1 "register_operand" "c,c")
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(const_int 0))
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(neg:RF (mult:RF
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(match_operand:RF 2 "fr_reg_or_fp01_operand" "fG,fG")
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@ -101,7 +101,7 @@
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(define_insn "m1addrf4_cond"
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[(set (match_operand:RF 0 "fr_register_operand" "=f,f")
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(if_then_else:RF (ne:RF (match_operand:BI 1 "register_operand" "c,c")
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(if_then_else:RF (ne:RF (match_operand:CCI 1 "register_operand" "c,c")
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(const_int 0))
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(plus:RF
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(mult:RF
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@ -118,7 +118,7 @@
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(define_insn "m1subrf4_cond"
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[(set (match_operand:RF 0 "fr_register_operand" "=f,f")
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(if_then_else:RF (ne:RF (match_operand:BI 1 "register_operand" "c,c")
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(if_then_else:RF (ne:RF (match_operand:CCI 1 "register_operand" "c,c")
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(const_int 0))
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(minus:RF
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(mult:RF
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@ -137,7 +137,7 @@
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(define_insn "m2addrf4_cond"
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[(set (match_operand:RF 0 "fr_register_operand" "=f,f")
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(if_then_else:RF (ne:RF (match_operand:BI 1 "register_operand" "c,c")
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(if_then_else:RF (ne:RF (match_operand:CCI 1 "register_operand" "c,c")
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(const_int 0))
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(plus:RF
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(match_operand:RF 2 "fr_reg_or_fp01_operand" "fG,fG")
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@ -154,7 +154,7 @@
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(define_insn "m2subrf4_cond"
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[(set (match_operand:RF 0 "fr_register_operand" "=f,f")
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(if_then_else:RF (ne:RF (match_operand:BI 1 "register_operand" "c,c")
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(if_then_else:RF (ne:RF (match_operand:CCI 1 "register_operand" "c,c")
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(const_int 0))
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(minus:RF
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(match_operand:RF 2 "fr_reg_or_fp01_operand" "fG,fG")
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@ -255,8 +255,8 @@
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(unspec:RF [(match_operand:RF 1 "fr_reg_or_fp01_operand" "fG")
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(match_operand:RF 2 "fr_reg_or_fp01_operand" "fG")]
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UNSPEC_FR_RECIP_APPROX_RES))
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(set (match_operand:BI 3 "register_operand" "=c")
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(unspec:BI [(match_dup 1) (match_dup 2)] UNSPEC_FR_RECIP_APPROX))
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(set (match_operand:CCI 3 "register_operand" "=c")
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(unspec:CCI [(match_dup 1) (match_dup 2)] UNSPEC_FR_RECIP_APPROX))
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(use (match_operand:SI 4 "const_int_operand" ""))]
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""
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"frcpa.s%4 %0, %3 = %F1, %F2"
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@ -297,7 +297,7 @@
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rtx q = gen_reg_rtx (RFmode);
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rtx r = gen_reg_rtx (RFmode);
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rtx q_res = gen_reg_rtx (RFmode);
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rtx cond = gen_reg_rtx (BImode);
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rtx cond = gen_reg_rtx (CCImode);
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rtx zero = CONST0_RTX (RFmode);
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rtx one = CONST1_RTX (RFmode);
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rtx status0 = CONST0_RTX (SImode);
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@ -345,7 +345,7 @@
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rtx q1 = gen_reg_rtx (RFmode);
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rtx r = gen_reg_rtx (RFmode);
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rtx q_res = gen_reg_rtx (RFmode);
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rtx cond = gen_reg_rtx (BImode);
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rtx cond = gen_reg_rtx (CCImode);
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rtx zero = CONST0_RTX (RFmode);
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rtx one = CONST1_RTX (RFmode);
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rtx status0 = CONST0_RTX (SImode);
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@ -414,7 +414,7 @@
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rtx y3 = gen_reg_rtx (RFmode);
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rtx q = gen_reg_rtx (RFmode);
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rtx r = gen_reg_rtx (RFmode);
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rtx cond = gen_reg_rtx (BImode);
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rtx cond = gen_reg_rtx (CCImode);
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rtx zero = CONST0_RTX (RFmode);
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rtx one = CONST1_RTX (RFmode);
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rtx status0 = CONST0_RTX (SImode);
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@ -471,7 +471,7 @@
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rtx e3 = gen_reg_rtx (RFmode);
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rtx q = gen_reg_rtx (RFmode);
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rtx r1 = gen_reg_rtx (RFmode);
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rtx cond = gen_reg_rtx (BImode);
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rtx cond = gen_reg_rtx (CCImode);
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rtx zero = CONST0_RTX (RFmode);
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rtx one = CONST1_RTX (RFmode);
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rtx status0 = CONST0_RTX (SImode);
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@ -535,7 +535,7 @@
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rtx q = gen_reg_rtx (RFmode);
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rtx r = gen_reg_rtx (RFmode);
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rtx r1 = gen_reg_rtx (RFmode);
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rtx cond = gen_reg_rtx (BImode);
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rtx cond = gen_reg_rtx (CCImode);
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rtx zero = CONST0_RTX (RFmode);
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rtx one = CONST1_RTX (RFmode);
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rtx status0 = CONST0_RTX (SImode);
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@ -702,7 +702,7 @@
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rtx e1 = gen_reg_rtx (RFmode);
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rtx q = gen_reg_rtx (RFmode);
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rtx q1 = gen_reg_rtx (RFmode);
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rtx cond = gen_reg_rtx (BImode);
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rtx cond = gen_reg_rtx (CCImode);
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rtx zero = CONST0_RTX (RFmode);
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rtx one = CONST1_RTX (RFmode);
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rtx status1 = CONST1_RTX (SImode);
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@ -844,7 +844,7 @@
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rtx q1 = gen_reg_rtx (RFmode);
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rtx q2 = gen_reg_rtx (RFmode);
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rtx r = gen_reg_rtx (RFmode);
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rtx cond = gen_reg_rtx (BImode);
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rtx cond = gen_reg_rtx (CCImode);
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rtx zero = CONST0_RTX (RFmode);
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rtx one = CONST1_RTX (RFmode);
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rtx status1 = CONST1_RTX (SImode);
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@ -888,7 +888,7 @@
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rtx e1 = gen_reg_rtx (RFmode);
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rtx q2 = gen_reg_rtx (RFmode);
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rtx r = gen_reg_rtx (RFmode);
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rtx cond = gen_reg_rtx (BImode);
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rtx cond = gen_reg_rtx (CCImode);
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rtx zero = CONST0_RTX (RFmode);
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rtx one = CONST1_RTX (RFmode);
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rtx status1 = CONST1_RTX (SImode);
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@ -920,8 +920,8 @@
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[(set (match_operand:RF 0 "fr_register_operand" "=f")
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(unspec:RF [(match_operand:RF 1 "fr_reg_or_fp01_operand" "fG")]
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UNSPEC_FR_SQRT_RECIP_APPROX_RES))
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(set (match_operand:BI 2 "register_operand" "=c")
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(unspec:BI [(match_dup 1)] UNSPEC_FR_SQRT_RECIP_APPROX))
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(set (match_operand:CCI 2 "register_operand" "=c")
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(unspec:CCI [(match_dup 1)] UNSPEC_FR_SQRT_RECIP_APPROX))
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(use (match_operand:SI 3 "const_int_operand" ""))]
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""
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"frsqrta.s%3 %0, %2 = %F1"
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@ -958,7 +958,7 @@
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rtx h = gen_reg_rtx (RFmode);
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rtx d = gen_reg_rtx (RFmode);
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rtx g2 = gen_reg_rtx (RFmode);
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rtx cond = gen_reg_rtx (BImode);
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rtx cond = gen_reg_rtx (CCImode);
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rtx zero = CONST0_RTX (RFmode);
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rtx one = CONST1_RTX (RFmode);
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rtx c1 = ia64_dconst_0_5();
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@ -1021,7 +1021,7 @@
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rtx h = gen_reg_rtx (RFmode);
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rtx h1 = gen_reg_rtx (RFmode);
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rtx d = gen_reg_rtx (RFmode);
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rtx cond = gen_reg_rtx (BImode);
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rtx cond = gen_reg_rtx (CCImode);
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rtx zero = CONST0_RTX (RFmode);
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rtx one = CONST1_RTX (RFmode);
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rtx c1 = ia64_dconst_0_5();
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@ -1104,7 +1104,7 @@
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rtx h2 = gen_reg_rtx (RFmode);
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rtx d = gen_reg_rtx (RFmode);
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rtx d1 = gen_reg_rtx (RFmode);
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rtx cond = gen_reg_rtx (BImode);
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rtx cond = gen_reg_rtx (CCImode);
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rtx zero = CONST0_RTX (RFmode);
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rtx c1 = ia64_dconst_0_5();
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rtx reg_df_c1 = gen_reg_rtx (DFmode);
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@ -1171,7 +1171,7 @@
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rtx h3 = gen_reg_rtx (RFmode);
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rtx d = gen_reg_rtx (RFmode);
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rtx d1 = gen_reg_rtx (RFmode);
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rtx cond = gen_reg_rtx (BImode);
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rtx cond = gen_reg_rtx (CCImode);
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rtx zero = CONST0_RTX (RFmode);
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rtx c1 = ia64_dconst_0_5();
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rtx reg_df_c1 = gen_reg_rtx (DFmode);
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@ -646,7 +646,7 @@ while (0)
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#define HARD_REGNO_NREGS(REGNO, MODE) \
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((REGNO) == PR_REG (0) && (MODE) == DImode ? 64 \
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: PR_REGNO_P (REGNO) && (MODE) == BImode ? 2 \
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: PR_REGNO_P (REGNO) && (MODE) == CCImode ? 1 \
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: (PR_REGNO_P (REGNO) || GR_REGNO_P (REGNO)) && (MODE) == CCImode ? 1\
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: FR_REGNO_P (REGNO) && (MODE) == XFmode ? 1 \
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: FR_REGNO_P (REGNO) && (MODE) == RFmode ? 1 \
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: FR_REGNO_P (REGNO) && (MODE) == XCmode ? 2 \
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@ -664,7 +664,7 @@ while (0)
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: PR_REGNO_P (REGNO) ? \
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(MODE) == BImode || GET_MODE_CLASS (MODE) == MODE_CC \
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: GR_REGNO_P (REGNO) ? \
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(MODE) != CCImode && (MODE) != XFmode && (MODE) != XCmode && (MODE) != RFmode \
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(MODE) != XFmode && (MODE) != XCmode && (MODE) != RFmode \
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: AR_REGNO_P (REGNO) ? (MODE) == DImode \
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: BR_REGNO_P (REGNO) ? (MODE) == DImode \
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: 0)
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@ -217,17 +217,34 @@
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;; Set of a single predicate register. This is only used to implement
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;; pr-to-pr move and complement.
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(define_insn "*movcci"
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[(set (match_operand:CCI 0 "register_operand" "=c,c,c")
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(match_operand:CCI 1 "nonmemory_operand" "O,n,c"))]
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(define_insn "movcci"
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[(set (match_operand:CCI 0 "destination_operand" "=c,c,?c,?*r, c,*r,*m,*r")
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(match_operand:CCI 1 "move_operand" " O,n, c, c,*r,*m,*r,*r"))]
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""
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"@
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cmp.ne %0, p0 = r0, r0
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cmp.eq %0, p0 = r0, r0
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(%1) cmp.eq.unc %0, p0 = r0, r0"
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[(set_attr "itanium_class" "icmp")
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(%1) cmp.eq.unc %0, p0 = r0, r0
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#
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tbit.nz %0, p0 = %1, 0
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ld1%O1 %0 = %1%P1
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st1%Q0 %0 = %1%P0
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mov %0 = %1"
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[(set_attr "itanium_class" "icmp,icmp,icmp,unknown,tbit,ld,st,ialu")
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(set_attr "predicable" "no")])
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(define_split
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[(set (match_operand:CCI 0 "register_operand" "")
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(match_operand:CCI 1 "register_operand" ""))]
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"reload_completed
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&& GET_CODE (operands[0]) == REG && GR_REGNO_P (REGNO (operands[0]))
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&& GET_CODE (operands[1]) == REG && PR_REGNO_P (REGNO (operands[1]))"
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[(set (match_dup 2) (const_int 0))
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(cond_exec (ne (match_dup 3) (const_int 0))
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(set (match_dup 2) (const_int 1)))]
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"operands[2] = gen_rtx_REG (BImode, REGNO (operands[0]));
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operands[3] = gen_rtx_REG (BImode, REGNO (operands[1]));")
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(define_insn "movbi"
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[(set (match_operand:BI 0 "destination_operand" "=c,c,?c,?*r, c,*r,*r,*m,*r")
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(match_operand:BI 1 "move_operand" " O,n, c, c,*r, n,*m,*r,*r"))]
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