re PR target/44583 (c-c++-common/torture/complex-sign-add.c fails for signed zeros)
2010-07-29 Steve Ellcey <sje@cup.hp.com> PR target/44583 * config/ia64/constraints.md (Z): New. * config/ia64/predicates.md (fr_reg_or_signed_fp01_operand): New. (xfreg_or_signed_fp01_operand): New. * config/ia64/ia64.md (addsf3): Replace fr_reg_or_fp01_operand with fr_reg_or_signed_fp01_operand and constraint G with Z. (subsf3): Ditto. (*maddsf4): Ditto. (*msubsf4): Ditto. (adddf3): Ditto. (adddf3_trunc): Ditto. (subdf3): Ditto. (*subdf3_trunc): Ditto. (*madddf4): Ditto. (*madddf4_trunc): Ditto. (*msubdf4): Ditto. (*msubdf4_trunc): Ditto. (addxf3): Replace xfreg_or_fp01_operand with xfreg_or_signed_fp01_operand and constraint G with Z. (*addxf3_truncsf): Ditto. (*addxf3_truncdf): Ditto. (subxf3): Ditto. (*subxf3_truncsf): Ditto. (*subxf3_truncdf): Ditto. (*maddxf4): Ditto. (*maddxf4_truncsf): Ditto. (*maddxf4_truncdf): Ditto. (*msubxf4): Ditto. (*msubxf4_truncsf): Ditto. (*msubxf4_truncdf): Ditto. From-SVN: r162869
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@ -1,3 +1,36 @@
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2010-08-04 Steve Ellcey <sje@cup.hp.com>
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PR target/44583
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* config/ia64/constraints.md (Z): New.
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* config/ia64/predicates.md (fr_reg_or_signed_fp01_operand): New.
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(xfreg_or_signed_fp01_operand): New.
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* config/ia64/ia64.md (addsf3): Replace fr_reg_or_fp01_operand
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with fr_reg_or_signed_fp01_operand and constraint G with Z.
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(subsf3): Ditto.
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(*maddsf4): Ditto.
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(*msubsf4): Ditto.
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(adddf3): Ditto.
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(adddf3_trunc): Ditto.
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(subdf3): Ditto.
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(*subdf3_trunc): Ditto.
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(*madddf4): Ditto.
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(*madddf4_trunc): Ditto.
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(*msubdf4): Ditto.
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(*msubdf4_trunc): Ditto.
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(addxf3): Replace xfreg_or_fp01_operand with
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xfreg_or_signed_fp01_operand and constraint G with Z.
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(*addxf3_truncsf): Ditto.
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(*addxf3_truncdf): Ditto.
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(subxf3): Ditto.
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(*subxf3_truncsf): Ditto.
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(*subxf3_truncdf): Ditto.
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(*maddxf4): Ditto.
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(*maddxf4_truncsf): Ditto.
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(*maddxf4_truncdf): Ditto.
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(*msubxf4): Ditto.
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(*msubxf4_truncsf): Ditto.
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(*msubxf4_truncdf): Ditto.
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2010-08-04 Richard Guenther <rguenther@suse.de>
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* alias.c (rtx_refs_may_alias_p): Do not resort to TBAA
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@ -95,6 +95,13 @@
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(and (match_code "const_double")
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(match_test "op == CONST0_RTX (mode) || op == CONST1_RTX (mode)")))
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(define_constraint "Z"
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"1.0 or (0.0 and !flag_signed_zeros)"
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(and (match_code "const_double")
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(ior (match_test "op == CONST1_RTX (mode)")
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(and (match_test "op == CONST0_RTX (mode)")
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(match_test "!flag_signed_zeros")))))
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(define_constraint "H"
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"0.0"
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(and (match_code "const_double")
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@ -2663,8 +2663,8 @@
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(define_insn "addsf3"
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[(set (match_operand:SF 0 "fr_register_operand" "=f")
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(plus:SF (match_operand:SF 1 "fr_reg_or_fp01_operand" "fG")
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(match_operand:SF 2 "fr_reg_or_fp01_operand" "fG")))]
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(plus:SF (match_operand:SF 1 "fr_reg_or_fp01_operand" "%fG")
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(match_operand:SF 2 "fr_reg_or_signed_fp01_operand" "fZ")))]
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""
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"fadd.s %0 = %F1, %F2"
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[(set_attr "itanium_class" "fmac")])
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@ -2672,7 +2672,7 @@
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(define_insn "subsf3"
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[(set (match_operand:SF 0 "fr_register_operand" "=f")
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(minus:SF (match_operand:SF 1 "fr_reg_or_fp01_operand" "fG")
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(match_operand:SF 2 "fr_reg_or_fp01_operand" "fG")))]
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(match_operand:SF 2 "fr_reg_or_signed_fp01_operand" "fZ")))]
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""
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"fsub.s %0 = %F1, %F2"
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[(set_attr "itanium_class" "fmac")])
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@ -2744,7 +2744,7 @@
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[(set (match_operand:SF 0 "fr_register_operand" "=f")
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(plus:SF (mult:SF (match_operand:SF 1 "fr_reg_or_fp01_operand" "fG")
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(match_operand:SF 2 "fr_reg_or_fp01_operand" "fG"))
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(match_operand:SF 3 "fr_reg_or_fp01_operand" "fG")))]
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(match_operand:SF 3 "fr_reg_or_signed_fp01_operand" "fZ")))]
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"TARGET_FUSED_MADD"
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"fma.s %0 = %F1, %F2, %F3"
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[(set_attr "itanium_class" "fmac")])
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@ -2753,7 +2753,7 @@
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[(set (match_operand:SF 0 "fr_register_operand" "=f")
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(minus:SF (mult:SF (match_operand:SF 1 "fr_reg_or_fp01_operand" "fG")
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(match_operand:SF 2 "fr_reg_or_fp01_operand" "fG"))
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(match_operand:SF 3 "fr_reg_or_fp01_operand" "fG")))]
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(match_operand:SF 3 "fr_reg_or_signed_fp01_operand" "fZ")))]
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"TARGET_FUSED_MADD"
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"fms.s %0 = %F1, %F2, %F3"
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[(set_attr "itanium_class" "fmac")])
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@ -2783,8 +2783,8 @@
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(define_insn "adddf3"
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[(set (match_operand:DF 0 "fr_register_operand" "=f")
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(plus:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG")
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(match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")))]
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(plus:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "%fG")
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(match_operand:DF 2 "fr_reg_or_signed_fp01_operand" "fZ")))]
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""
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"fadd.d %0 = %F1, %F2"
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[(set_attr "itanium_class" "fmac")])
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@ -2792,8 +2792,8 @@
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(define_insn "*adddf3_trunc"
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[(set (match_operand:SF 0 "fr_register_operand" "=f")
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(float_truncate:SF
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(plus:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG")
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(match_operand:DF 2 "fr_reg_or_fp01_operand" "fG"))))]
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(plus:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "%fG")
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(match_operand:DF 2 "fr_reg_or_signed_fp01_operand" "fZ"))))]
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""
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"fadd.s %0 = %F1, %F2"
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[(set_attr "itanium_class" "fmac")])
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@ -2801,7 +2801,7 @@
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(define_insn "subdf3"
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[(set (match_operand:DF 0 "fr_register_operand" "=f")
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(minus:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG")
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(match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")))]
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(match_operand:DF 2 "fr_reg_or_signed_fp01_operand" "fZ")))]
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""
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"fsub.d %0 = %F1, %F2"
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[(set_attr "itanium_class" "fmac")])
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@ -2810,7 +2810,7 @@
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[(set (match_operand:SF 0 "fr_register_operand" "=f")
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(float_truncate:SF
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(minus:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG")
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(match_operand:DF 2 "fr_reg_or_fp01_operand" "fG"))))]
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(match_operand:DF 2 "fr_reg_or_signed_fp01_operand" "fZ"))))]
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""
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"fsub.s %0 = %F1, %F2"
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[(set_attr "itanium_class" "fmac")])
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@ -2891,7 +2891,7 @@
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[(set (match_operand:DF 0 "fr_register_operand" "=f")
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(plus:DF (mult:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG")
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(match_operand:DF 2 "fr_reg_or_fp01_operand" "fG"))
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(match_operand:DF 3 "fr_reg_or_fp01_operand" "fG")))]
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(match_operand:DF 3 "fr_reg_or_signed_fp01_operand" "fZ")))]
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"TARGET_FUSED_MADD"
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"fma.d %0 = %F1, %F2, %F3"
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[(set_attr "itanium_class" "fmac")])
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@ -2901,7 +2901,7 @@
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(float_truncate:SF
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(plus:DF (mult:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG")
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(match_operand:DF 2 "fr_reg_or_fp01_operand" "fG"))
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(match_operand:DF 3 "fr_reg_or_fp01_operand" "fG"))))]
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(match_operand:DF 3 "fr_reg_or_signed_fp01_operand" "fZ"))))]
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"TARGET_FUSED_MADD"
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"fma.s %0 = %F1, %F2, %F3"
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[(set_attr "itanium_class" "fmac")])
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@ -2910,7 +2910,7 @@
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[(set (match_operand:DF 0 "fr_register_operand" "=f")
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(minus:DF (mult:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG")
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(match_operand:DF 2 "fr_reg_or_fp01_operand" "fG"))
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(match_operand:DF 3 "fr_reg_or_fp01_operand" "fG")))]
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(match_operand:DF 3 "fr_reg_or_signed_fp01_operand" "fZ")))]
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"TARGET_FUSED_MADD"
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"fms.d %0 = %F1, %F2, %F3"
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[(set_attr "itanium_class" "fmac")])
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@ -2920,7 +2920,7 @@
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(float_truncate:SF
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(minus:DF (mult:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG")
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(match_operand:DF 2 "fr_reg_or_fp01_operand" "fG"))
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(match_operand:DF 3 "fr_reg_or_fp01_operand" "fG"))))]
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(match_operand:DF 3 "fr_reg_or_signed_fp01_operand" "fZ"))))]
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"TARGET_FUSED_MADD"
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"fms.s %0 = %F1, %F2, %F3"
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[(set_attr "itanium_class" "fmac")])
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@ -2969,8 +2969,8 @@
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(define_insn "addxf3"
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[(set (match_operand:XF 0 "fr_register_operand" "=f")
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(plus:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")
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(match_operand:XF 2 "xfreg_or_fp01_operand" "fG")))]
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(plus:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "%fG")
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(match_operand:XF 2 "xfreg_or_signed_fp01_operand" "fZ")))]
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""
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"fadd %0 = %F1, %F2"
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[(set_attr "itanium_class" "fmac")])
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@ -2978,8 +2978,8 @@
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(define_insn "*addxf3_truncsf"
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[(set (match_operand:SF 0 "fr_register_operand" "=f")
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(float_truncate:SF
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(plus:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")
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(match_operand:XF 2 "xfreg_or_fp01_operand" "fG"))))]
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(plus:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "%fG")
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(match_operand:XF 2 "xfreg_or_signed_fp01_operand" "fZ"))))]
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""
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"fadd.s %0 = %F1, %F2"
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[(set_attr "itanium_class" "fmac")])
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@ -2987,8 +2987,8 @@
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(define_insn "*addxf3_truncdf"
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[(set (match_operand:DF 0 "fr_register_operand" "=f")
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(float_truncate:DF
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(plus:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")
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(match_operand:XF 2 "xfreg_or_fp01_operand" "fG"))))]
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(plus:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "%fG")
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(match_operand:XF 2 "xfreg_or_signed_fp01_operand" "fZ"))))]
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""
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"fadd.d %0 = %F1, %F2"
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[(set_attr "itanium_class" "fmac")])
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@ -2996,7 +2996,7 @@
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(define_insn "subxf3"
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[(set (match_operand:XF 0 "fr_register_operand" "=f")
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(minus:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")
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(match_operand:XF 2 "xfreg_or_fp01_operand" "fG")))]
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(match_operand:XF 2 "xfreg_or_signed_fp01_operand" "fZ")))]
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""
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"fsub %0 = %F1, %F2"
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[(set_attr "itanium_class" "fmac")])
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@ -3005,7 +3005,7 @@
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[(set (match_operand:SF 0 "fr_register_operand" "=f")
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(float_truncate:SF
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(minus:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")
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(match_operand:XF 2 "xfreg_or_fp01_operand" "fG"))))]
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(match_operand:XF 2 "xfreg_or_signed_fp01_operand" "fZ"))))]
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""
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"fsub.s %0 = %F1, %F2"
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[(set_attr "itanium_class" "fmac")])
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@ -3014,7 +3014,7 @@
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[(set (match_operand:DF 0 "fr_register_operand" "=f")
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(float_truncate:DF
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(minus:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")
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(match_operand:XF 2 "xfreg_or_fp01_operand" "fG"))))]
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(match_operand:XF 2 "xfreg_or_signed_fp01_operand" "fZ"))))]
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""
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"fsub.d %0 = %F1, %F2"
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[(set_attr "itanium_class" "fmac")])
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@ -3104,7 +3104,7 @@
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[(set (match_operand:XF 0 "fr_register_operand" "=f")
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(plus:XF (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")
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(match_operand:XF 2 "xfreg_or_fp01_operand" "fG"))
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(match_operand:XF 3 "xfreg_or_fp01_operand" "fG")))]
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(match_operand:XF 3 "xfreg_or_signed_fp01_operand" "fZ")))]
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"TARGET_FUSED_MADD"
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"fma %0 = %F1, %F2, %F3"
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[(set_attr "itanium_class" "fmac")])
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@ -3114,7 +3114,7 @@
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(float_truncate:SF
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(plus:XF (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")
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(match_operand:XF 2 "xfreg_or_fp01_operand" "fG"))
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(match_operand:XF 3 "xfreg_or_fp01_operand" "fG"))))]
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(match_operand:XF 3 "xfreg_or_signed_fp01_operand" "fZ"))))]
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"TARGET_FUSED_MADD"
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"fma.s %0 = %F1, %F2, %F3"
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[(set_attr "itanium_class" "fmac")])
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@ -3124,7 +3124,7 @@
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(float_truncate:DF
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(plus:XF (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")
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(match_operand:XF 2 "xfreg_or_fp01_operand" "fG"))
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(match_operand:XF 3 "xfreg_or_fp01_operand" "fG"))))]
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(match_operand:XF 3 "xfreg_or_signed_fp01_operand" "fZ"))))]
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"TARGET_FUSED_MADD"
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"fma.d %0 = %F1, %F2, %F3"
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[(set_attr "itanium_class" "fmac")])
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@ -3133,7 +3133,7 @@
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[(set (match_operand:XF 0 "fr_register_operand" "=f")
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(minus:XF (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")
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(match_operand:XF 2 "xfreg_or_fp01_operand" "fG"))
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(match_operand:XF 3 "xfreg_or_fp01_operand" "fG")))]
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(match_operand:XF 3 "xfreg_or_signed_fp01_operand" "fZ")))]
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"TARGET_FUSED_MADD"
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"fms %0 = %F1, %F2, %F3"
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[(set_attr "itanium_class" "fmac")])
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@ -3143,7 +3143,7 @@
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(float_truncate:SF
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(minus:XF (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")
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(match_operand:XF 2 "xfreg_or_fp01_operand" "fG"))
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(match_operand:XF 3 "xfreg_or_fp01_operand" "fG"))))]
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(match_operand:XF 3 "xfreg_or_signed_fp01_operand" "fZ"))))]
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"TARGET_FUSED_MADD"
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"fms.s %0 = %F1, %F2, %F3"
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[(set_attr "itanium_class" "fmac")])
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@ -3153,7 +3153,7 @@
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(float_truncate:DF
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(minus:XF (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")
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(match_operand:XF 2 "xfreg_or_fp01_operand" "fG"))
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(match_operand:XF 3 "xfreg_or_fp01_operand" "fG"))))]
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(match_operand:XF 3 "xfreg_or_signed_fp01_operand" "fZ"))))]
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"TARGET_FUSED_MADD"
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"fms.d %0 = %F1, %F2, %F3"
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[(set_attr "itanium_class" "fmac")])
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@ -542,6 +542,19 @@
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(and (match_operand 0 "fr_reg_or_fp01_operand")
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(not (match_code "subreg"))))
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;; Like fr_reg_or_fp01_operand, but don't allow 0 if flag_signed_zero is set.
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;; Using f0 as the second arg to fadd or fsub, or as the third arg to fma or
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;; fms can cause a zero result to have the wrong sign.
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(define_predicate "fr_reg_or_signed_fp01_operand"
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(ior (match_operand 0 "fr_register_operand")
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(and (match_code "const_double")
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(match_test "satisfies_constraint_Z (op)"))))
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||||
;; Like fr_reg_or_signed_fp01_operand, but don't allow any SUBREGs.
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(define_predicate "xfreg_or_signed_fp01_operand"
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||||
(and (match_operand 0 "fr_reg_or_signed_fp01_operand")
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(not (match_code "subreg"))))
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;; True if OP is a constant zero, or a register.
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||||
(define_predicate "fr_reg_or_0_operand"
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||||
(ior (match_operand 0 "fr_register_operand")
|
||||
|
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Loading…
Reference in New Issue