rs6000: Remove spe_acc and spefscr
We can also remove the two other SPE registers. * config/rs6000/darwin.h (REGISTER_NAMES): Delete the SPE_ACC and SPEFSCR registers. * config/rs6000/rs6000.c (rs6000_reg_names, alt_reg_names): Ditto. (enum rs6000_reg_type): Delete SPE_ACC_TYPE and SPEFSCR_REG_TYPE. (rs6000_debug_reg_global): Adjust. (rs6000_init_hard_regno_mode_ok): Adjust. (rs6000_dbx_register_number): Adjust. * config/rs6000/rs6000.h (FIRST_PSEUDO_REGISTER): Change to 115. (FIXED_REGISTERS, CALL_USED_REGISTERS, CALL_REALLY_USED_REGISTERS): Remove SPE_ACC and SPEFSCR. (REG_ALLOC_ORDER): Ditto. (FRAME_POINTER_REGNUM): Change to 111. (enum reg_class): Remove the SPE_ACC and SPEFSCR registers. (REG_CLASS_NAMES): Ditto. (REG_CLASS_CONTENTS): Delete the SPE_ACC and SPEFSCR registers. (REGISTER_NAMES): Ditto. (ADDITIONAL_REG_NAMES): Ditto. (rs6000_reg_names): Ditto. * config/rs6000/rs6000.md: Renumber some register number define_constants. From-SVN: r248986
This commit is contained in:
Segher Boessenkool
Segher Boessenkool
parent
3e2bca2e2c
commit
346081bd18
@ -1,3 +1,26 @@
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2017-06-07 Segher Boessenkool <segher@kernel.crashing.org>
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* config/rs6000/darwin.h (REGISTER_NAMES): Delete the SPE_ACC and
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SPEFSCR registers.
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* config/rs6000/rs6000.c (rs6000_reg_names, alt_reg_names): Ditto.
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(enum rs6000_reg_type): Delete SPE_ACC_TYPE and SPEFSCR_REG_TYPE.
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(rs6000_debug_reg_global): Adjust.
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(rs6000_init_hard_regno_mode_ok): Adjust.
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(rs6000_dbx_register_number): Adjust.
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* config/rs6000/rs6000.h (FIRST_PSEUDO_REGISTER): Change to 115.
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(FIXED_REGISTERS, CALL_USED_REGISTERS, CALL_REALLY_USED_REGISTERS):
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Remove SPE_ACC and SPEFSCR.
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(REG_ALLOC_ORDER): Ditto.
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(FRAME_POINTER_REGNUM): Change to 111.
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(enum reg_class): Remove the SPE_ACC and SPEFSCR registers.
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(REG_CLASS_NAMES): Ditto.
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(REG_CLASS_CONTENTS): Delete the SPE_ACC and SPEFSCR registers.
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(REGISTER_NAMES): Ditto.
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(ADDITIONAL_REG_NAMES): Ditto.
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(rs6000_reg_names): Ditto.
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* config/rs6000/rs6000.md: Renumber some register number
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define_constants.
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2017-06-07 Segher Boessenkool <segher@kernel.crashing.org>
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* config/rs6000/darwin.h (REGISTER_NAMES): Delete the SPE high
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@ -192,7 +192,6 @@ extern int darwin_emit_branch_islands;
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"v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", \
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"v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", \
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"vrsave", "vscr", \
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"spe_acc", "spefscr", \
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"sfp", \
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"tfhar", "tfiar", "texasr" \
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}
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@ -437,8 +437,6 @@ enum rs6000_reg_type {
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FPR_REG_TYPE,
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SPR_REG_TYPE,
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CR_REG_TYPE,
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SPE_ACC_TYPE,
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SPEFSCR_REG_TYPE
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};
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/* Map register class to register type. */
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@ -1502,8 +1500,6 @@ char rs6000_reg_names[][8] =
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"16", "17", "18", "19", "20", "21", "22", "23",
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"24", "25", "26", "27", "28", "29", "30", "31",
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"vrsave", "vscr",
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/* SPE registers. */
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"spe_acc", "spefscr",
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/* Soft frame pointer. */
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"sfp",
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/* HTM SPR registers. */
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@ -1530,8 +1526,6 @@ static const char alt_reg_names[][8] =
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"%v16", "%v17", "%v18", "%v19", "%v20", "%v21", "%v22", "%v23",
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"%v24", "%v25", "%v26", "%v27", "%v28", "%v29", "%v30", "%v31",
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"vrsave", "vscr",
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/* SPE registers. */
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"spe_acc", "spefscr",
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/* Soft frame pointer. */
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"sfp",
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/* HTM SPR registers. */
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@ -2514,8 +2508,6 @@ rs6000_debug_reg_global (void)
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rs6000_debug_reg_print (CA_REGNO, CA_REGNO, "ca");
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rs6000_debug_reg_print (VRSAVE_REGNO, VRSAVE_REGNO, "vrsave");
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rs6000_debug_reg_print (VSCR_REGNO, VSCR_REGNO, "vscr");
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rs6000_debug_reg_print (SPE_ACC_REGNO, SPE_ACC_REGNO, "spe_a");
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rs6000_debug_reg_print (SPEFSCR_REGNO, SPEFSCR_REGNO, "spe_f");
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fputs ("\nVirtual/stack/frame registers:\n", stderr);
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for (v = 0; v < ARRAY_SIZE (virtual_regs); v++)
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@ -3024,8 +3016,6 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p)
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rs6000_regno_regclass[CA_REGNO] = NO_REGS;
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rs6000_regno_regclass[VRSAVE_REGNO] = VRSAVE_REGS;
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rs6000_regno_regclass[VSCR_REGNO] = VRSAVE_REGS;
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rs6000_regno_regclass[SPE_ACC_REGNO] = SPE_ACC_REGS;
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rs6000_regno_regclass[SPEFSCR_REGNO] = SPEFSCR_REGS;
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rs6000_regno_regclass[TFHAR_REGNO] = SPR_REGS;
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rs6000_regno_regclass[TFIAR_REGNO] = SPR_REGS;
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rs6000_regno_regclass[TEXASR_REGNO] = SPR_REGS;
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@ -3048,8 +3038,6 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p)
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reg_class_to_reg_type[(int)LINK_OR_CTR_REGS] = SPR_REG_TYPE;
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reg_class_to_reg_type[(int)CR_REGS] = CR_REG_TYPE;
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reg_class_to_reg_type[(int)CR0_REGS] = CR_REG_TYPE;
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reg_class_to_reg_type[(int)SPE_ACC_REGS] = SPE_ACC_TYPE;
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reg_class_to_reg_type[(int)SPEFSCR_REGS] = SPEFSCR_REG_TYPE;
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if (TARGET_VSX)
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{
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@ -37481,10 +37469,6 @@ rs6000_dbx_register_number (unsigned int regno, unsigned int format)
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return 356;
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if (regno == VSCR_REGNO)
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return 67;
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if (regno == SPE_ACC_REGNO)
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return 99;
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if (regno == SPEFSCR_REGNO)
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return 612;
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#endif
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return regno;
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}
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@ -1017,7 +1017,7 @@ enum data_align { align_abi, align_opt, align_both };
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The 3 HTM registers aren't also included in DWARF_FRAME_REGISTERS. */
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#define FIRST_PSEUDO_REGISTER 117
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#define FIRST_PSEUDO_REGISTER 115
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/* This must be included for pre gcc 3.0 glibc compatibility. */
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#define PRE_GCC3_DWARF_FRAME_REGISTERS 77
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@ -1056,7 +1056,7 @@ enum data_align { align_abi, align_opt, align_both };
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
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1, 1 \
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, 1, 1, 1, 1, 1, 1 \
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, 1, 1, 1, 1 \
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}
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/* 1 for registers not available across function calls.
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@ -1076,7 +1076,7 @@ enum data_align { align_abi, align_opt, align_both };
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
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1, 1 \
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, 1, 1, 1, 1, 1, 1 \
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, 1, 1, 1, 1 \
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}
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/* Like `CALL_USED_REGISTERS' except this macro doesn't require that
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@ -1095,7 +1095,7 @@ enum data_align { align_abi, align_opt, align_both };
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
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0, 0 \
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, 0, 0, 0, 0, 0, 0 \
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, 0, 0, 0, 0 \
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}
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#define TOTAL_ALTIVEC_REGS (LAST_ALTIVEC_REGNO - FIRST_ALTIVEC_REGNO + 1)
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@ -1133,7 +1133,6 @@ enum data_align { align_abi, align_opt, align_both };
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v19 - v14 (not saved or used for anything)
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v31 - v20 (saved; order given to save least number)
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vrsave, vscr (fixed)
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spe_acc, spefscr (fixed)
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sfp (fixed)
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tfhar (fixed)
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tfiar (fixed)
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@ -1179,7 +1178,7 @@ enum data_align { align_abi, align_opt, align_both };
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96, 95, 94, 93, 92, 91, \
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108, 107, 106, 105, 104, 103, 102, 101, 100, 99, 98, 97, \
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109, 110, \
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111, 112, 113, 114, 115, 116 \
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111, 112, 113, 114 \
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}
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/* True if register is floating-point. */
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@ -1351,7 +1350,7 @@ enum data_align { align_abi, align_opt, align_both };
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#define HARD_FRAME_POINTER_REGNUM 31
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/* Base register for access to local variables of the function. */
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#define FRAME_POINTER_REGNUM 113
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#define FRAME_POINTER_REGNUM 111
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/* Base register for access to arguments of the function. */
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#define ARG_POINTER_REGNUM 67
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@ -1404,8 +1403,6 @@ enum reg_class
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VSX_REGS,
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VRSAVE_REGS,
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VSCR_REGS,
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SPE_ACC_REGS,
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SPEFSCR_REGS,
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SPR_REGS,
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NON_SPECIAL_REGS,
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LINK_REGS,
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@ -1435,8 +1432,6 @@ enum reg_class
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"VSX_REGS", \
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"VRSAVE_REGS", \
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"VSCR_REGS", \
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"SPE_ACC_REGS", \
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"SPEFSCR_REGS", \
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"SPR_REGS", \
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"NON_SPECIAL_REGS", \
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"LINK_REGS", \
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@ -1460,9 +1455,9 @@ enum reg_class
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/* NO_REGS. */ \
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{ 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \
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/* BASE_REGS. */ \
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{ 0xfffffffe, 0x00000000, 0x00000008, 0x00020000 }, \
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{ 0xfffffffe, 0x00000000, 0x00000008, 0x00008000 }, \
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/* GENERAL_REGS. */ \
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{ 0xffffffff, 0x00000000, 0x00000008, 0x00020000 }, \
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{ 0xffffffff, 0x00000000, 0x00000008, 0x00008000 }, \
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/* FLOAT_REGS. */ \
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{ 0x00000000, 0xffffffff, 0x00000000, 0x00000000 }, \
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/* ALTIVEC_REGS. */ \
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@ -1473,14 +1468,10 @@ enum reg_class
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{ 0x00000000, 0x00000000, 0x00000000, 0x00002000 }, \
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/* VSCR_REGS. */ \
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{ 0x00000000, 0x00000000, 0x00000000, 0x00004000 }, \
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/* SPE_ACC_REGS. */ \
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{ 0x00000000, 0x00000000, 0x00000000, 0x00008000 }, \
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/* SPEFSCR_REGS. */ \
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{ 0x00000000, 0x00000000, 0x00000000, 0x00010000 }, \
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/* SPR_REGS. */ \
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{ 0x00000000, 0x00000000, 0x00000000, 0x00040000 }, \
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{ 0x00000000, 0x00000000, 0x00000000, 0x00010000 }, \
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/* NON_SPECIAL_REGS. */ \
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{ 0xffffffff, 0xffffffff, 0x00000008, 0x00020000 }, \
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{ 0xffffffff, 0xffffffff, 0x00000008, 0x00008000 }, \
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/* LINK_REGS. */ \
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{ 0x00000000, 0x00000000, 0x00000002, 0x00000000 }, \
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/* CTR_REGS. */ \
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@ -1490,17 +1481,17 @@ enum reg_class
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/* SPECIAL_REGS. */ \
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{ 0x00000000, 0x00000000, 0x00000006, 0x00002000 }, \
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/* SPEC_OR_GEN_REGS. */ \
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{ 0xffffffff, 0x00000000, 0x0000000e, 0x00022000 }, \
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{ 0xffffffff, 0x00000000, 0x0000000e, 0x0000a000 }, \
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/* CR0_REGS. */ \
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{ 0x00000000, 0x00000000, 0x00000010, 0x00000000 }, \
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/* CR_REGS. */ \
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{ 0x00000000, 0x00000000, 0x00000ff0, 0x00000000 }, \
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/* NON_FLOAT_REGS. */ \
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{ 0xffffffff, 0x00000000, 0x00000ffe, 0x00020000 }, \
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{ 0xffffffff, 0x00000000, 0x00000ffe, 0x00008000 }, \
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/* CA_REGS. */ \
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{ 0x00000000, 0x00000000, 0x00001000, 0x00000000 }, \
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/* ALL_REGS. */ \
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{ 0xffffffff, 0xffffffff, 0xfffffffe, 0x0007ffff } \
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{ 0xffffffff, 0xffffffff, 0xfffffffe, 0x0001ffff } \
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}
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/* The same information, inverted:
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@ -2429,12 +2420,10 @@ extern char rs6000_reg_names[][8]; /* register names (0 vs. %r0). */
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&rs6000_reg_names[108][0], /* v31 */ \
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&rs6000_reg_names[109][0], /* vrsave */ \
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&rs6000_reg_names[110][0], /* vscr */ \
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&rs6000_reg_names[111][0], /* spe_acc */ \
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&rs6000_reg_names[112][0], /* spefscr */ \
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&rs6000_reg_names[113][0], /* sfp */ \
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&rs6000_reg_names[114][0], /* tfhar */ \
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&rs6000_reg_names[115][0], /* tfiar */ \
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&rs6000_reg_names[116][0], /* texasr */ \
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&rs6000_reg_names[111][0], /* sfp */ \
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&rs6000_reg_names[112][0], /* tfhar */ \
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&rs6000_reg_names[113][0], /* tfiar */ \
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&rs6000_reg_names[114][0], /* texasr */ \
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}
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/* Table of additional register names to use in user input. */
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@ -2465,7 +2454,6 @@ extern char rs6000_reg_names[][8]; /* register names (0 vs. %r0). */
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{"v24", 101},{"v25", 102},{"v26", 103},{"v27", 104}, \
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{"v28", 105},{"v29", 106},{"v30", 107},{"v31", 108}, \
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{"vrsave", 109}, {"vscr", 110}, \
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{"spe_acc", 111}, {"spefscr", 112}, \
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/* no additional names for: lr, ctr, ap */ \
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{"cr0", 68}, {"cr1", 69}, {"cr2", 70}, {"cr3", 71}, \
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{"cr4", 72}, {"cr5", 73}, {"cr6", 74}, {"cr7", 75}, \
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@ -2490,7 +2478,7 @@ extern char rs6000_reg_names[][8]; /* register names (0 vs. %r0). */
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{"vs56", 101},{"vs57", 102},{"vs58", 103},{"vs59", 104}, \
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{"vs60", 105},{"vs61", 106},{"vs62", 107},{"vs63", 108}, \
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/* Transactional Memory Facility (HTM) Registers. */ \
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{"tfhar", 114}, {"tfiar", 115}, {"texasr", 116}, \
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{"tfhar", 112}, {"tfiar", 113}, {"texasr", 114}, \
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}
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/* This is how to output an element of a case-vector that is relative. */
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@ -50,12 +50,10 @@
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(LAST_ALTIVEC_REGNO 108)
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(VRSAVE_REGNO 109)
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(VSCR_REGNO 110)
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(SPE_ACC_REGNO 111)
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(SPEFSCR_REGNO 112)
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(FRAME_POINTER_REGNUM 113)
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(TFHAR_REGNO 114)
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(TFIAR_REGNO 115)
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(TEXASR_REGNO 116)
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(FRAME_POINTER_REGNUM 111)
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(TFHAR_REGNO 112)
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(TFIAR_REGNO 113)
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(TEXASR_REGNO 114)
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])
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;;
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