sse.md (vec_setv4sf): Removed.
2008-05-21 H.J. Lu <hongjiu.lu@intel.com> * config/i386/sse.md (vec_setv4sf): Removed. (vec_setv2df): Likewise. (vec_setv2di): Likewise. (vec_setv4si): Likewise. (vec_setv8hi): Likewise. (vec_setv16qi): Likewise. (vec_set<mode>): New. From-SVN: r135726
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@ -1,3 +1,13 @@
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2008-05-21 H.J. Lu <hongjiu.lu@intel.com>
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* config/i386/sse.md (vec_setv4sf): Removed.
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(vec_setv2df): Likewise.
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(vec_setv2di): Likewise.
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(vec_setv4si): Likewise.
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(vec_setv8hi): Likewise.
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(vec_setv16qi): Likewise.
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(vec_set<mode>): New.
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2008-05-21 H.J. Lu <hongjiu.lu@intel.com>
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2008-05-21 H.J. Lu <hongjiu.lu@intel.com>
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* config/i386/i386.c (ix86_expand_vector_init_general): Remove
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* config/i386/i386.c (ix86_expand_vector_init_general): Remove
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@ -2372,9 +2372,9 @@
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DONE;
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DONE;
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})
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})
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(define_expand "vec_setv4sf"
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(define_expand "vec_set<mode>"
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[(match_operand:V4SF 0 "register_operand" "")
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[(match_operand:SSEMODE 0 "register_operand" "")
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(match_operand:SF 1 "register_operand" "")
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(match_operand:<ssescalarmode> 1 "register_operand" "")
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(match_operand 2 "const_int_operand" "")]
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(match_operand 2 "const_int_operand" "")]
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"TARGET_SSE"
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"TARGET_SSE"
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{
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{
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@ -2786,17 +2786,6 @@
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[(set_attr "type" "sselog,ssemov,ssemov,ssemov,ssemov")
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[(set_attr "type" "sselog,ssemov,ssemov,ssemov,ssemov")
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(set_attr "mode" "V2DF,V1DF,DF,V4SF,V2SF")])
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(set_attr "mode" "V2DF,V1DF,DF,V4SF,V2SF")])
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(define_expand "vec_setv2df"
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[(match_operand:V2DF 0 "register_operand" "")
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(match_operand:DF 1 "register_operand" "")
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(match_operand 2 "const_int_operand" "")]
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"TARGET_SSE"
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{
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ix86_expand_vector_set (false, operands[0], operands[1],
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INTVAL (operands[2]));
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DONE;
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})
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(define_expand "vec_extractv2df"
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(define_expand "vec_extractv2df"
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[(match_operand:DF 0 "register_operand" "")
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[(match_operand:DF 0 "register_operand" "")
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(match_operand:V2DF 1 "register_operand" "")
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(match_operand:V2DF 1 "register_operand" "")
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@ -4921,17 +4910,6 @@
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[(set_attr "type" "ssemov,ssemov,ssemov,sselog,ssemov,ssemov,ssemov")
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[(set_attr "type" "ssemov,ssemov,ssemov,sselog,ssemov,ssemov,ssemov")
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(set_attr "mode" "TI,TI,TI,TI,V4SF,V2SF,V2SF")])
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(set_attr "mode" "TI,TI,TI,TI,V4SF,V2SF,V2SF")])
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(define_expand "vec_setv2di"
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[(match_operand:V2DI 0 "register_operand" "")
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(match_operand:DI 1 "register_operand" "")
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(match_operand 2 "const_int_operand" "")]
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"TARGET_SSE"
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{
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ix86_expand_vector_set (false, operands[0], operands[1],
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INTVAL (operands[2]));
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DONE;
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})
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(define_expand "vec_extractv2di"
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(define_expand "vec_extractv2di"
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[(match_operand:DI 0 "register_operand" "")
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[(match_operand:DI 0 "register_operand" "")
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(match_operand:V2DI 1 "register_operand" "")
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(match_operand:V2DI 1 "register_operand" "")
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@ -4943,17 +4921,6 @@
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DONE;
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DONE;
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})
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})
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(define_expand "vec_setv4si"
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[(match_operand:V4SI 0 "register_operand" "")
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(match_operand:SI 1 "register_operand" "")
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(match_operand 2 "const_int_operand" "")]
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"TARGET_SSE"
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{
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ix86_expand_vector_set (false, operands[0], operands[1],
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INTVAL (operands[2]));
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DONE;
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})
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(define_expand "vec_extractv4si"
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(define_expand "vec_extractv4si"
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[(match_operand:SI 0 "register_operand" "")
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[(match_operand:SI 0 "register_operand" "")
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(match_operand:V4SI 1 "register_operand" "")
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(match_operand:V4SI 1 "register_operand" "")
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@ -4965,17 +4932,6 @@
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DONE;
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DONE;
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})
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})
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(define_expand "vec_setv8hi"
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[(match_operand:V8HI 0 "register_operand" "")
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(match_operand:HI 1 "register_operand" "")
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(match_operand 2 "const_int_operand" "")]
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"TARGET_SSE"
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{
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ix86_expand_vector_set (false, operands[0], operands[1],
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INTVAL (operands[2]));
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DONE;
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})
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(define_expand "vec_extractv8hi"
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(define_expand "vec_extractv8hi"
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[(match_operand:HI 0 "register_operand" "")
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[(match_operand:HI 0 "register_operand" "")
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(match_operand:V8HI 1 "register_operand" "")
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(match_operand:V8HI 1 "register_operand" "")
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@ -4987,17 +4943,6 @@
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DONE;
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DONE;
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})
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})
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(define_expand "vec_setv16qi"
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[(match_operand:V16QI 0 "register_operand" "")
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(match_operand:QI 1 "register_operand" "")
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(match_operand 2 "const_int_operand" "")]
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"TARGET_SSE"
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{
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ix86_expand_vector_set (false, operands[0], operands[1],
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INTVAL (operands[2]));
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DONE;
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})
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(define_expand "vec_extractv16qi"
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(define_expand "vec_extractv16qi"
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[(match_operand:QI 0 "register_operand" "")
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[(match_operand:QI 0 "register_operand" "")
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(match_operand:V16QI 1 "register_operand" "")
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(match_operand:V16QI 1 "register_operand" "")
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