Inlined floatunssidf2 and floatunsdidf2
From-SVN: r130225
This commit is contained in:
Sa Liu
parent
99552e406c
commit
3538c42dd7
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@ -663,7 +663,6 @@
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(float:DF (match_operand:SI 1 "register_operand" "")))]
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""
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{
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rtx value, insns;
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rtx c0 = gen_reg_rtx (SImode);
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rtx c1 = gen_reg_rtx (DFmode);
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rtx r0 = gen_reg_rtx (SImode);
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@ -671,30 +670,79 @@
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emit_move_insn (c0, GEN_INT (-0x80000000ll));
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emit_move_insn (c1, spu_float_const ("2147483648", DFmode));
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emit_insn (gen_xorsi3 (r0, operands[1], c0));
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start_sequence ();
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value =
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emit_library_call_value (convert_optab_libfunc (ufloat_optab,
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DFmode, SImode),
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NULL_RTX, LCT_NORMAL, DFmode, 1, r0, SImode);
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insns = get_insns ();
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end_sequence ();
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emit_libcall_block (insns, r1, value,
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gen_rtx_UNSIGNED_FLOAT (DFmode, r0));
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emit_insn (gen_floatunssidf2 (r1, r0));
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emit_insn (gen_subdf3 (operands[0], r1, c1));
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DONE;
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})
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(define_expand "floatunssidf2"
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[(set (match_operand:DF 0 "register_operand" "=r")
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(unsigned_float:DF (match_operand:SI 1 "register_operand" "r")))]
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""
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"{
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rtx value, insns;
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rtx c0 = spu_const_from_ints (V16QImode, 0x02031011, 0x12138080,
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0x06071415, 0x16178080);
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rtx r0 = gen_reg_rtx (V16QImode);
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if (optimize_size)
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{
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start_sequence ();
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value =
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emit_library_call_value (convert_optab_libfunc (ufloat_optab,
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DFmode, SImode),
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NULL_RTX, LCT_NORMAL, DFmode, 1, operands[1], SImode);
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insns = get_insns ();
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end_sequence ();
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emit_libcall_block (insns, operands[0], value,
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gen_rtx_UNSIGNED_FLOAT (DFmode, operands[1]));
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}
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else
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{
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emit_move_insn (r0, c0);
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emit_insn (gen_floatunssidf2_internal (operands[0], operands[1], r0));
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}
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DONE;
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}")
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(define_insn_and_split "floatunssidf2_internal"
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[(set (match_operand:DF 0 "register_operand" "=r")
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(unsigned_float:DF (match_operand:SI 1 "register_operand" "r")))
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(use (match_operand:V16QI 2 "register_operand" "r"))
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(clobber (match_scratch:V4SI 3 "=&r"))
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(clobber (match_scratch:V4SI 4 "=&r"))
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(clobber (match_scratch:V4SI 5 "=&r"))
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(clobber (match_scratch:V4SI 6 "=&r"))]
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""
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"clz\t%3,%1\;il\t%6,1023+31\;shl\t%4,%1,%3\;ceqi\t%5,%3,32\;sf\t%6,%3,%6\;a\t%4,%4,%4\;andc\t%6,%6,%5\;shufb\t%6,%6,%4,%2\;shlqbii\t%0,%6,4"
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"reload_completed"
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[(set (match_dup:DF 0)
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(unsigned_float:DF (match_dup:SI 1)))]
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"{
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rtx *ops = operands;
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rtx op1_v4si = gen_rtx_REG(V4SImode, REGNO(ops[1]));
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rtx op0_ti = gen_rtx_REG (TImode, REGNO (ops[0]));
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rtx op2_ti = gen_rtx_REG (TImode, REGNO (ops[2]));
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rtx op6_ti = gen_rtx_REG (TImode, REGNO (ops[6]));
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emit_insn (gen_clzv4si2 (ops[3],op1_v4si));
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emit_move_insn (ops[6], spu_const (V4SImode, 1023+31));
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emit_insn (gen_ashlv4si3 (ops[4],op1_v4si,ops[3]));
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emit_insn (gen_ceq_v4si (ops[5],ops[3],spu_const (V4SImode, 32)));
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emit_insn (gen_subv4si3 (ops[6],ops[6],ops[3]));
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emit_insn (gen_addv4si3 (ops[4],ops[4],ops[4]));
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emit_insn (gen_andc_v4si (ops[6],ops[6],ops[5]));
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emit_insn (gen_shufb (ops[6],ops[6],ops[4],op2_ti));
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emit_insn (gen_shlqbi_ti (op0_ti,op6_ti,GEN_INT(4)));
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DONE;
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}"
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[(set_attr "length" "32")])
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(define_expand "floatdidf2"
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[(set (match_operand:DF 0 "register_operand" "")
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(float:DF (match_operand:DI 1 "register_operand" "")))]
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""
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{
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rtx value, insns;
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rtx c0 = gen_reg_rtx (DImode);
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rtx r0 = gen_reg_rtx (DImode);
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rtx r1 = gen_reg_rtx (DFmode);
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@ -712,22 +760,81 @@
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emit_insn (gen_selb (r0, neg, operands[1], mask));
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emit_insn (gen_andc_di (setneg, c0, mask));
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start_sequence ();
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value =
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emit_library_call_value (convert_optab_libfunc (ufloat_optab,
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DFmode, DImode),
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NULL_RTX, LCT_NORMAL, DFmode, 1, r0, DImode);
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insns = get_insns ();
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end_sequence ();
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emit_libcall_block (insns, r1, value,
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gen_rtx_UNSIGNED_FLOAT (DFmode, r0));
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emit_insn (gen_floatunsdidf2 (r1, r0));
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emit_insn (gen_iordi3 (r2, gen_rtx_SUBREG (DImode, r1, 0), setneg));
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emit_move_insn (operands[0], gen_rtx_SUBREG (DFmode, r2, 0));
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DONE;
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})
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(define_expand "floatunsdidf2"
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[(set (match_operand:DF 0 "register_operand" "=r")
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(unsigned_float:DF (match_operand:DI 1 "register_operand" "r")))]
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""
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"{
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rtx value, insns;
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rtx c0 = spu_const_from_ints (V16QImode, 0x02031011, 0x12138080,
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0x06071415, 0x16178080);
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rtx c1 = spu_const_from_ints (V4SImode, 1023+63, 1023+31, 0, 0);
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rtx r0 = gen_reg_rtx (V16QImode);
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rtx r1 = gen_reg_rtx (V4SImode);
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if (optimize_size)
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{
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start_sequence ();
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value =
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emit_library_call_value (convert_optab_libfunc (ufloat_optab,
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DFmode, DImode),
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NULL_RTX, LCT_NORMAL, DFmode, 1, operands[1], DImode);
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insns = get_insns ();
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end_sequence ();
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emit_libcall_block (insns, operands[0], value,
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gen_rtx_UNSIGNED_FLOAT (DFmode, operands[1]));
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}
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else
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{
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emit_move_insn (r1, c1);
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emit_move_insn (r0, c0);
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emit_insn (gen_floatunsdidf2_internal (operands[0], operands[1], r0, r1));
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}
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DONE;
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}")
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(define_insn_and_split "floatunsdidf2_internal"
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[(set (match_operand:DF 0 "register_operand" "=r")
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(unsigned_float:DF (match_operand:DI 1 "register_operand" "r")))
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(use (match_operand:V16QI 2 "register_operand" "r"))
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(use (match_operand:V4SI 3 "register_operand" "r"))
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(clobber (match_scratch:V4SI 4 "=&r"))
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(clobber (match_scratch:V4SI 5 "=&r"))
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(clobber (match_scratch:V4SI 6 "=&r"))]
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""
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"clz\t%4,%1\;shl\t%5,%1,%4\;ceqi\t%6,%4,32\;sf\t%4,%4,%3\;a\t%5,%5,%5\;andc\t%4,%4,%6\;shufb\t%4,%4,%5,%2\;shlqbii\t%4,%4,4\;shlqbyi\t%5,%4,8\;dfa\t%0,%4,%5"
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"reload_completed"
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[(set (match_operand:DF 0 "register_operand" "=r")
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(unsigned_float:DF (match_operand:DI 1 "register_operand" "r")))]
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"{
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rtx *ops = operands;
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rtx op1_v4si = gen_rtx_REG (V4SImode, REGNO(ops[1]));
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rtx op2_ti = gen_rtx_REG (TImode, REGNO(ops[2]));
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rtx op4_ti = gen_rtx_REG (TImode, REGNO(ops[4]));
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rtx op5_ti = gen_rtx_REG (TImode, REGNO(ops[5]));
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rtx op4_df = gen_rtx_REG (DFmode, REGNO(ops[4]));
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rtx op5_df = gen_rtx_REG (DFmode, REGNO(ops[5]));
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emit_insn (gen_clzv4si2 (ops[4],op1_v4si));
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emit_insn (gen_ashlv4si3 (ops[5],op1_v4si,ops[4]));
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emit_insn (gen_ceq_v4si (ops[6],ops[4],spu_const (V4SImode, 32)));
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emit_insn (gen_subv4si3 (ops[4],ops[3],ops[4]));
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emit_insn (gen_addv4si3 (ops[5],ops[5],ops[5]));
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emit_insn (gen_andc_v4si (ops[4],ops[4],ops[6]));
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emit_insn (gen_shufb (ops[4],ops[4],ops[5],op2_ti));
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emit_insn (gen_shlqbi_ti (op4_ti,op4_ti,GEN_INT(4)));
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emit_insn (gen_shlqby_ti (op5_ti,op4_ti,GEN_INT(8)));
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emit_insn (gen_adddf3 (ops[0],op4_df,op5_df));
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DONE;
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}"
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[(set_attr "length" "40")])
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;; add
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