(one_cmpldi2): New pattern.
({a,l}shrdi{3,_const}): Allow 63 as shift count. From-SVN: r9854
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@ -4009,6 +4009,24 @@
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;; one complement instructions
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;; "one_cmpldi2" is only here to help combine().
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(define_insn "one_cmpldi2"
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[(set (match_operand:DI 0 "general_operand" "=dm")
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(not:DI (match_operand:DI 1 "general_operand" "0")))]
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""
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"*
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{
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CC_STATUS_INIT;
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if (GET_CODE (operands[0]) == REG)
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operands[2] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
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else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC
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|| GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
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operands[1] = operands[0];
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else
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operands[1] = adj_offsettable_operand (operands[0], 4);
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return \"not%.l %1\;not%.l %0\";
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}")
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(define_insn "one_cmplsi2"
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[(set (match_operand:SI 0 "general_operand" "=dm")
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(not:SI (match_operand:SI 1 "general_operand" "0")))]
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@ -4293,12 +4311,14 @@
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[(set (match_operand:DI 0 "general_operand" "=d")
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(ashiftrt:DI (match_operand:DI 1 "general_operand" "0")
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(match_operand 2 "const_int_operand" "n")))]
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"(INTVAL (operands[2]) == 1
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|| INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16
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|| INTVAL (operands[2]) == 2 || INTVAL (operands[2]) == 3)"
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"(INTVAL (operands[2]) == 1 || INTVAL (operands[2]) == 2
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|| INTVAL (operands[2]) == 3 || INTVAL (operands[2]) == 8
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|| INTVAL (operands[2]) == 16 || INTVAL (operands[2]) == 63)"
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"*
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{
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operands[1] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
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if (INTVAL (operands[2]) == 63)
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return \"add%.l %0,%0\;subx%.l %0,%0\;move%.l %0,%1\";
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CC_STATUS_INIT;
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if (INTVAL (operands[2]) == 1)
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return \"asr%.l %#1,%0\;roxr%.l %#1,%1\";
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@ -4320,9 +4340,10 @@
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"
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{
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if (GET_CODE (operands[2]) != CONST_INT
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|| (INTVAL (operands[2]) != 1 && INTVAL (operands[2]) != 32
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&& INTVAL (operands[2]) != 8 && INTVAL (operands[2]) != 16
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&& INTVAL (operands[2]) != 2 && INTVAL (operands[2]) != 3))
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|| (INTVAL (operands[2]) != 1 && INTVAL (operands[2]) != 2
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&& INTVAL (operands[2]) != 3 && INTVAL (operands[2]) != 8
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&& INTVAL (operands[2]) != 16 && INTVAL (operands[2]) != 32
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&& INTVAL (operands[2]) != 63))
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FAIL;
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} ")
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@ -4434,13 +4455,15 @@
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[(set (match_operand:DI 0 "general_operand" "=d")
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(lshiftrt:DI (match_operand:DI 1 "general_operand" "0")
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(match_operand 2 "const_int_operand" "n")))]
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"(INTVAL (operands[2]) == 1
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|| INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16
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|| INTVAL (operands[2]) == 2 || INTVAL (operands[2]) == 3)"
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"(INTVAL (operands[2]) == 1 || INTVAL (operands[2]) == 2
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|| INTVAL (operands[2]) == 3 || INTVAL (operands[2]) == 8
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|| INTVAL (operands[2]) == 16 || INTVAL (operands[2]) == 63)"
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"*
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{
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CC_STATUS_INIT;
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operands[1] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
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if (INTVAL (operands[2]) == 63)
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return \"add%.l %0,%0\;clr%.l %0\;clr%.l %1\;addx%.l %1,%1\";
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CC_STATUS_INIT;
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if (INTVAL (operands[2]) == 1)
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return \"lsr%.l %#1,%0\;roxr%.l %#1,%1\";
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else if (INTVAL (operands[2]) == 8)
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@ -4461,9 +4484,10 @@
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"
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{
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if (GET_CODE (operands[2]) != CONST_INT
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|| (INTVAL (operands[2]) != 1 && INTVAL (operands[2]) != 32
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&& INTVAL (operands[2]) != 8 && INTVAL (operands[2]) != 16
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&& INTVAL (operands[2]) != 2 && INTVAL (operands[2]) != 3))
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|| (INTVAL (operands[2]) != 1 && INTVAL (operands[2]) != 2
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&& INTVAL (operands[2]) != 3 && INTVAL (operands[2]) != 8
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&& INTVAL (operands[2]) != 16 && INTVAL (operands[2]) != 32
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&& INTVAL (operands[2]) != 63))
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FAIL;
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} ")
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