re PR target/51931 (No support for MIPS16 long branches)
gcc/ PR target/51931 * config/mips/mips-protos.h (mips_strip_unspec_address): Declare. * config/mips/mips.c (mips_strip_unspec_address): Make extern. (mips16_rewrite_pool_constant): Make a copy of the pool constant before adding to a PC-relative table. (mips16_lay_out_constants): Add a SPLIT_P parameter. (mips16_load_branch_target, mips16_split_long_branches): New functions. (mips_reorg): Update call to mips16_lay_out_constants. Call mips16_split_long_branches. * config/mips/predicates.md (pc_or_label_operand): Delete. * config/mips/mips.md (length): Add a calculation for MIPS16 branches. Move the extended_mips16 handling further down. (*branch_equality<mode>_mips16): Replace use pc_or_label_operand with explicit label_ref and pc. Follow the usual operand numbering. (*branch_equality<mode>_mips16_inverted): New pattern. (*jump_mips16): Add length attribute. (indirect_jump_and_restore_<mode>): New pattern. (consttable_int): Call mips_strip_unspec_address on the operand. gcc/testsuite/ PR target/51931 * gcc.c-torture/compile/20001226-1.c: Remove nomips16 attribute. * g++.dg/opt/longbranch1.C: Likewise. From-SVN: r190104
This commit is contained in:
Richard Sandiford
Richard Sandiford
parent
b5b071a568
commit
36be1dee1d
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@ -1,3 +1,24 @@
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2012-08-02 Richard Sandiford <rdsandiford@googlemail.com>
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PR target/51931
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* config/mips/mips-protos.h (mips_strip_unspec_address): Declare.
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* config/mips/mips.c (mips_strip_unspec_address): Make extern.
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(mips16_rewrite_pool_constant): Make a copy of the pool constant
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before adding to a PC-relative table.
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(mips16_lay_out_constants): Add a SPLIT_P parameter.
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(mips16_load_branch_target, mips16_split_long_branches): New functions.
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(mips_reorg): Update call to mips16_lay_out_constants.
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Call mips16_split_long_branches.
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* config/mips/predicates.md (pc_or_label_operand): Delete.
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* config/mips/mips.md (length): Add a calculation for MIPS16 branches.
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Move the extended_mips16 handling further down.
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(*branch_equality<mode>_mips16): Replace use pc_or_label_operand
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with explicit label_ref and pc. Follow the usual operand numbering.
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(*branch_equality<mode>_mips16_inverted): New pattern.
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(*jump_mips16): Add length attribute.
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(indirect_jump_and_restore_<mode>): New pattern.
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(consttable_int): Call mips_strip_unspec_address on the operand.
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2012-08-02 Richard Sandiford <rdsandiford@googlemail.com>
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* recog.c (split_insn): Copy the original SET_SRC before using
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@ -190,6 +190,7 @@ extern rtx mips_pic_base_register (rtx);
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extern rtx mips_got_load (rtx, rtx, enum mips_symbol_type);
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extern bool mips_split_symbol (rtx, rtx, enum machine_mode, rtx *);
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extern rtx mips_unspec_address (rtx, enum mips_symbol_type);
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extern rtx mips_strip_unspec_address (rtx);
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extern void mips_move_integer (rtx, rtx, unsigned HOST_WIDE_INT);
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extern bool mips_legitimize_move (enum machine_mode, rtx, rtx);
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@ -2563,7 +2563,7 @@ mips_unspec_address (rtx address, enum mips_symbol_type symbol_type)
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/* If OP is an UNSPEC address, return the address to which it refers,
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otherwise return OP itself. */
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static rtx
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rtx
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mips_strip_unspec_address (rtx op)
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{
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rtx base, offset;
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@ -14070,7 +14070,7 @@ mips16_rewrite_pool_constant (struct mips16_constant_pool *pool, rtx *x)
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split_const (*x, &base, &offset);
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if (GET_CODE (base) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (base))
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{
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label = mips16_add_constant (pool, get_pool_constant (base),
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label = mips16_add_constant (pool, copy_rtx (get_pool_constant (base)),
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get_pool_mode (base));
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base = gen_rtx_LABEL_REF (Pmode, label);
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*x = mips_unspec_address_offset (base, offset, SYMBOL_PC_RELATIVE);
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@ -14126,10 +14126,11 @@ mips_cfg_in_reorg (void)
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|| TARGET_RELAX_PIC_CALLS);
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}
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/* Build MIPS16 constant pools. */
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/* Build MIPS16 constant pools. Split the instructions if SPLIT_P,
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otherwise assume that they are already split. */
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static void
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mips16_lay_out_constants (void)
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mips16_lay_out_constants (bool split_p)
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{
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struct mips16_constant_pool pool;
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struct mips16_rewrite_pool_refs_info info;
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@ -14138,10 +14139,13 @@ mips16_lay_out_constants (void)
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if (!TARGET_MIPS16_PCREL_LOADS)
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return;
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if (mips_cfg_in_reorg ())
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split_all_insns ();
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else
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split_all_insns_noflow ();
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if (split_p)
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{
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if (mips_cfg_in_reorg ())
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split_all_insns ();
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else
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split_all_insns_noflow ();
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}
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barrier = 0;
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memset (&pool, 0, sizeof (pool));
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for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
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@ -15490,6 +15494,110 @@ mips_df_reorg (void)
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df_finish_pass (false);
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}
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/* Emit code to load LABEL_REF SRC into MIPS16 register DEST. This is
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called very late in mips_reorg, but the caller is required to run
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mips16_lay_out_constants on the result. */
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static void
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mips16_load_branch_target (rtx dest, rtx src)
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{
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if (TARGET_ABICALLS && !TARGET_ABSOLUTE_ABICALLS)
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{
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rtx page, low;
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if (mips_cfun_has_cprestore_slot_p ())
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mips_emit_move (dest, mips_cprestore_slot (dest, true));
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else
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mips_emit_move (dest, pic_offset_table_rtx);
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page = mips_unspec_address (src, SYMBOL_GOTOFF_PAGE);
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low = mips_unspec_address (src, SYMBOL_GOT_PAGE_OFST);
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emit_insn (gen_rtx_SET (VOIDmode, dest,
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PMODE_INSN (gen_unspec_got, (dest, page))));
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emit_insn (gen_rtx_SET (VOIDmode, dest,
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gen_rtx_LO_SUM (Pmode, dest, low)));
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}
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else
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{
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src = mips_unspec_address (src, SYMBOL_ABSOLUTE);
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mips_emit_move (dest, src);
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}
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}
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/* If we're compiling a MIPS16 function, look for and split any long branches.
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This must be called after all other instruction modifications in
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mips_reorg. */
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static void
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mips16_split_long_branches (void)
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{
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bool something_changed;
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if (!TARGET_MIPS16)
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return;
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/* Loop until the alignments for all targets are sufficient. */
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do
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{
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rtx insn;
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shorten_branches (get_insns ());
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something_changed = false;
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for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
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if (JUMP_P (insn)
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&& USEFUL_INSN_P (insn)
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&& get_attr_length (insn) > 8)
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{
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rtx old_label, new_label, temp, saved_temp;
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rtx target, jump, jump_sequence;
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start_sequence ();
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/* Free up a MIPS16 register by saving it in $1. */
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saved_temp = gen_rtx_REG (Pmode, AT_REGNUM);
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temp = gen_rtx_REG (Pmode, GP_REG_FIRST + 2);
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emit_move_insn (saved_temp, temp);
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/* Load the branch target into TEMP. */
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old_label = JUMP_LABEL (insn);
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target = gen_rtx_LABEL_REF (Pmode, old_label);
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mips16_load_branch_target (temp, target);
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/* Jump to the target and restore the register's
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original value. */
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jump = emit_jump_insn (PMODE_INSN (gen_indirect_jump_and_restore,
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(temp, temp, saved_temp)));
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JUMP_LABEL (jump) = old_label;
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LABEL_NUSES (old_label)++;
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/* Rewrite any symbolic references that are supposed to use
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a PC-relative constant pool. */
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mips16_lay_out_constants (false);
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if (simplejump_p (insn))
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/* We're going to replace INSN with a longer form. */
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new_label = NULL_RTX;
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else
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{
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/* Create a branch-around label for the original
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instruction. */
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new_label = gen_label_rtx ();
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emit_label (new_label);
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}
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jump_sequence = get_insns ();
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end_sequence ();
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emit_insn_after (jump_sequence, insn);
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if (new_label)
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invert_jump (insn, new_label, false);
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else
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delete_insn (insn);
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something_changed = true;
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}
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}
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while (something_changed);
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}
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/* Implement TARGET_MACHINE_DEPENDENT_REORG. */
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static void
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@ -15500,7 +15608,7 @@ mips_reorg (void)
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to date if the CFG is available. */
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if (mips_cfg_in_reorg ())
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compute_bb_for_insn ();
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mips16_lay_out_constants ();
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mips16_lay_out_constants (true);
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if (mips_cfg_in_reorg ())
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{
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mips_df_reorg ();
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@ -15519,6 +15627,7 @@ mips_reorg (void)
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/* The expansion could invalidate some of the VR4130 alignment
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optimizations, but this should be an extremely rare case anyhow. */
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mips_reorg_process_insns ();
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mips16_split_long_branches ();
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}
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/* Implement TARGET_ASM_OUTPUT_MI_THUNK. Generate rtl rather than asm text
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@ -15639,7 +15748,7 @@ mips_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
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insn = get_insns ();
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insn_locators_alloc ();
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split_all_insns_noflow ();
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mips16_lay_out_constants ();
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mips16_lay_out_constants (true);
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shorten_branches (insn);
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final_start_function (insn, file, 1);
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final (insn, file, 1);
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@ -402,11 +402,7 @@
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;; Length of instruction in bytes.
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(define_attr "length" ""
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(cond [(and (eq_attr "extended_mips16" "yes")
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(match_test "TARGET_MIPS16"))
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(const_int 8)
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;; Direct branch instructions have a range of [-0x20000,0x1fffc],
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(cond [;; Direct branch instructions have a range of [-0x20000,0x1fffc],
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;; relative to the address of the delay slot. If a branch is
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;; outside this range, we have a choice of two sequences.
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;; For PIC, an out-of-range branch like:
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@ -431,14 +427,21 @@
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;; using la/jr in this case too, but we do not do so at
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;; present.
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;;
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;; Note that this value does not account for the delay slot
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;; The value we specify here does not account for the delay slot
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;; instruction, whose length is added separately. If the RTL
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;; pattern has no explicit delay slot, mips_adjust_insn_length
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;; will add the length of the implicit nop. The values for
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;; forward and backward branches will be different as well.
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(eq_attr "type" "branch")
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;; will add the length of the implicit nop. The range of
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;; [-0x20000, 0x1fffc] from the address of the delay slot
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;; therefore translates to a range of:
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;;
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;; [-(0x20000 - sizeof (branch)), 0x1fffc - sizeof (slot)]
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;; == [-0x1fffc, 0x1fff8]
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;;
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;; from the shorten_branches reference address.
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(and (eq_attr "type" "branch")
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(not (match_test "TARGET_MIPS16")))
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(cond [(and (le (minus (match_dup 0) (pc)) (const_int 131064))
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(le (minus (pc) (match_dup 0)) (const_int 131068)))
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(le (minus (pc) (match_dup 0)) (const_int 131068)))
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(const_int 4)
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;; The non-PIC case: branch, first delay slot, and J.
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@ -453,6 +456,100 @@
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;; of an insn.
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(const_int MAX_PIC_BRANCH_LENGTH))
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;; An unextended MIPS16 branch has a range of [-0x100, 0xfe]
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;; from the address of the following instruction, which leads
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;; to a range of:
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;;
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;; [-(0x100 - sizeof (branch)), 0xfe]
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;; == [-0xfe, 0xfe]
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;;
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;; from the shorten_branches reference address. Extended branches
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;; likewise have a range of [-0x10000, 0xfffe] from the address
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;; of the following instruction, which leads to a range of:
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;;
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;; [-(0x10000 - sizeof (branch)), 0xfffe]
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;; == [-0xfffc, 0xfffe]
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;;
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;; from the reference address.
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;;
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;; When a branch is out of range, mips_reorg splits it into a form
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;; that uses in-range branches. There are four basic sequences:
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;;
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;; (1) Absolute addressing with a readable text segment
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;; (32-bit addresses):
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;;
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;; b... foo 2 bytes
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;; move $1,$2 2 bytes
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;; lw $2,label 2 bytes
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;; jr $2 2 bytes
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;; move $2,$1 2 bytes
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;; .align 2 0 or 2 bytes
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;; label:
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;; .word target 4 bytes
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;; foo:
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;; (16 bytes in the worst case)
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;;
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;; (2) Absolute addressing with a readable text segment
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;; (64-bit addresses):
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;;
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;; b... foo 2 bytes
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;; move $1,$2 2 bytes
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;; ld $2,label 2 bytes
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;; jr $2 2 bytes
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;; move $2,$1 2 bytes
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;; .align 3 0 to 6 bytes
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;; label:
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;; .dword target 8 bytes
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;; foo:
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;; (24 bytes in the worst case)
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;;
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;; (3) Absolute addressing without a readable text segment
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;; (which requires 32-bit addresses at present):
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;;
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;; b... foo 2 bytes
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;; move $1,$2 2 bytes
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;; lui $2,%hi(target) 4 bytes
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;; sll $2,8 2 bytes
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;; sll $2,8 2 bytes
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;; addiu $2,%lo(target) 4 bytes
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;; jr $2 2 bytes
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;; move $2,$1 2 bytes
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;; foo:
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;; (20 bytes)
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;;
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;; (4) PIC addressing (which requires 32-bit addresses at present):
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;;
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;; b... foo 2 bytes
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;; move $1,$2 2 bytes
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;; lw $2,cprestore 0, 2 or 4 bytes
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;; lw $2,%got(target)($2) 4 bytes
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;; addiu $2,%lo(target) 4 bytes
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;; jr $2 2 bytes
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;; move $2,$1 2 bytes
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;; foo:
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;; (20 bytes in the worst case)
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;;
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;; Note that the conditions test adjusted lengths, whereas the
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;; result is an unadjusted length, and is thus twice the true value.
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(and (eq_attr "type" "branch")
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(match_test "TARGET_MIPS16"))
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(cond [(and (le (minus (match_dup 0) (pc)) (const_int 254))
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(le (minus (pc) (match_dup 0)) (const_int 254)))
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(const_int 4)
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(and (le (minus (match_dup 0) (pc)) (const_int 65534))
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(le (minus (pc) (match_dup 0)) (const_int 65532)))
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(const_int 8)
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(and (match_test "TARGET_ABICALLS")
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(not (match_test "TARGET_ABSOLUTE_ABICALLS")))
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(const_int 40)
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(match_test "Pmode == SImode")
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(const_int 32)
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] (const_int 48))
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(and (eq_attr "extended_mips16" "yes")
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(match_test "TARGET_MIPS16"))
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(const_int 8)
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;; "Ghost" instructions occupy no space.
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(eq_attr "type" "ghost")
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(const_int 0)
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@ -5400,28 +5497,29 @@
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(define_insn "*branch_equality<mode>_mips16"
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[(set (pc)
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(if_then_else
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(match_operator 0 "equality_operator"
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[(match_operand:GPR 1 "register_operand" "d,t")
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(match_operator 1 "equality_operator"
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[(match_operand:GPR 2 "register_operand" "d,t")
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(const_int 0)])
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(match_operand 2 "pc_or_label_operand" "")
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(match_operand 3 "pc_or_label_operand" "")))]
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(label_ref (match_operand 0 "" ""))
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(pc)))]
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"TARGET_MIPS16"
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{
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if (operands[2] != pc_rtx)
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{
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if (which_alternative == 0)
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return "b%C0z\t%1,%2";
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else
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return "bt%C0z\t%2";
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}
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else
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{
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if (which_alternative == 0)
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return "b%N0z\t%1,%3";
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else
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return "bt%N0z\t%3";
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}
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}
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"@
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b%C1z\t%2,%0
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bt%C1z\t%0"
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[(set_attr "type" "branch")])
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(define_insn "*branch_equality<mode>_mips16_inverted"
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[(set (pc)
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(if_then_else
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(match_operator 1 "equality_operator"
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[(match_operand:GPR 2 "register_operand" "d,t")
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(const_int 0)])
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(pc)
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(label_ref (match_operand 0 "" ""))))]
|
||||
"TARGET_MIPS16"
|
||||
"@
|
||||
b%N1z\t%2,%0
|
||||
bt%N1z\t%0"
|
||||
[(set_attr "type" "branch")])
|
||||
|
||||
(define_expand "cbranch<mode>4"
|
||||
|
|
@ -5717,7 +5815,30 @@
|
|||
(label_ref (match_operand 0 "" "")))]
|
||||
"TARGET_MIPS16"
|
||||
"b\t%l0"
|
||||
[(set_attr "type" "branch")])
|
||||
[(set_attr "type" "branch")
|
||||
(set (attr "length")
|
||||
;; This calculation is like the normal branch one, but the
|
||||
;; range of the unextended instruction is [-0x800, 0x7fe] rather
|
||||
;; than [-0x100, 0xfe]. This translates to a range of:
|
||||
;;
|
||||
;; [-(0x800 - sizeof (branch)), 0x7fe]
|
||||
;; == [-0x7fe, 0x7fe]
|
||||
;;
|
||||
;; from the shorten_branches reference address. Long-branch
|
||||
;; sequences will replace this one, so the minimum length
|
||||
;; is one instruction shorter than for conditional branches.
|
||||
(cond [(and (le (minus (match_dup 0) (pc)) (const_int 2046))
|
||||
(le (minus (pc) (match_dup 0)) (const_int 2046)))
|
||||
(const_int 4)
|
||||
(and (le (minus (match_dup 0) (pc)) (const_int 65534))
|
||||
(le (minus (pc) (match_dup 0)) (const_int 65532)))
|
||||
(const_int 8)
|
||||
(and (match_test "TARGET_ABICALLS")
|
||||
(not (match_test "TARGET_ABSOLUTE_ABICALLS")))
|
||||
(const_int 36)
|
||||
(match_test "Pmode == SImode")
|
||||
(const_int 28)
|
||||
] (const_int 44)))])
|
||||
|
||||
(define_expand "indirect_jump"
|
||||
[(set (pc) (match_operand 0 "register_operand"))]
|
||||
|
|
@ -5735,6 +5856,18 @@
|
|||
[(set_attr "type" "jump")
|
||||
(set_attr "mode" "none")])
|
||||
|
||||
;; A combined jump-and-move instruction, used for MIPS16 long-branch
|
||||
;; sequences. Having a dedicated pattern is more convenient than
|
||||
;; creating a SEQUENCE for this special case.
|
||||
(define_insn "indirect_jump_and_restore_<mode>"
|
||||
[(set (pc) (match_operand:P 1 "register_operand" "d"))
|
||||
(set (match_operand:P 0 "register_operand" "=d")
|
||||
(match_operand:P 2 "register_operand" "y"))]
|
||||
""
|
||||
"%(%<jr\t%1\;move\t%0,%2%>%)"
|
||||
[(set_attr "type" "multi")
|
||||
(set_attr "extended_mips16" "yes")])
|
||||
|
||||
(define_expand "tablejump"
|
||||
[(set (pc)
|
||||
(match_operand 0 "register_operand"))
|
||||
|
|
@ -6549,7 +6682,8 @@
|
|||
UNSPEC_CONSTTABLE_INT)]
|
||||
"TARGET_MIPS16"
|
||||
{
|
||||
assemble_integer (operands[0], INTVAL (operands[1]),
|
||||
assemble_integer (mips_strip_unspec_address (operands[0]),
|
||||
INTVAL (operands[1]),
|
||||
BITS_PER_UNIT * INTVAL (operands[1]), 1);
|
||||
return "";
|
||||
}
|
||||
|
|
|
|||
|
|
@ -139,9 +139,6 @@
|
|||
(match_operand 0 "hilo_operand")
|
||||
(match_operand 0 "register_operand")))
|
||||
|
||||
(define_special_predicate "pc_or_label_operand"
|
||||
(match_code "pc,label_ref"))
|
||||
|
||||
(define_predicate "const_call_insn_operand"
|
||||
(match_code "const,symbol_ref,label_ref")
|
||||
{
|
||||
|
|
|
|||
|
|
@ -1,3 +1,9 @@
|
|||
2012-08-02 Richard Sandiford <rdsandiford@googlemail.com>
|
||||
|
||||
PR target/51931
|
||||
* gcc.c-torture/compile/20001226-1.c: Remove nomips16 attribute.
|
||||
* g++.dg/opt/longbranch1.C: Likewise.
|
||||
|
||||
2012-08-02 Marc Glisse <marc.glisse@inria.fr>
|
||||
|
||||
PR tree-optimization/53805
|
||||
|
|
|
|||
|
|
@ -26,10 +26,6 @@
|
|||
muchcode; muchcode; muchcode; muchcode; muchcode; muchcode; \
|
||||
muchcode; muchcode; muchcode; muchcode; muchcode; muchcode
|
||||
|
||||
#ifdef __mips
|
||||
/* See PR 51931. */
|
||||
__attribute__((nomips16))
|
||||
#endif
|
||||
int
|
||||
main (int argc, char **argv)
|
||||
{
|
||||
|
|
|
|||
|
|
@ -21,10 +21,6 @@
|
|||
#define C1024(x,y) C256(x,y) C256(x+16,y) C256(x+32,y) C256(x+48,y)
|
||||
#define C4096(x,y) C1024(x,y) C1024(x,y+16) C1024(x,y+32) C1024(x,y+48)
|
||||
|
||||
#ifdef __mips
|
||||
/* See PR 51931. */
|
||||
__attribute__((nomips16))
|
||||
#endif
|
||||
unsigned foo(int x[64], int y[64])
|
||||
{
|
||||
C4096(x,y);
|
||||
|
|
|
|||
Loading…
Reference in New Issue