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tree-optimization/105312 - fix ISEL VCOND expansion

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The following aligns ISEL VEC_COND_EXPR expansion using VCOND
with the optab query done by vector lowering.  Instead of only
allowing the signed optab to provide EQ/NE compares we allow both
here though since there seems to be no documented canonicalization.

2022-04-20  Richard Biener  <rguenther@suse.de>

	PR tree-optimization/105312
	* gimple-isel.cc (gimple_expand_vec_cond_expr): Query both
	VCOND and VCONDU for EQ and NE.

	* gcc.target/arm/pr105312.c: New testcase.
This commit is contained in:
Richard Biener 2022-04-20 10:17:24 +02:00
parent 0707f42809
commit 36f1de95a6
2 changed files with 31 additions and 0 deletions
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8
gcc/gimple-isel.cc
View File

@ -245,6 +245,14 @@ gimple_expand_vec_cond_expr (struct function *fun, gimple_stmt_iterator *gsi,
GET_MODE_NUNITS (cmp_op_mode)));
icode = get_vcond_icode (mode, cmp_op_mode, unsignedp);
/* Some targets do not have vcondeq and only vcond with NE/EQ
but not vcondu, so make sure to also try vcond here as
vcond_icode_p would canonicalize the optab query to. */
if (icode == CODE_FOR_nothing
&& (tcode == NE_EXPR || tcode == EQ_EXPR)
&& ((icode = get_vcond_icode (mode, cmp_op_mode, !unsignedp))
!= CODE_FOR_nothing))
unsignedp = !unsignedp;
if (icode == CODE_FOR_nothing)
{
if (tcode == LT_EXPR

23
gcc/testsuite/gcc.target/arm/pr105312.c Normal file
View File

@ -0,0 +1,23 @@
/* { dg-do compile } */
/* { dg-require-effective-target arm_neon_ok } */
/* { dg-options "-mcpu=cortex-a15" } */
/* { dg-add-options arm_neon } */
typedef float stress_matrix_type_t;
typedef unsigned int size_t;
static void __attribute__((optimize("-O3"))) stress_matrix_xy_identity(
const size_t n,
stress_matrix_type_t a[restrict n][n],
stress_matrix_type_t b[restrict n][n],
stress_matrix_type_t r[restrict n][n])
{
register size_t i;
(void)a;
(void)b;
for (i = 0; i < n; i++) {
register size_t j;
for (j = 0; j < n; j++)
r[i][j] = (i == j) ? 1.0 : 0.0;
return;
}
}