re PR target/80510 (Optimize Power7/power8 Altivec load/stores)
[gcc] 2017-06-23 Michael Meissner <meissner@linux.vnet.ibm.com> PR target/80510 * config/rs6000/rs6000.md (ALTIVEC_DFORM): Do not allow DImode in 32-bit, since indexed is not valid for DImode. (mov<mode>_hardfloat32): Reorder ISA 2.07 load/stores before ISA 3.0 d-form load/stores to be the same as mov<mode>_hardfloat64. (define_peephole2 for Altivec d-form load): Add 32-bit support. (define_peephole2 for Altivec d-form store): Likewise. [gcc/testsuite] 2017-06-23 Michael Meissner <meissner@linux.vnet.ibm.com> PR target/80510 * gcc.target/powerpc/pr80510-1.c: Allow test to run on 32-bit. * gcc.target/powerpc/pr80510-2.c: Likewise. From-SVN: r249607
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Michael Meissner
Michael Meissner
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@ -1,5 +1,13 @@
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2017-06-23 Michael Meissner <meissner@linux.vnet.ibm.com>
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PR target/80510
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* config/rs6000/rs6000.md (ALTIVEC_DFORM): Do not allow DImode in
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32-bit, since indexed is not valid for DImode.
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(mov<mode>_hardfloat32): Reorder ISA 2.07 load/stores before ISA
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3.0 d-form load/stores to be the same as mov<mode>_hardfloat64.
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(define_peephole2 for Altivec d-form load): Add 32-bit support.
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(define_peephole2 for Altivec d-form store): Likewise.
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PR ipa/81185
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* multiple_target.c (create_dispatcher_calls): Only create the
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dispatcher call if the function is the default clone of a
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@ -690,7 +690,9 @@
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;; Iterator to optimize the following cases:
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;; D-form load to FPR register & move to Altivec register
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;; Move Altivec register to FPR register and store
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(define_mode_iterator ALTIVEC_DFORM [DI DF SF])
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(define_mode_iterator ALTIVEC_DFORM [DF
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SF
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(DI "TARGET_POWERPC64")])
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;; Start with fixed-point load and store insns. Here we put only the more
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@ -7391,8 +7393,8 @@
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;; except for 0.0 which can be created on VSX with an xor instruction.
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(define_insn "*mov<mode>_hardfloat32"
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[(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=m,d,d,<f64_av>,Z,<f64_p9>,wY,<f64_vsx>,<f64_vsx>,!r,Y,r,!r")
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(match_operand:FMOVE64 1 "input_operand" "d,m,d,Z,<f64_av>,wY,<f64_p9>,<f64_vsx>,<zero_fp>,<zero_fp>,r,Y,r"))]
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[(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=m,d,d,<f64_p9>,wY,<f64_av>,Z,<f64_vsx>,<f64_vsx>,!r,Y,r,!r")
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(match_operand:FMOVE64 1 "input_operand" "d,m,d,wY,<f64_p9>,Z,<f64_av>,<f64_vsx>,<zero_fp>,<zero_fp>,r,Y,r"))]
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"! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT
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&& (gpc_reg_operand (operands[0], <MODE>mode)
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|| gpc_reg_operand (operands[1], <MODE>mode))"
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@ -7400,10 +7402,10 @@
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stfd%U0%X0 %1,%0
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lfd%U1%X1 %0,%1
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fmr %0,%1
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lxsd%U1x %x0,%y1
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stxsd%U0x %x1,%y0
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lxsd %0,%1
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stxsd %1,%0
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lxsd%U1x %x0,%y1
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stxsd%U0x %x1,%y0
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xxlor %x0,%x1,%x1
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xxlxor %x0,%x0,%x0
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#
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@ -13967,13 +13969,13 @@
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;; LXSDX 32,3,9
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(define_peephole2
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[(match_scratch:DI 0 "b")
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[(match_scratch:P 0 "b")
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(set (match_operand:ALTIVEC_DFORM 1 "fpr_reg_operand")
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(match_operand:ALTIVEC_DFORM 2 "simple_offsettable_mem_operand"))
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(set (match_operand:ALTIVEC_DFORM 3 "altivec_register_operand")
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(match_dup 1))]
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"TARGET_VSX && TARGET_POWERPC64 && TARGET_UPPER_REGS_<MODE>
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&& !TARGET_P9_DFORM_SCALAR && peep2_reg_dead_p (2, operands[1])"
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"TARGET_VSX && TARGET_UPPER_REGS_<MODE> && !TARGET_P9_DFORM_SCALAR
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&& peep2_reg_dead_p (2, operands[1])"
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[(set (match_dup 0)
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(match_dup 4))
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(set (match_dup 3)
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@ -13988,7 +13990,7 @@
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add_op0 = XEXP (addr, 0);
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add_op1 = XEXP (addr, 1);
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gcc_assert (REG_P (add_op0));
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new_addr = gen_rtx_PLUS (DImode, add_op0, tmp_reg);
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new_addr = gen_rtx_PLUS (Pmode, add_op0, tmp_reg);
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operands[4] = add_op1;
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operands[5] = change_address (mem, <MODE>mode, new_addr);
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@ -14004,13 +14006,13 @@
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;; STXSDX 32,3,9
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(define_peephole2
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[(match_scratch:DI 0 "b")
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[(match_scratch:P 0 "b")
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(set (match_operand:ALTIVEC_DFORM 1 "fpr_reg_operand")
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(match_operand:ALTIVEC_DFORM 2 "altivec_register_operand"))
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(set (match_operand:ALTIVEC_DFORM 3 "simple_offsettable_mem_operand")
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(match_dup 1))]
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"TARGET_VSX && TARGET_POWERPC64 && TARGET_UPPER_REGS_<MODE>
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&& !TARGET_P9_DFORM_SCALAR && peep2_reg_dead_p (2, operands[1])"
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"TARGET_VSX && TARGET_UPPER_REGS_<MODE> && !TARGET_P9_DFORM_SCALAR
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&& peep2_reg_dead_p (2, operands[1])"
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[(set (match_dup 0)
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(match_dup 4))
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(set (match_dup 5)
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@ -14025,7 +14027,7 @@
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add_op0 = XEXP (addr, 0);
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add_op1 = XEXP (addr, 1);
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gcc_assert (REG_P (add_op0));
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new_addr = gen_rtx_PLUS (DImode, add_op0, tmp_reg);
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new_addr = gen_rtx_PLUS (Pmode, add_op0, tmp_reg);
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operands[4] = add_op1;
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operands[5] = change_address (mem, <MODE>mode, new_addr);
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@ -1,3 +1,9 @@
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2017-06-23 Michael Meissner <meissner@linux.vnet.ibm.com>
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PR target/80510
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* gcc.target/powerpc/pr80510-1.c: Allow test to run on 32-bit.
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* gcc.target/powerpc/pr80510-2.c: Likewise.
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2017-06-22 Jeff Law <law@redhat.com>
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* gcc.c-torture/compile/stack-check-1.c: Require "untyped_assembly".
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@ -1,4 +1,4 @@
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/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */
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/* { dg-do compile { target { powerpc*-*-* } } } */
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/* { dg-skip-if "" { powerpc*-*-darwin* } } */
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/* { dg-require-effective-target powerpc_vsx_ok } */
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/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power7" } } */
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@ -6,9 +6,7 @@
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/* Make sure that STXSDX is generated for double scalars in Altivec registers
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on power7 instead of moving the value to a FPR register and doing a X-FORM
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store.
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32-bit currently does not have support for STXSDX in the mov{df,dd} patterns. */
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store. */
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#ifndef TYPE
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#define TYPE double
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@ -1,4 +1,4 @@
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/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */
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/* { dg-do compile { target { powerpc*-*-* } } } */
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/* { dg-skip-if "" { powerpc*-*-darwin* } } */
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/* { dg-require-effective-target powerpc_p8vector_ok } */
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/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */
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@ -6,9 +6,7 @@
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/* Make sure that STXSSPX is generated for float scalars in Altivec registers
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on power7 instead of moving the value to a FPR register and doing a X-FORM
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store.
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32-bit currently does not have support for STXSSPX in the mov{sf,sd} patterns. */
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store. */
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#ifndef TYPE
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#define TYPE float
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