i386.c (ix86_simd_clone_compute_vecsize_and_simdlen): Add support for AVX512F clones...
* config/i386/i386.c (ix86_simd_clone_compute_vecsize_and_simdlen): Add support for AVX512F clones, include them by default for exported OpenMP declare simd functions. For AVX2 allow simdlen 32 and use it if charasteric type is 8-bit, for AVX512F allow simdlen up to 128. * lib/target-supports.exp (check_effective_target_vect_simd_clones): Check for avx512f effective targets instead of avx2. * gcc.dg/gomp/declare-simd-1.c: Add scan-assembler-times directives for AVX512F clones. * gcc.dg/gomp/declare-simd-3.c: Likewise. * g++.dg/gomp/declare-simd-1.C: Likewise. * g++.dg/gomp/declare-simd-3.C: Likewise. * g++.dg/gomp/declare-simd-4.C: Likewise. From-SVN: r234780
This commit is contained in:
Jakub Jelinek
Jakub Jelinek
parent
ec35ea455c
commit
3866f8dd85
@ -1,5 +1,11 @@
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2016-04-06 Jakub Jelinek <jakub@redhat.com>
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* config/i386/i386.c (ix86_simd_clone_compute_vecsize_and_simdlen):
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Add support for AVX512F clones, include them by default for
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exported OpenMP declare simd functions. For AVX2 allow simdlen 32
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and use it if charasteric type is 8-bit, for AVX512F allow simdlen
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up to 128.
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PR middle-end/70550
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* tree.h (OMP_CLAUSE_FIRSTPRIVATE_IMPLICIT): Define.
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* gimplify.c (gimplify_adjust_omp_clauses_1): Set it for implicit
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@ -53761,7 +53761,7 @@ ix86_simd_clone_compute_vecsize_and_simdlen (struct cgraph_node *node,
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if (clonei->simdlen
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&& (clonei->simdlen < 2
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|| clonei->simdlen > 16
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|| clonei->simdlen > 128
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|| (clonei->simdlen & (clonei->simdlen - 1)) != 0))
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{
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warning_at (DECL_SOURCE_LOCATION (node->decl), 0,
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@ -53819,7 +53819,9 @@ ix86_simd_clone_compute_vecsize_and_simdlen (struct cgraph_node *node,
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{
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/* If the function isn't exported, we can pick up just one ISA
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for the clones. */
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if (TARGET_AVX2)
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if (TARGET_AVX512F)
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clonei->vecsize_mangle = 'e';
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else if (TARGET_AVX2)
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clonei->vecsize_mangle = 'd';
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else if (TARGET_AVX)
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clonei->vecsize_mangle = 'c';
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@ -53829,8 +53831,8 @@ ix86_simd_clone_compute_vecsize_and_simdlen (struct cgraph_node *node,
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}
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else
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{
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clonei->vecsize_mangle = "bcd"[num];
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ret = 3;
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clonei->vecsize_mangle = "bcde"[num];
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ret = 4;
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}
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switch (clonei->vecsize_mangle)
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{
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@ -53846,6 +53848,10 @@ ix86_simd_clone_compute_vecsize_and_simdlen (struct cgraph_node *node,
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clonei->vecsize_int = 256;
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clonei->vecsize_float = 256;
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break;
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case 'e':
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clonei->vecsize_int = 512;
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clonei->vecsize_float = 512;
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break;
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}
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if (clonei->simdlen == 0)
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{
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@ -53854,9 +53860,24 @@ ix86_simd_clone_compute_vecsize_and_simdlen (struct cgraph_node *node,
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else
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clonei->simdlen = clonei->vecsize_float;
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clonei->simdlen /= GET_MODE_BITSIZE (TYPE_MODE (base_type));
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if (clonei->simdlen > 16)
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clonei->simdlen = 16;
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}
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else if (clonei->simdlen > 16)
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switch (clonei->vecsize_int)
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{
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case 512:
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/* For AVX512-F, support VLEN up to 128. */
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break;
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case 256:
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/* For AVX2, support VLEN up to 32. */
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if (clonei->simdlen <= 32)
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break;
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/* FALLTHRU */
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default:
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/* Otherwise, support VLEN up to 16. */
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warning_at (DECL_SOURCE_LOCATION (node->decl), 0,
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"unsupported simdlen %d", clonei->simdlen);
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return 0;
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}
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return ret;
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}
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@ -53881,6 +53902,10 @@ ix86_simd_clone_adjust (struct cgraph_node *node)
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if (!TARGET_AVX2)
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str = "avx2";
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break;
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case 'e':
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if (!TARGET_AVX512F)
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str = "avx512f";
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break;
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default:
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gcc_unreachable ();
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}
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@ -53920,6 +53945,10 @@ ix86_simd_clone_usable (struct cgraph_node *node)
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if (!TARGET_AVX2)
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return -1;
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return 0;
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case 'e':
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if (!TARGET_AVX512F)
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return -1;
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return 0;
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default:
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gcc_unreachable ();
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}
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@ -1,5 +1,14 @@
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2016-04-06 Jakub Jelinek <jakub@redhat.com>
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* lib/target-supports.exp (check_effective_target_vect_simd_clones):
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Check for avx512f effective targets instead of avx2.
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* gcc.dg/gomp/declare-simd-1.c: Add scan-assembler-times directives
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for AVX512F clones.
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* gcc.dg/gomp/declare-simd-3.c: Likewise.
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* g++.dg/gomp/declare-simd-1.C: Likewise.
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* g++.dg/gomp/declare-simd-3.C: Likewise.
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* g++.dg/gomp/declare-simd-4.C: Likewise.
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PR middle-end/70550
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* c-c++-common/gomp/pr70550-1.c: New test.
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* c-c++-common/gomp/pr70550-2.c: New test.
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@ -20,6 +20,8 @@ int f2 (int a, int *b, int c)
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// { dg-final { scan-assembler-times "_ZGVcN8uva32l4__Z2f2iPii:" 1 { target { i?86-*-* x86_64-*-* } } } }
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// { dg-final { scan-assembler-times "_ZGVdM8uva32l4__Z2f2iPii:" 1 { target { i?86-*-* x86_64-*-* } } } }
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// { dg-final { scan-assembler-times "_ZGVdN8uva32l4__Z2f2iPii:" 1 { target { i?86-*-* x86_64-*-* } } } }
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// { dg-final { scan-assembler-times "_ZGVeM8uva32l4__Z2f2iPii:" 1 { target { i?86-*-* x86_64-*-* } } } }
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// { dg-final { scan-assembler-times "_ZGVeN8uva32l4__Z2f2iPii:" 1 { target { i?86-*-* x86_64-*-* } } } }
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#pragma omp declare simd uniform (c) aligned (b : 4 * sizeof (int)) linear (a : 4) simdlen (4)
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template <typename T>
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@ -85,6 +87,8 @@ namespace N1
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// { dg-final { scan-assembler-times "_ZGVcN2va16__ZN2N12N23f10EPx:" 1 { target { i?86-*-* x86_64-*-* } } } }
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// { dg-final { scan-assembler-times "_ZGVdM2va16__ZN2N12N23f10EPx:" 1 { target { i?86-*-* x86_64-*-* } } } }
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// { dg-final { scan-assembler-times "_ZGVdN2va16__ZN2N12N23f10EPx:" 1 { target { i?86-*-* x86_64-*-* } } } }
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// { dg-final { scan-assembler-times "_ZGVeM2va16__ZN2N12N23f10EPx:" 1 { target { i?86-*-* x86_64-*-* } } } }
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// { dg-final { scan-assembler-times "_ZGVeN2va16__ZN2N12N23f10EPx:" 1 { target { i?86-*-* x86_64-*-* } } } }
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struct A
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{
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@ -193,6 +197,8 @@ int B<int>::f25<7> (int a, int *b, int c)
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// { dg-final { scan-assembler-times "_ZGVcN8vuva32u__ZN1BIiE3f25ILi7EEEiiPii:" 1 { target { i?86-*-* x86_64-*-* } } } }
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// { dg-final { scan-assembler-times "_ZGVdM8vuva32u__ZN1BIiE3f25ILi7EEEiiPii:" 1 { target { i?86-*-* x86_64-*-* } } } }
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// { dg-final { scan-assembler-times "_ZGVdN8vuva32u__ZN1BIiE3f25ILi7EEEiiPii:" 1 { target { i?86-*-* x86_64-*-* } } } }
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// { dg-final { scan-assembler-times "_ZGVeM8vuva32u__ZN1BIiE3f25ILi7EEEiiPii:" 1 { target { i?86-*-* x86_64-*-* } } } }
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// { dg-final { scan-assembler-times "_ZGVeN8vuva32u__ZN1BIiE3f25ILi7EEEiiPii:" 1 { target { i?86-*-* x86_64-*-* } } } }
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#pragma omp declare simd simdlen (4) aligned (b : 8 * sizeof (int)) linear (a, c : 2)
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template <>
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@ -208,6 +214,8 @@ int B<int>::f26<-1> (int a, int *b, int c)
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// { dg-final { scan-assembler-times "_ZGVcN4vl2va32__ZN1BIiE3f26ILin1EEEiiPii:" 1 { target { i?86-*-* x86_64-*-* } } } }
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// { dg-final { scan-assembler-times "_ZGVdM4vl2va32__ZN1BIiE3f26ILin1EEEiiPii:" 1 { target { i?86-*-* x86_64-*-* } } } }
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// { dg-final { scan-assembler-times "_ZGVdN4vl2va32__ZN1BIiE3f26ILin1EEEiiPii:" 1 { target { i?86-*-* x86_64-*-* } } } }
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// { dg-final { scan-assembler-times "_ZGVeM4vl2va32__ZN1BIiE3f26ILin1EEEiiPii:" 1 { target { i?86-*-* x86_64-*-* } } } }
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// { dg-final { scan-assembler-times "_ZGVeN4vl2va32__ZN1BIiE3f26ILin1EEEiiPii:" 1 { target { i?86-*-* x86_64-*-* } } } }
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int
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f27 (int x)
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@ -237,6 +245,8 @@ f30 (int x)
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// { dg-final { scan-assembler-times "_ZGVcN16v__Z3f30i:" 1 { target { i?86-*-* x86_64-*-* } } } }
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// { dg-final { scan-assembler-times "_ZGVdM16v__Z3f30i:" 1 { target { i?86-*-* x86_64-*-* } } } }
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// { dg-final { scan-assembler-times "_ZGVdN16v__Z3f30i:" 1 { target { i?86-*-* x86_64-*-* } } } }
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// { dg-final { scan-assembler-times "_ZGVeM16v__Z3f30i:" 1 { target { i?86-*-* x86_64-*-* } } } }
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// { dg-final { scan-assembler-times "_ZGVeN16v__Z3f30i:" 1 { target { i?86-*-* x86_64-*-* } } } }
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template <int N>
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struct C
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@ -19,6 +19,8 @@ int f1 (int a, int b, int c, int &d, int &e, int &f)
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// { dg-final { scan-assembler-times "_ZGVcN4vulLUR4__Z2f1iiiRiS_S_:" 1 { target { i?86-*-* x86_64-*-* } } } }
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// { dg-final { scan-assembler-times "_ZGVdM8vulLUR4__Z2f1iiiRiS_S_:" 1 { target { i?86-*-* x86_64-*-* } } } }
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// { dg-final { scan-assembler-times "_ZGVdN8vulLUR4__Z2f1iiiRiS_S_:" 1 { target { i?86-*-* x86_64-*-* } } } }
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// { dg-final { scan-assembler-times "_ZGVeM16vulLUR4__Z2f1iiiRiS_S_:" 1 { target { i?86-*-* x86_64-*-* } } } }
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// { dg-final { scan-assembler-times "_ZGVeN16vulLUR4__Z2f1iiiRiS_S_:" 1 { target { i?86-*-* x86_64-*-* } } } }
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#pragma omp declare simd uniform(b) linear(c, d) linear(uval(e)) linear(ref(f))
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int f2 (int a, int b, int c, int &d, int &e, int &f)
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@ -44,6 +46,8 @@ int f2 (int a, int b, int c, int &d, int &e, int &f)
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// { dg-final { scan-assembler-times "_ZGVcN4vulLUR4__Z2f2iiiRiS_S_:" 1 { target { i?86-*-* x86_64-*-* } } } }
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// { dg-final { scan-assembler-times "_ZGVdM8vulLUR4__Z2f2iiiRiS_S_:" 1 { target { i?86-*-* x86_64-*-* } } } }
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// { dg-final { scan-assembler-times "_ZGVdN8vulLUR4__Z2f2iiiRiS_S_:" 1 { target { i?86-*-* x86_64-*-* } } } }
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// { dg-final { scan-assembler-times "_ZGVeM16vulLUR4__Z2f2iiiRiS_S_:" 1 { target { i?86-*-* x86_64-*-* } } } }
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// { dg-final { scan-assembler-times "_ZGVeN16vulLUR4__Z2f2iiiRiS_S_:" 1 { target { i?86-*-* x86_64-*-* } } } }
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#pragma omp declare simd uniform(b) linear(c, d) linear(uval(e)) linear(ref(f))
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int f3 (const int a, const int b, const int c, const int &d, const int &e, const int &f)
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@ -57,6 +61,8 @@ int f3 (const int a, const int b, const int c, const int &d, const int &e, const
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// { dg-final { scan-assembler-times "_ZGVcN4vulLUR4__Z2f3iiiRKiS0_S0_:" 1 { target { i?86-*-* x86_64-*-* } } } }
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// { dg-final { scan-assembler-times "_ZGVdM8vulLUR4__Z2f3iiiRKiS0_S0_:" 1 { target { i?86-*-* x86_64-*-* } } } }
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// { dg-final { scan-assembler-times "_ZGVdN8vulLUR4__Z2f3iiiRKiS0_S0_:" 1 { target { i?86-*-* x86_64-*-* } } } }
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// { dg-final { scan-assembler-times "_ZGVeM16vulLUR4__Z2f3iiiRKiS0_S0_:" 1 { target { i?86-*-* x86_64-*-* } } } }
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// { dg-final { scan-assembler-times "_ZGVeN16vulLUR4__Z2f3iiiRKiS0_S0_:" 1 { target { i?86-*-* x86_64-*-* } } } }
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#pragma omp declare simd uniform(b) linear(c, d) linear(uval(e)) linear(ref(f))
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int f4 (const int a, const int b, const int c, const int &d, const int &e, const int &f)
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@ -76,3 +82,5 @@ int f4 (const int a, const int b, const int c, const int &d, const int &e, const
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// { dg-final { scan-assembler-times "_ZGVcN4vulLUR4__Z2f4iiiRKiS0_S0_:" 1 { target { i?86-*-* x86_64-*-* } } } }
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// { dg-final { scan-assembler-times "_ZGVdM8vulLUR4__Z2f4iiiRKiS0_S0_:" 1 { target { i?86-*-* x86_64-*-* } } } }
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// { dg-final { scan-assembler-times "_ZGVdN8vulLUR4__Z2f4iiiRKiS0_S0_:" 1 { target { i?86-*-* x86_64-*-* } } } }
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// { dg-final { scan-assembler-times "_ZGVeM16vulLUR4__Z2f4iiiRKiS0_S0_:" 1 { target { i?86-*-* x86_64-*-* } } } }
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// { dg-final { scan-assembler-times "_ZGVeN16vulLUR4__Z2f4iiiRKiS0_S0_:" 1 { target { i?86-*-* x86_64-*-* } } } }
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@ -11,6 +11,8 @@ f1 (int *p, int *q, short *s)
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// { dg-final { scan-assembler-times "_ZGVcN4l4ln4ln6__Z2f1PiS_Ps:" 1 { target { i?86-*-* x86_64-*-* } } } }
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// { dg-final { scan-assembler-times "_ZGVdM8l4ln4ln6__Z2f1PiS_Ps:" 1 { target { i?86-*-* x86_64-*-* } } } }
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// { dg-final { scan-assembler-times "_ZGVdN8l4ln4ln6__Z2f1PiS_Ps:" 1 { target { i?86-*-* x86_64-*-* } } } }
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// { dg-final { scan-assembler-times "_ZGVeM16l4ln4ln6__Z2f1PiS_Ps:" 1 { target { i?86-*-* x86_64-*-* } } } }
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// { dg-final { scan-assembler-times "_ZGVeN16l4ln4ln6__Z2f1PiS_Ps:" 1 { target { i?86-*-* x86_64-*-* } } } }
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#pragma omp declare simd linear(p:s) linear(q:t) uniform (s) linear(r:s) notinbranch simdlen(8) uniform(t)
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int
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@ -22,6 +24,7 @@ f2 (int *p, short *q, int s, int r, int &t)
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// { dg-final { scan-assembler-times "_ZGVbN8ls2ls4uls2u__Z2f2PiPsiiRi:" 1 { target { i?86-*-* x86_64-*-* } } } }
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// { dg-final { scan-assembler-times "_ZGVcN8ls2ls4uls2u__Z2f2PiPsiiRi:" 1 { target { i?86-*-* x86_64-*-* } } } }
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// { dg-final { scan-assembler-times "_ZGVdN8ls2ls4uls2u__Z2f2PiPsiiRi:" 1 { target { i?86-*-* x86_64-*-* } } } }
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// { dg-final { scan-assembler-times "_ZGVeN8ls2ls4uls2u__Z2f2PiPsiiRi:" 1 { target { i?86-*-* x86_64-*-* } } } }
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#pragma omp declare simd linear(ref(p):s) linear(val(q):t) uniform (s) linear(uval(r):s) notinbranch simdlen(8) uniform(t)
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int
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@ -33,3 +36,4 @@ f3 (int &p, short &q, int s, int &r, int &t)
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// { dg-final { scan-assembler-times "_ZGVbN8Rs2Ls4uUs2u__Z2f3RiRsiS_S_:" 1 { target { i?86-*-* x86_64-*-* } } } }
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// { dg-final { scan-assembler-times "_ZGVcN8Rs2Ls4uUs2u__Z2f3RiRsiS_S_:" 1 { target { i?86-*-* x86_64-*-* } } } }
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// { dg-final { scan-assembler-times "_ZGVdN8Rs2Ls4uUs2u__Z2f3RiRsiS_S_:" 1 { target { i?86-*-* x86_64-*-* } } } }
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// { dg-final { scan-assembler-times "_ZGVeN8Rs2Ls4uUs2u__Z2f3RiRsiS_S_:" 1 { target { i?86-*-* x86_64-*-* } } } }
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@ -19,6 +19,8 @@ int f2 (int a, int *b, int c)
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/* { dg-final { scan-assembler-times "_ZGVcN8uva32l4_f2:" 1 { target { i?86-*-* x86_64-*-* } } } } */
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/* { dg-final { scan-assembler-times "_ZGVdM8uva32l4_f2:" 1 { target { i?86-*-* x86_64-*-* } } } } */
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/* { dg-final { scan-assembler-times "_ZGVdN8uva32l4_f2:" 1 { target { i?86-*-* x86_64-*-* } } } } */
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/* { dg-final { scan-assembler-times "_ZGVeM8uva32l4_f2:" 1 { target { i?86-*-* x86_64-*-* } } } } */
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/* { dg-final { scan-assembler-times "_ZGVeN8uva32l4_f2:" 1 { target { i?86-*-* x86_64-*-* } } } } */
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#pragma omp declare simd uniform (a) aligned (b : 8 * sizeof (long long)) linear (c : 4) simdlen (8)
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__extension__
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@ -53,6 +55,8 @@ f7 (int x)
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/* { dg-final { scan-assembler-times "_ZGVcN16v_f7:" 1 { target { i?86-*-* x86_64-*-* } } } } */
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/* { dg-final { scan-assembler-times "_ZGVdM16v_f7:" 1 { target { i?86-*-* x86_64-*-* } } } } */
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/* { dg-final { scan-assembler-times "_ZGVdN16v_f7:" 1 { target { i?86-*-* x86_64-*-* } } } } */
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/* { dg-final { scan-assembler-times "_ZGVeM16v_f7:" 1 { target { i?86-*-* x86_64-*-* } } } } */
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/* { dg-final { scan-assembler-times "_ZGVeN16v_f7:" 1 { target { i?86-*-* x86_64-*-* } } } } */
|
||||
|
||||
int
|
||||
f9 (int x)
|
||||
@ -82,6 +86,8 @@ f13 (int c; int *b; int a; int a, int *b, int c)
|
||||
/* { dg-final { scan-assembler-times "_ZGVcN8uva32l4_f13:" 1 { target { i?86-*-* x86_64-*-* } } } } */
|
||||
/* { dg-final { scan-assembler-times "_ZGVdM8uva32l4_f13:" 1 { target { i?86-*-* x86_64-*-* } } } } */
|
||||
/* { dg-final { scan-assembler-times "_ZGVdN8uva32l4_f13:" 1 { target { i?86-*-* x86_64-*-* } } } } */
|
||||
/* { dg-final { scan-assembler-times "_ZGVeM8uva32l4_f13:" 1 { target { i?86-*-* x86_64-*-* } } } } */
|
||||
/* { dg-final { scan-assembler-times "_ZGVeN8uva32l4_f13:" 1 { target { i?86-*-* x86_64-*-* } } } } */
|
||||
|
||||
#pragma omp declare simd uniform (a) aligned (b : 8 * sizeof (int)) linear (c : 4) simdlen (8)
|
||||
int
|
||||
@ -98,6 +104,8 @@ f14 (a, b, c)
|
||||
/* { dg-final { scan-assembler-times "_ZGVcN8uva32l4_f14:" 1 { target { i?86-*-* x86_64-*-* } } } } */
|
||||
/* { dg-final { scan-assembler-times "_ZGVdM8uva32l4_f14:" 1 { target { i?86-*-* x86_64-*-* } } } } */
|
||||
/* { dg-final { scan-assembler-times "_ZGVdN8uva32l4_f14:" 1 { target { i?86-*-* x86_64-*-* } } } } */
|
||||
/* { dg-final { scan-assembler-times "_ZGVeM8uva32l4_f14:" 1 { target { i?86-*-* x86_64-*-* } } } } */
|
||||
/* { dg-final { scan-assembler-times "_ZGVeN8uva32l4_f14:" 1 { target { i?86-*-* x86_64-*-* } } } } */
|
||||
|
||||
#pragma omp declare simd uniform (a) aligned (b : 8 * sizeof (int)) linear (c : 4) simdlen (8)
|
||||
int
|
||||
@ -112,6 +120,8 @@ f15 (int a, int *b, int c)
|
||||
/* { dg-final { scan-assembler-times "_ZGVcN8uva32l4_f15:" 1 { target { i?86-*-* x86_64-*-* } } } } */
|
||||
/* { dg-final { scan-assembler-times "_ZGVdM8uva32l4_f15:" 1 { target { i?86-*-* x86_64-*-* } } } } */
|
||||
/* { dg-final { scan-assembler-times "_ZGVdN8uva32l4_f15:" 1 { target { i?86-*-* x86_64-*-* } } } } */
|
||||
/* { dg-final { scan-assembler-times "_ZGVeM8uva32l4_f15:" 1 { target { i?86-*-* x86_64-*-* } } } } */
|
||||
/* { dg-final { scan-assembler-times "_ZGVeN8uva32l4_f15:" 1 { target { i?86-*-* x86_64-*-* } } } } */
|
||||
|
||||
#pragma omp declare simd uniform (d) aligned (e : 8 * sizeof (int)) linear (f : 4) simdlen (8)
|
||||
int f15 (int d, int *e, int f);
|
||||
@ -131,12 +141,16 @@ int f17 (int g, long *h)
|
||||
/* { dg-final { scan-assembler-times "_ZGVcN4l20va8_f17:" 1 { target { { i?86-*-* x86_64-*-* } && lp64 } } } } */
|
||||
/* { dg-final { scan-assembler-times "_ZGVdM4l20va8_f17:" 1 { target { { i?86-*-* x86_64-*-* } && lp64 } } } } */
|
||||
/* { dg-final { scan-assembler-times "_ZGVdN4l20va8_f17:" 1 { target { { i?86-*-* x86_64-*-* } && lp64 } } } } */
|
||||
/* { dg-final { scan-assembler-times "_ZGVeM4l20va8_f17:" 1 { target { { i?86-*-* x86_64-*-* } && lp64 } } } } */
|
||||
/* { dg-final { scan-assembler-times "_ZGVeN4l20va8_f17:" 1 { target { { i?86-*-* x86_64-*-* } && lp64 } } } } */
|
||||
/* { dg-final { scan-assembler-times "_ZGVbM4l12va4_f17:" 1 { target { { i?86-*-* x86_64-*-* } && ilp32 } } } } */
|
||||
/* { dg-final { scan-assembler-times "_ZGVbN4l12va4_f17:" 1 { target { { i?86-*-* x86_64-*-* } && ilp32 } } } } */
|
||||
/* { dg-final { scan-assembler-times "_ZGVcM4l12va4_f17:" 1 { target { { i?86-*-* x86_64-*-* } && ilp32 } } } } */
|
||||
/* { dg-final { scan-assembler-times "_ZGVcN4l12va4_f17:" 1 { target { { i?86-*-* x86_64-*-* } && ilp32 } } } } */
|
||||
/* { dg-final { scan-assembler-times "_ZGVdM4l12va4_f17:" 1 { target { { i?86-*-* x86_64-*-* } && ilp32 } } } } */
|
||||
/* { dg-final { scan-assembler-times "_ZGVdN4l12va4_f17:" 1 { target { { i?86-*-* x86_64-*-* } && ilp32 } } } } */
|
||||
/* { dg-final { scan-assembler-times "_ZGVeM4l12va4_f17:" 1 { target { { i?86-*-* x86_64-*-* } && ilp32 } } } } */
|
||||
/* { dg-final { scan-assembler-times "_ZGVeN4l12va4_f17:" 1 { target { { i?86-*-* x86_64-*-* } && ilp32 } } } } */
|
||||
|
||||
#pragma omp declare simd aligned (i : sizeof (*i)) linear (j : 2 * sizeof (i[0]) + sizeof (j)) simdlen (4)
|
||||
int
|
||||
@ -153,9 +167,13 @@ f18 (j, i)
|
||||
/* { dg-final { scan-assembler-times "_ZGVcN4l20va8_f18:" 1 { target { { i?86-*-* x86_64-*-* } && lp64 } } } } */
|
||||
/* { dg-final { scan-assembler-times "_ZGVdM4l20va8_f18:" 1 { target { { i?86-*-* x86_64-*-* } && lp64 } } } } */
|
||||
/* { dg-final { scan-assembler-times "_ZGVdN4l20va8_f18:" 1 { target { { i?86-*-* x86_64-*-* } && lp64 } } } } */
|
||||
/* { dg-final { scan-assembler-times "_ZGVeM4l20va8_f18:" 1 { target { { i?86-*-* x86_64-*-* } && lp64 } } } } */
|
||||
/* { dg-final { scan-assembler-times "_ZGVeN4l20va8_f18:" 1 { target { { i?86-*-* x86_64-*-* } && lp64 } } } } */
|
||||
/* { dg-final { scan-assembler-times "_ZGVbM4l12va4_f18:" 1 { target { { i?86-*-* x86_64-*-* } && ilp32 } } } } */
|
||||
/* { dg-final { scan-assembler-times "_ZGVbN4l12va4_f18:" 1 { target { { i?86-*-* x86_64-*-* } && ilp32 } } } } */
|
||||
/* { dg-final { scan-assembler-times "_ZGVcM4l12va4_f18:" 1 { target { { i?86-*-* x86_64-*-* } && ilp32 } } } } */
|
||||
/* { dg-final { scan-assembler-times "_ZGVcN4l12va4_f18:" 1 { target { { i?86-*-* x86_64-*-* } && ilp32 } } } } */
|
||||
/* { dg-final { scan-assembler-times "_ZGVdM4l12va4_f18:" 1 { target { { i?86-*-* x86_64-*-* } && ilp32 } } } } */
|
||||
/* { dg-final { scan-assembler-times "_ZGVdN4l12va4_f18:" 1 { target { { i?86-*-* x86_64-*-* } && ilp32 } } } } */
|
||||
/* { dg-final { scan-assembler-times "_ZGVeM4l12va4_f18:" 1 { target { { i?86-*-* x86_64-*-* } && ilp32 } } } } */
|
||||
/* { dg-final { scan-assembler-times "_ZGVeN4l12va4_f18:" 1 { target { { i?86-*-* x86_64-*-* } && ilp32 } } } } */
|
||||
|
||||
@ -11,6 +11,8 @@ f1 (int *p, int *q, short *s)
|
||||
/* { dg-final { scan-assembler-times "_ZGVcN4l4ln4ln6_f1:" 1 { target { i?86-*-* x86_64-*-* } } } } */
|
||||
/* { dg-final { scan-assembler-times "_ZGVdM8l4ln4ln6_f1:" 1 { target { i?86-*-* x86_64-*-* } } } } */
|
||||
/* { dg-final { scan-assembler-times "_ZGVdN8l4ln4ln6_f1:" 1 { target { i?86-*-* x86_64-*-* } } } } */
|
||||
/* { dg-final { scan-assembler-times "_ZGVeM16l4ln4ln6_f1:" 1 { target { i?86-*-* x86_64-*-* } } } } */
|
||||
/* { dg-final { scan-assembler-times "_ZGVeN16l4ln4ln6_f1:" 1 { target { i?86-*-* x86_64-*-* } } } } */
|
||||
|
||||
#pragma omp declare simd linear(p:s) linear(q:t) uniform (s) linear(r:s) notinbranch simdlen(8) uniform(t)
|
||||
int
|
||||
@ -22,3 +24,4 @@ f2 (int *p, short *q, int s, int r, int t)
|
||||
/* { dg-final { scan-assembler-times "_ZGVbN8ls2ls4uls2u_f2:" 1 { target { i?86-*-* x86_64-*-* } } } } */
|
||||
/* { dg-final { scan-assembler-times "_ZGVcN8ls2ls4uls2u_f2:" 1 { target { i?86-*-* x86_64-*-* } } } } */
|
||||
/* { dg-final { scan-assembler-times "_ZGVdN8ls2ls4uls2u_f2:" 1 { target { i?86-*-* x86_64-*-* } } } } */
|
||||
/* { dg-final { scan-assembler-times "_ZGVeN8ls2ls4uls2u_f2:" 1 { target { i?86-*-* x86_64-*-* } } } } */
|
||||
|
||||
@ -2603,7 +2603,7 @@ proc check_effective_target_vect_simd_clones { } {
|
||||
# avx2 clone. Only the right clone for the specified arch will be
|
||||
# chosen, but still we need to at least be able to assemble
|
||||
# avx2.
|
||||
if { [check_effective_target_avx2] } {
|
||||
if { [check_effective_target_avx512f] } {
|
||||
set et_vect_simd_clones_saved 1
|
||||
}
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user