store-merging: Avoid ICEs on roughly ~0ULL/8 sized stores [PR105094]
On the following testcase on 64-bit targets, store-merging sees a MEM_REF store from {} ctor with "negative" bitsize where bitoff + bitsize wraps around to very small end offset. This later confuses the code so that it allocates just a few bytes of memory but fills in huge amounts of it. Later on there is a param_store_merging_max_size size check but due to the wrap-around we pass that. The following patch punts on such large bitsizes. 2022-03-30 Jakub Jelinek <jakub@redhat.com> PR tree-optimization/105094 * gimple-ssa-store-merging.cc (mem_valid_for_store_merging): Punt if bitsize <= 0 rather than just == 0. * gcc.dg/pr105094.c: New test.
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@ -4940,7 +4940,7 @@ mem_valid_for_store_merging (tree mem, poly_uint64 *pbitsize,
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tree base_addr = get_inner_reference (mem, &bitsize, &bitpos, &offset, &mode,
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&unsignedp, &reversep, &volatilep);
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*pbitsize = bitsize;
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if (known_eq (bitsize, 0))
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if (known_le (bitsize, 0))
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return NULL_TREE;
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if (TREE_CODE (mem) == COMPONENT_REF
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@ -0,0 +1,13 @@
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/* PR tree-optimization/105094 */
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/* { dg-do compile } */
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/* { dg-options "-O2" } */
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struct S { short a; char b[~(__SIZE_TYPE__)0 / __CHAR_BIT__ - 1]; };
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void bar (struct S *);
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void
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foo (void)
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{
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struct S s = { 5 };
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bar (&s);
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}
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