target.h (struct gcc_target): Update prototypes of needs_block_p and gen_spec_check.
2008-10-14 Andrey Belevantsev <abel@ispras.ru>
Dmitry Melnik <dm@ispras.ru>
Dmitry Zhurikhin <zhur@ispras.ru>
Alexander Monakov <amonakov@ispras.ru>
Maxim Kuvyrkov <maxim@codesourcery.com>
* target.h (struct gcc_target): Update prototypes of needs_block_p
and gen_spec_check.
* haifa-sched.c (create_check_block_twin): Update calls to the above.
* sel-sched.c (create_speculation_check): Likewise.
* doc/tm.texi: Provide documentation for new target hooks.
* config/ia64/ia64.c: Include sel-sched.h. Rewrite speculation hooks.
(ia64_gen_spec_insn): Removed.
(get_spec_check_gen_function, insn_can_be_in_speculative_p,
ia64_gen_spec_check): New static functions.
(ia64_alloc_sched_context, ia64_init_sched_context,
ia64_set_sched_context, ia64_clear_sched_context,
ia64_free_sched_context, ia64_get_insn_spec_ds,
ia64_get_insn_checked_ds, ia64_skip_rtx_p): Declare functions.
(ia64_needs_block_p): Change prototype.
(ia64_gen_check): Rename to ia64_gen_spec_check.
(ia64_adjust_cost): Rename to ia64_adjust_cost_2. Add new parameter
into declaration, add special memory dependencies handling.
(TARGET_SCHED_ALLOC_SCHED_CONTEXT, TARGET_SCHED_INIT_SCHED_CONTEXT,
TARGET_SCHED_SET_SCHED_CONTEXT, TARGET_SCHED_CLEAR_SCHED_CONTEXT,
TARGET_SCHED_FREE_SCHED_CONTEXT, TARGET_SCHED_GET_INSN_SPEC_DS,
TARGET_SCHED_GET_INSN_CHECKED_DS, TARGET_SCHED_SKIP_RTX_P):
Define new target hooks.
(TARGET_SCHED_GEN_CHECK): Rename to TARGET_SCHED_GEN_SPEC_CHECK.
(ia64_optimization_options): Turn on selective scheduling with -O3,
disable -fauto-inc-dec. Set mflag_sched_control_spec to true by default
with selective scheduling.
(ia64_override_options): Initialize align_loops and align_functions
to 32 and 64, respectively. Set global selective scheduling flags
according to target-dependent flags.
(rtx_needs_barrier): Support UNSPEC_LDS_A.
(group_barrier_needed): Use new mstop-bit-before-check flag.
Add heuristic.
(dfa_state_size): Make global.
(spec_check_no, max_uid): Remove.
(mem_ops_in_group, current_cycle): New variables.
(ia64_sched_init): Disable checks for !SCHED_GROUP_P after reload.
Initialize new variables.
(is_load_p, record_memory_reference): New functions.
(ia64_dfa_sched_reorder): Lower priority of loads when limit is
reached.
(ia64_variable_issue): Change use of current_sched_info to
sched_deps_info. Update comment. Note if a load or a store is issued.
(ia64_first_cycle_multipass_dfa_lookahead_guard_spec): Require a cycle
advance if maximal number of loads or stores was issued on current
cycle.
(scheduled_good_insn): New static helper function.
(ia64_dfa_new_cycle): Assert that last_scheduled_insn is set when
a group barrier is needed. Fix vertical spacing. Guard the code
doing state transition with last_scheduled_insn check.
Mark that a stop bit should be before current insn if there was a
cycle advance. Update current_cycle and mem_ops_in_group.
(ia64_h_i_d_extended): Change use of current_sched_info to
sched_deps_info. Reallocate stops_p by larger chunks.
(struct _ia64_sched_context): New structure.
(ia64_sched_context_t): New typedef.
(ia64_alloc_sched_context, ia64_init_sched_context,
ia64_set_sched_context, ia64_clear_sched_context,
ia64_free_sched_context): New static functions.
(gen_func_t): New typedef.
(get_spec_load_gen_function): New function.
(SPEC_GEN_EXTEND_OFFSET): Declare.
(ia64_set_sched_flags): Check common_sched_info instead of *flags.
(get_mode_no_for_insn): Change the condition that prevents use of
special hardware registers so it can now handle pseudos.
(get_spec_unspec_code): New function.
(ia64_skip_rtx_p, get_insn_spec_code, ia64_get_insn_spec_ds,
ia64_get_insn_checked_ds, ia64_gen_spec_load): New static functions.
(ia64_speculate_insn, ia64_needs_block_p): Support branchy checks
during selective scheduling.
(ia64_speculate_insn): Use ds_get_speculation_types when
determining whether we need to change the pattern.
(SPEC_GEN_LD_MAP, SPEC_GEN_CHECK_OFFSET): Declare.
(ia64_spec_check_src_p): Support new speculation/check codes.
(struct bundle_state): New field.
(issue_nops_and_insn): Initialize it.
(insert_bundle_state): Minimize mid-bundle stop bits.
(important_for_bundling_p): New function.
(get_next_important_insn): Use important_for_bundling_p.
(bundling): When shifting TImode from unimportant insns, ignore
also group barriers. Assert that best state is found before
the backward bundling pass. Print number of mid-bundle stop bits.
Minimize mid-bundle stop bits. Check correct calculation of
mid-bundle stop bits.
(ia64_sched_finish, final_emit_insn_group_barriers): Fix formatting.
(final_emit_insn_group_barriers): Emit stop bits before insns starting
a new cycle.
(sel2_run): New variable.
(ia64_reorg): When flag_selective_scheduling2 is set, run the selective
scheduling pass instead of schedule_ebbs.
* config/ia64/ia64.md (speculable1, speculable2): New attributes.
(UNSPEC_LDS_A): New UNSPEC.
(movqi_internal, movhi_internal, movsi_internal, movdi_internal,
movti_internal, movsf_internal, movdf_internal,
movxf_internal): Make visible. Add speculable* attributes.
(output_c_nc): New mode attribute.
(mov<mode>_speculative_a, zero_extend<mode>di2_speculative_a,
mov<mode>_nc, zero_extend<mode>di2_nc,
advanced_load_check_nc_<mode>): New insns.
(zero_extend*): Add speculable* attributes.
* config/ia64/ia64.opt (msched_fp_mem_deps_zero_cost): New option.
(msched-stop-bits-after-every-cycle): Likewise.
(msched-max-memory-insns,
msched-max-memory-insns-hard-limit): Likewise.
(msched-spec-verbose): Remove.
(msched-prefer-non-data-spec-insns,
msched-prefer-non-control-spec-insns, msched-count-spec-in-critical-path,
msel-sched-dont-check-control-spec): Use Target
Report Var instead of Common Report Var.
* config/ia64/itanium2.md: Remove incorrect bypass.
* config/ia64/t-ia64 (ia64.o): Add dependency on sel-sched.h.
Co-Authored-By: Alexander Monakov <amonakov@ispras.ru>
Co-Authored-By: Dmitry Melnik <dm@ispras.ru>
Co-Authored-By: Dmitry Zhurikhin <zhur@ispras.ru>
Co-Authored-By: Maxim Kuvyrkov <maxim@codesourcery.com>
From-SVN: r141108
This commit is contained in:
Andrey Belevantsev
Andrey Belevantsev
parent
847e63465e
commit
388092d5b4
122
gcc/ChangeLog
122
gcc/ChangeLog
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@ -1,3 +1,125 @@
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2008-10-14 Andrey Belevantsev <abel@ispras.ru>
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Dmitry Melnik <dm@ispras.ru>
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Dmitry Zhurikhin <zhur@ispras.ru>
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Alexander Monakov <amonakov@ispras.ru>
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Maxim Kuvyrkov <maxim@codesourcery.com>
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* target.h (struct gcc_target): Update prototypes of needs_block_p
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and gen_spec_check.
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* haifa-sched.c (create_check_block_twin): Update calls to the above.
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* sel-sched.c (create_speculation_check): Likewise.
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* doc/tm.texi: Provide documentation for new target hooks.
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* config/ia64/ia64.c: Include sel-sched.h. Rewrite speculation hooks.
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(ia64_gen_spec_insn): Removed.
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(get_spec_check_gen_function, insn_can_be_in_speculative_p,
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ia64_gen_spec_check): New static functions.
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(ia64_alloc_sched_context, ia64_init_sched_context,
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ia64_set_sched_context, ia64_clear_sched_context,
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ia64_free_sched_context, ia64_get_insn_spec_ds,
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ia64_get_insn_checked_ds, ia64_skip_rtx_p): Declare functions.
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(ia64_needs_block_p): Change prototype.
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(ia64_gen_check): Rename to ia64_gen_spec_check.
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(ia64_adjust_cost): Rename to ia64_adjust_cost_2. Add new parameter
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into declaration, add special memory dependencies handling.
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(TARGET_SCHED_ALLOC_SCHED_CONTEXT, TARGET_SCHED_INIT_SCHED_CONTEXT,
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TARGET_SCHED_SET_SCHED_CONTEXT, TARGET_SCHED_CLEAR_SCHED_CONTEXT,
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TARGET_SCHED_FREE_SCHED_CONTEXT, TARGET_SCHED_GET_INSN_SPEC_DS,
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TARGET_SCHED_GET_INSN_CHECKED_DS, TARGET_SCHED_SKIP_RTX_P):
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Define new target hooks.
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(TARGET_SCHED_GEN_CHECK): Rename to TARGET_SCHED_GEN_SPEC_CHECK.
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(ia64_optimization_options): Turn on selective scheduling with -O3,
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disable -fauto-inc-dec. Set mflag_sched_control_spec to true by default
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with selective scheduling.
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(ia64_override_options): Initialize align_loops and align_functions
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to 32 and 64, respectively. Set global selective scheduling flags
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according to target-dependent flags.
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(rtx_needs_barrier): Support UNSPEC_LDS_A.
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(group_barrier_needed): Use new mstop-bit-before-check flag.
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Add heuristic.
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(dfa_state_size): Make global.
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(spec_check_no, max_uid): Remove.
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(mem_ops_in_group, current_cycle): New variables.
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(ia64_sched_init): Disable checks for !SCHED_GROUP_P after reload.
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Initialize new variables.
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(is_load_p, record_memory_reference): New functions.
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(ia64_dfa_sched_reorder): Lower priority of loads when limit is
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reached.
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(ia64_variable_issue): Change use of current_sched_info to
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sched_deps_info. Update comment. Note if a load or a store is issued.
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(ia64_first_cycle_multipass_dfa_lookahead_guard_spec): Require a cycle
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advance if maximal number of loads or stores was issued on current
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cycle.
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(scheduled_good_insn): New static helper function.
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(ia64_dfa_new_cycle): Assert that last_scheduled_insn is set when
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a group barrier is needed. Fix vertical spacing. Guard the code
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doing state transition with last_scheduled_insn check.
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Mark that a stop bit should be before current insn if there was a
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cycle advance. Update current_cycle and mem_ops_in_group.
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(ia64_h_i_d_extended): Change use of current_sched_info to
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sched_deps_info. Reallocate stops_p by larger chunks.
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(struct _ia64_sched_context): New structure.
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(ia64_sched_context_t): New typedef.
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(ia64_alloc_sched_context, ia64_init_sched_context,
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ia64_set_sched_context, ia64_clear_sched_context,
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ia64_free_sched_context): New static functions.
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(gen_func_t): New typedef.
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(get_spec_load_gen_function): New function.
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(SPEC_GEN_EXTEND_OFFSET): Declare.
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(ia64_set_sched_flags): Check common_sched_info instead of *flags.
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(get_mode_no_for_insn): Change the condition that prevents use of
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special hardware registers so it can now handle pseudos.
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(get_spec_unspec_code): New function.
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(ia64_skip_rtx_p, get_insn_spec_code, ia64_get_insn_spec_ds,
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ia64_get_insn_checked_ds, ia64_gen_spec_load): New static functions.
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(ia64_speculate_insn, ia64_needs_block_p): Support branchy checks
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during selective scheduling.
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(ia64_speculate_insn): Use ds_get_speculation_types when
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determining whether we need to change the pattern.
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(SPEC_GEN_LD_MAP, SPEC_GEN_CHECK_OFFSET): Declare.
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(ia64_spec_check_src_p): Support new speculation/check codes.
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(struct bundle_state): New field.
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(issue_nops_and_insn): Initialize it.
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(insert_bundle_state): Minimize mid-bundle stop bits.
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(important_for_bundling_p): New function.
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(get_next_important_insn): Use important_for_bundling_p.
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(bundling): When shifting TImode from unimportant insns, ignore
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also group barriers. Assert that best state is found before
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the backward bundling pass. Print number of mid-bundle stop bits.
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Minimize mid-bundle stop bits. Check correct calculation of
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mid-bundle stop bits.
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(ia64_sched_finish, final_emit_insn_group_barriers): Fix formatting.
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(final_emit_insn_group_barriers): Emit stop bits before insns starting
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a new cycle.
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(sel2_run): New variable.
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(ia64_reorg): When flag_selective_scheduling2 is set, run the selective
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scheduling pass instead of schedule_ebbs.
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* config/ia64/ia64.md (speculable1, speculable2): New attributes.
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(UNSPEC_LDS_A): New UNSPEC.
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(movqi_internal, movhi_internal, movsi_internal, movdi_internal,
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movti_internal, movsf_internal, movdf_internal,
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movxf_internal): Make visible. Add speculable* attributes.
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(output_c_nc): New mode attribute.
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(mov<mode>_speculative_a, zero_extend<mode>di2_speculative_a,
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mov<mode>_nc, zero_extend<mode>di2_nc,
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advanced_load_check_nc_<mode>): New insns.
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(zero_extend*): Add speculable* attributes.
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* config/ia64/ia64.opt (msched_fp_mem_deps_zero_cost): New option.
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(msched-stop-bits-after-every-cycle): Likewise.
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(msched-max-memory-insns,
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msched-max-memory-insns-hard-limit): Likewise.
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(msched-spec-verbose): Remove.
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(msched-prefer-non-data-spec-insns,
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msched-prefer-non-control-spec-insns, msched-count-spec-in-critical-path,
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msel-sched-dont-check-control-spec): Use Target
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Report Var instead of Common Report Var.
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* config/ia64/itanium2.md: Remove incorrect bypass.
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* config/ia64/t-ia64 (ia64.o): Add dependency on sel-sched.h.
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2008-10-14 Jakub Jelinek <jakub@redhat.com>
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PR middle-end/37805
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File diff suppressed because it is too large
Load Diff
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@ -82,12 +82,15 @@
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(UNSPEC_VECT_EXTR 31)
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(UNSPEC_LDA 40)
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(UNSPEC_LDS 41)
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(UNSPEC_LDSA 42)
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(UNSPEC_LDCCLR 43)
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(UNSPEC_CHKACLR 45)
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(UNSPEC_CHKS 47)
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(UNSPEC_FR_RECIP_APPROX_RES 48)
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(UNSPEC_FR_SQRT_RECIP_APPROX_RES 49)
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(UNSPEC_LDS_A 42)
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(UNSPEC_LDSA 43)
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(UNSPEC_LDCCLR 44)
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(UNSPEC_LDCNC 45)
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(UNSPEC_CHKACLR 46)
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(UNSPEC_CHKANC 47)
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(UNSPEC_CHKS 48)
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(UNSPEC_FR_RECIP_APPROX_RES 49)
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(UNSPEC_FR_SQRT_RECIP_APPROX_RES 50)
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])
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(define_constants
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@ -185,6 +188,10 @@
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(define_attr "control_speculative" "no,yes" (const_string "no"))
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(define_attr "check_load" "no,yes" (const_string "no"))
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(define_attr "speculable1" "no,yes" (const_string "no"))
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(define_attr "speculable2" "no,yes" (const_string "no"))
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;; DFA descriptions of ia64 processors used for insn scheduling and
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;; bundling.
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@ -234,7 +241,9 @@
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ld1%O1 %0 = %1%P1
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st1%Q0 %0 = %1%P0
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mov %0 = %1"
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[(set_attr "itanium_class" "icmp,icmp,unknown,unknown,tbit,ialu,ld,st,ialu")])
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[(set_attr "itanium_class" "icmp,icmp,unknown,unknown,tbit,ialu,ld,st,ialu")
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(set_attr "speculable1" "yes")
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(set_attr "speculable2" "no, no, no, no, no, no, yes,no,no")])
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(define_split
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[(set (match_operand:BI 0 "register_operand" "")
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@ -273,7 +282,7 @@
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operands[1] = op1;
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})
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(define_insn "*movqi_internal"
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(define_insn "movqi_internal"
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[(set (match_operand:QI 0 "destination_operand" "=r,r,r, m, r,*f,*f")
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(match_operand:QI 1 "move_operand" "rO,J,m,rO,*f,rO,*f"))]
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"ia64_move_ok (operands[0], operands[1])"
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@ -285,7 +294,9 @@
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getf.sig %0 = %1
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setf.sig %0 = %r1
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mov %0 = %1"
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[(set_attr "itanium_class" "ialu,ialu,ld,st,frfr,tofr,fmisc")])
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[(set_attr "itanium_class" "ialu,ialu,ld,st,frfr,tofr,fmisc")
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(set_attr "speculable1" "yes")
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(set_attr "speculable2" "no, no, yes,no,no, no, no")])
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(define_expand "movhi"
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[(set (match_operand:HI 0 "general_operand" "")
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@ -298,7 +309,7 @@
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operands[1] = op1;
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})
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(define_insn "*movhi_internal"
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(define_insn "movhi_internal"
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[(set (match_operand:HI 0 "destination_operand" "=r,r,r, m, r,*f,*f")
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(match_operand:HI 1 "move_operand" "rO,J,m,rO,*f,rO,*f"))]
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"ia64_move_ok (operands[0], operands[1])"
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@ -310,7 +321,9 @@
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getf.sig %0 = %1
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setf.sig %0 = %r1
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mov %0 = %1"
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[(set_attr "itanium_class" "ialu,ialu,ld,st,frfr,tofr,fmisc")])
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[(set_attr "itanium_class" "ialu,ialu,ld,st,frfr,tofr,fmisc")
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(set_attr "speculable1" "yes")
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(set_attr "speculable2" "no, no, yes,no,no, no, no")])
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(define_expand "movsi"
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[(set (match_operand:SI 0 "general_operand" "")
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@ -323,7 +336,7 @@
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operands[1] = op1;
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})
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(define_insn "*movsi_internal"
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(define_insn "movsi_internal"
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[(set (match_operand:SI 0 "destination_operand" "=r,r,r,r,r, m, r,*f,*f, r,*d")
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(match_operand:SI 1 "move_operand" "rO,J,j,i,m,rO,*f,rO,*f,*d,rK"))]
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"ia64_move_ok (operands[0], operands[1])"
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@ -340,7 +353,9 @@
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mov %0 = %1
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mov %0 = %r1"
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;; frar_m, toar_m ??? why not frar_i and toar_i
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[(set_attr "itanium_class" "ialu,ialu,ialu,long_i,ld,st,frfr,tofr,fmisc,frar_m,toar_m")])
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[(set_attr "itanium_class" "ialu,ialu,ialu,long_i,ld,st,frfr,tofr,fmisc,frar_m,toar_m")
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(set_attr "speculable1" "yes")
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(set_attr "speculable2" "no, no, no, no, yes,no,no, no, no, no, no")])
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(define_expand "movdi"
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[(set (match_operand:DI 0 "general_operand" "")
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@ -353,7 +368,7 @@
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operands[1] = op1;
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})
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(define_insn "*movdi_internal"
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(define_insn "movdi_internal"
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[(set (match_operand:DI 0 "destination_operand"
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"=r,r,r,r,r, m, r,*f,*f,*f, Q, r,*b, r,*e, r,*d, r,*c")
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(match_operand:DI 1 "move_operand"
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@ -387,7 +402,9 @@
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return alt[which_alternative];
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}
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[(set_attr "itanium_class" "ialu,ialu,ialu,long_i,ld,st,frfr,tofr,fmisc,fld,stf,frbr,tobr,frar_i,toar_i,frar_m,toar_m,frpr,topr")])
|
||||
[(set_attr "itanium_class" "ialu,ialu,ialu,long_i,ld,st,frfr,tofr,fmisc,fld,stf,frbr,tobr,frar_i,toar_i,frar_m,toar_m,frpr,topr")
|
||||
(set_attr "speculable1" "yes")
|
||||
(set_attr "speculable2" "no, no, no, no, yes,no,no, no, no, yes,no, no, no, no, no, no, no, no, no")])
|
||||
|
||||
(define_mode_iterator MODE [BI QI HI SI DI SF DF XF TI])
|
||||
(define_mode_iterator MODE_FOR_EXTEND [QI HI SI])
|
||||
|
|
@ -472,6 +489,26 @@
|
|||
(XF "ldfe.c.clr %0 = %1%P1")
|
||||
(TI "ldfp8.c.clr %X0 = %1%P1")])
|
||||
|
||||
(define_mode_attr output_c_nc [
|
||||
(BI "ld1.c.nc%O1 %0 = %1%P1")
|
||||
(QI "ld1.c.nc%O1 %0 = %1%P1")
|
||||
(HI "ld2.c.nc%O1 %0 = %1%P1")
|
||||
(SI "ld4.c.nc%O1 %0 = %1%P1")
|
||||
(DI
|
||||
"@
|
||||
ld8.c.nc%O1 %0 = %1%P1
|
||||
ldf8.c.nc %0 = %1%P1")
|
||||
(SF
|
||||
"@
|
||||
ldfs.c.nc %0 = %1%P1
|
||||
ld4.c.nc%O1 %0 = %1%P1")
|
||||
(DF
|
||||
"@
|
||||
ldfd.c.nc %0 = %1%P1
|
||||
ld8.c.nc%O1 %0 = %1%P1")
|
||||
(XF "ldfe.c.nc %0 = %1%P1")
|
||||
(TI "ldfp8.c.nc %X0 = %1%P1")])
|
||||
|
||||
(define_mode_attr ld_reg_constr [(BI "=*r") (QI "=r") (HI "=r") (SI "=r") (DI "=r,*f") (SF "=f,*r") (DF "=f,*r") (XF "=f") (TI "=*x")])
|
||||
(define_mode_attr ldc_reg_constr [(BI "+*r") (QI "+r") (HI "+r") (SI "+r") (DI "+r,*f") (SF "+f,*r") (DF "+f,*r") (XF "+f") (TI "+*x")])
|
||||
(define_mode_attr chk_reg_constr [(BI "*r") (QI "r") (HI "r") (SI "r") (DI "r,*f") (SF "f,*r") (DF "f,*r") (XF "f") (TI "*x")])
|
||||
|
|
@ -530,6 +567,15 @@
|
|||
(set_attr "data_speculative" "<attr_yes>")
|
||||
(set_attr "control_speculative" "<attr_yes>")])
|
||||
|
||||
(define_insn "mov<mode>_speculative_a"
|
||||
[(set (match_operand:MODE 0 "<reg_pred_prefix>_register_operand" "<ld_reg_constr>")
|
||||
(unspec:MODE [(match_operand:MODE 1 "memory_operand" "<mem_constr>")] UNSPEC_LDS_A))]
|
||||
"ia64_move_ok (operands[0], operands[1])"
|
||||
"<output_sa>"
|
||||
[(set_attr "itanium_class" "<ld_class>")
|
||||
(set_attr "data_speculative" "<attr_yes>")
|
||||
(set_attr "control_speculative" "<attr_yes>")])
|
||||
|
||||
(define_insn "zero_extend<mode>di2_speculative_advanced"
|
||||
[(set (match_operand:DI 0 "gr_register_operand" "=r")
|
||||
(zero_extend:DI (unspec:MODE_FOR_EXTEND [(match_operand:MODE_FOR_EXTEND 1 "memory_operand" "<mem_constr>")] UNSPEC_LDSA)))]
|
||||
|
|
@ -539,6 +585,15 @@
|
|||
(set_attr "data_speculative" "<attr_yes>")
|
||||
(set_attr "control_speculative" "<attr_yes>")])
|
||||
|
||||
(define_insn "zero_extend<mode>di2_speculative_a"
|
||||
[(set (match_operand:DI 0 "gr_register_operand" "=r")
|
||||
(zero_extend:DI (unspec:MODE_FOR_EXTEND [(match_operand:MODE_FOR_EXTEND 1 "memory_operand" "<mem_constr>")] UNSPEC_LDS_A)))]
|
||||
""
|
||||
"<output_sa>"
|
||||
[(set_attr "itanium_class" "<ld_class>")
|
||||
(set_attr "data_speculative" "<attr_yes>")
|
||||
(set_attr "control_speculative" "<attr_yes>")])
|
||||
|
||||
(define_insn "mov<mode>_clr"
|
||||
[(set (match_operand:MODE 0 "<reg_pred_prefix>_register_operand" "<ldc_reg_constr>")
|
||||
(if_then_else:MODE (ne (unspec [(match_dup 0)] UNSPEC_LDCCLR) (const_int 0))
|
||||
|
|
@ -549,6 +604,16 @@
|
|||
[(set_attr "itanium_class" "<ld_class>")
|
||||
(set_attr "check_load" "<attr_yes>")])
|
||||
|
||||
(define_insn "mov<mode>_nc"
|
||||
[(set (match_operand:MODE 0 "<reg_pred_prefix>_register_operand" "<ldc_reg_constr>")
|
||||
(if_then_else:MODE (ne (unspec [(match_dup 0)] UNSPEC_LDCNC) (const_int 0))
|
||||
(match_operand:MODE 1 "memory_operand" "<mem_constr>")
|
||||
(match_dup 0)))]
|
||||
"ia64_move_ok (operands[0], operands[1])"
|
||||
"<output_c_nc>"
|
||||
[(set_attr "itanium_class" "<ld_class>")
|
||||
(set_attr "check_load" "<attr_yes>")])
|
||||
|
||||
(define_insn "zero_extend<mode>di2_clr"
|
||||
[(set (match_operand:DI 0 "gr_register_operand" "+r")
|
||||
(if_then_else:DI (ne (unspec [(match_dup 0)] UNSPEC_LDCCLR) (const_int 0))
|
||||
|
|
@ -559,6 +624,16 @@
|
|||
[(set_attr "itanium_class" "<ld_class>")
|
||||
(set_attr "check_load" "<attr_yes>")])
|
||||
|
||||
(define_insn "zero_extend<mode>di2_nc"
|
||||
[(set (match_operand:DI 0 "gr_register_operand" "+r")
|
||||
(if_then_else:DI (ne (unspec [(match_dup 0)] UNSPEC_LDCNC) (const_int 0))
|
||||
(zero_extend:DI (match_operand:MODE_FOR_EXTEND 1 "memory_operand" "<mem_constr>"))
|
||||
(match_dup 0)))]
|
||||
""
|
||||
"<output_c_nc>"
|
||||
[(set_attr "itanium_class" "<ld_class>")
|
||||
(set_attr "check_load" "<attr_yes>")])
|
||||
|
||||
(define_insn "advanced_load_check_clr_<mode>"
|
||||
[(set (pc)
|
||||
(if_then_else (ne (unspec [(match_operand:MODE 0 "<reg_pred_prefix>_register_operand" "<chk_reg_constr>")] UNSPEC_CHKACLR) (const_int 0))
|
||||
|
|
@ -568,6 +643,15 @@
|
|||
"chk.a.clr %0, %l1"
|
||||
[(set_attr "itanium_class" "<chka_class>")])
|
||||
|
||||
(define_insn "advanced_load_check_nc_<mode>"
|
||||
[(set (pc)
|
||||
(if_then_else (ne (unspec [(match_operand:MODE 0 "<reg_pred_prefix>_register_operand" "<chk_reg_constr>")] UNSPEC_CHKANC) (const_int 0))
|
||||
(pc)
|
||||
(label_ref (match_operand 1 "" ""))))]
|
||||
""
|
||||
"chk.a.clr %0, %l1"
|
||||
[(set_attr "itanium_class" "<chka_class>")])
|
||||
|
||||
(define_insn "speculation_check_<mode>"
|
||||
[(set (pc)
|
||||
(if_then_else (ne (unspec [(match_operand:MODE 0 "<reg_pred_prefix>_register_operand" "<chk_reg_constr>")] UNSPEC_CHKS) (const_int 0))
|
||||
|
|
@ -863,7 +947,7 @@
|
|||
operands[1] = op1;
|
||||
})
|
||||
|
||||
(define_insn_and_split "*movti_internal"
|
||||
(define_insn_and_split "movti_internal"
|
||||
[(set (match_operand:TI 0 "destination_operand" "=r, *fm,*x,*f, Q")
|
||||
(match_operand:TI 1 "general_operand" "r*fim,r, Q, *fOQ,*f"))]
|
||||
"ia64_move_ok (operands[0], operands[1])"
|
||||
|
|
@ -879,7 +963,9 @@
|
|||
ia64_split_tmode_move (operands);
|
||||
DONE;
|
||||
}
|
||||
[(set_attr "itanium_class" "unknown,unknown,fldp,unknown,unknown")])
|
||||
[(set_attr "itanium_class" "unknown,unknown,fldp,unknown,unknown")
|
||||
(set_attr "speculable1" "yes")
|
||||
(set_attr "speculable2" "no, no, yes, no, no")])
|
||||
|
||||
;; Floating Point Moves
|
||||
;;
|
||||
|
|
@ -897,7 +983,7 @@
|
|||
operands[1] = op1;
|
||||
})
|
||||
|
||||
(define_insn "*movsf_internal"
|
||||
(define_insn "movsf_internal"
|
||||
[(set (match_operand:SF 0 "destination_operand" "=f,f, Q,*r, f,*r,*r, m")
|
||||
(match_operand:SF 1 "general_operand" "fG,Q,fG,fG,*r,*r, m,*r"))]
|
||||
"ia64_move_ok (operands[0], operands[1])"
|
||||
|
|
@ -910,7 +996,9 @@
|
|||
mov %0 = %1
|
||||
ld4%O1 %0 = %1%P1
|
||||
st4%Q0 %0 = %1%P0"
|
||||
[(set_attr "itanium_class" "fmisc,fld,stf,frfr,tofr,ialu,ld,st")])
|
||||
[(set_attr "itanium_class" "fmisc,fld,stf,frfr,tofr,ialu,ld,st")
|
||||
(set_attr "speculable1" "yes")
|
||||
(set_attr "speculable2" "no, yes,no, no, no, no, yes,no")])
|
||||
|
||||
(define_expand "movdf"
|
||||
[(set (match_operand:DF 0 "general_operand" "")
|
||||
|
|
@ -923,7 +1011,7 @@
|
|||
operands[1] = op1;
|
||||
})
|
||||
|
||||
(define_insn "*movdf_internal"
|
||||
(define_insn "movdf_internal"
|
||||
[(set (match_operand:DF 0 "destination_operand" "=f,f, Q,*r, f,*r,*r, m")
|
||||
(match_operand:DF 1 "general_operand" "fG,Q,fG,fG,*r,*r, m,*r"))]
|
||||
"ia64_move_ok (operands[0], operands[1])"
|
||||
|
|
@ -936,7 +1024,9 @@
|
|||
mov %0 = %1
|
||||
ld8%O1 %0 = %1%P1
|
||||
st8%Q0 %0 = %1%P0"
|
||||
[(set_attr "itanium_class" "fmisc,fld,stf,frfr,tofr,ialu,ld,st")])
|
||||
[(set_attr "itanium_class" "fmisc,fld,stf,frfr,tofr,ialu,ld,st")
|
||||
(set_attr "speculable1" "yes")
|
||||
(set_attr "speculable2" "no, yes,no, no, no, no, yes,no")])
|
||||
|
||||
;; With no offsettable memory references, we've got to have a scratch
|
||||
;; around to play with the second word if the variable winds up in GRs.
|
||||
|
|
@ -951,7 +1041,7 @@
|
|||
|
||||
;; ??? There's no easy way to mind volatile acquire/release semantics.
|
||||
|
||||
(define_insn "*movxf_internal"
|
||||
(define_insn "movxf_internal"
|
||||
[(set (match_operand:XF 0 "destination_operand" "=f,f, m")
|
||||
(match_operand:XF 1 "general_operand" "fG,m,fG"))]
|
||||
"ia64_move_ok (operands[0], operands[1])"
|
||||
|
|
@ -959,7 +1049,9 @@
|
|||
mov %0 = %F1
|
||||
ldfe %0 = %1%P1
|
||||
stfe %0 = %F1%P0"
|
||||
[(set_attr "itanium_class" "fmisc,fld,stf")])
|
||||
[(set_attr "itanium_class" "fmisc,fld,stf")
|
||||
(set_attr "speculable1" "yes")
|
||||
(set_attr "speculable2" "no, yes,no")])
|
||||
|
||||
;; Same as for movxf, but for RFmode.
|
||||
(define_expand "movrf"
|
||||
|
|
@ -1049,7 +1141,9 @@
|
|||
"@
|
||||
zxt1 %0 = %1
|
||||
ld1%O1 %0 = %1%P1"
|
||||
[(set_attr "itanium_class" "xtd,ld")])
|
||||
[(set_attr "itanium_class" "xtd,ld")
|
||||
(set_attr "speculable1" "yes")
|
||||
(set_attr "speculable2" "no, yes")])
|
||||
|
||||
(define_insn "zero_extendhidi2"
|
||||
[(set (match_operand:DI 0 "gr_register_operand" "=r,r")
|
||||
|
|
@ -1058,7 +1152,9 @@
|
|||
"@
|
||||
zxt2 %0 = %1
|
||||
ld2%O1 %0 = %1%P1"
|
||||
[(set_attr "itanium_class" "xtd,ld")])
|
||||
[(set_attr "itanium_class" "xtd,ld")
|
||||
(set_attr "speculable1" "yes")
|
||||
(set_attr "speculable2" "no, yes")])
|
||||
|
||||
(define_insn "zero_extendsidi2"
|
||||
[(set (match_operand:DI 0 "grfr_register_operand" "=r,r,?f")
|
||||
|
|
@ -1069,7 +1165,9 @@
|
|||
addp4 %0 = %1, r0
|
||||
ld4%O1 %0 = %1%P1
|
||||
fmix.r %0 = f0, %1"
|
||||
[(set_attr "itanium_class" "ialu,ld,fmisc")])
|
||||
[(set_attr "itanium_class" "ialu,ld,fmisc")
|
||||
(set_attr "speculable1" "yes")
|
||||
(set_attr "speculable2" "no, yes,no")])
|
||||
|
||||
;; Convert between floating point types of different sizes.
|
||||
|
||||
|
|
|
|||
|
|
@ -105,7 +105,7 @@ Target Report Var(mflag_sched_ar_data_spec) Init(1)
|
|||
Use data speculation after reload
|
||||
|
||||
msched-control-spec
|
||||
Target Report Var(mflag_sched_control_spec) Init(0)
|
||||
Target Report Var(mflag_sched_control_spec) Init(2)
|
||||
Use control speculation
|
||||
|
||||
msched-br-in-data-spec
|
||||
|
|
@ -120,28 +120,44 @@ msched-in-control-spec
|
|||
Target Report Var(mflag_sched_in_control_spec) Init(1)
|
||||
Use in block control speculation
|
||||
|
||||
msched-ldc
|
||||
Target Report Var(mflag_sched_ldc) Init(1)
|
||||
msched-spec-ldc
|
||||
Target Report Var(mflag_sched_spec_ldc) Init(1)
|
||||
Use simple data speculation check
|
||||
|
||||
msched-control-ldc
|
||||
Target Report Var(mflag_control_ldc) Init(0)
|
||||
msched-spec-control-ldc
|
||||
Target Report Var(mflag_sched_spec_control_ldc) Init(0)
|
||||
Use simple data speculation check for control speculation
|
||||
|
||||
msched-spec-verbose
|
||||
Common Report Var(mflag_sched_spec_verbose) Init(0)
|
||||
Print information about speculative motions.
|
||||
|
||||
msched-prefer-non-data-spec-insns
|
||||
Common Report Var(mflag_sched_prefer_non_data_spec_insns) Init(0)
|
||||
Target Report Var(mflag_sched_prefer_non_data_spec_insns) Init(0)
|
||||
If set, data speculative instructions will be chosen for schedule only if there are no other choices at the moment
|
||||
|
||||
msched-prefer-non-control-spec-insns
|
||||
Common Report Var(mflag_sched_prefer_non_control_spec_insns) Init(0)
|
||||
Target Report Var(mflag_sched_prefer_non_control_spec_insns) Init(0)
|
||||
If set, control speculative instructions will be chosen for schedule only if there are no other choices at the moment
|
||||
|
||||
msched-count-spec-in-critical-path
|
||||
Common Report Var(mflag_sched_count_spec_in_critical_path) Init(0)
|
||||
Target Report Var(mflag_sched_count_spec_in_critical_path) Init(0)
|
||||
Count speculative dependencies while calculating priority of instructions
|
||||
|
||||
msched-stop-bits-after-every-cycle
|
||||
Target Report Var(mflag_sched_stop_bits_after_every_cycle) Init(1)
|
||||
Place a stop bit after every cycle when scheduling
|
||||
|
||||
msched-fp-mem-deps-zero-cost
|
||||
Target Report Var(mflag_sched_fp_mem_deps_zero_cost) Init(0)
|
||||
Assume that floating-point stores and loads are not likely to cause conflict when placed into one instruction group
|
||||
|
||||
msched-max-memory-insns=
|
||||
Target RejectNegative Joined UInteger Var(ia64_max_memory_insns) Init(1)
|
||||
Soft limit on number of memory insns per instruction group, giving lower priority to subsequent memory insns attempting to schedule in the same insn group. Frequently useful to prevent cache bank conflicts. Default value is 1
|
||||
|
||||
msched-max-memory-insns-hard-limit
|
||||
Target Report Var(mflag_sched_mem_insns_hard_limit) Init(0)
|
||||
Disallow more than `msched-max-memory-insns' in instruction group. Otherwise, limit is `soft' (prefer non-memory operations when limit is reached)
|
||||
|
||||
msel-sched-dont-check-control-spec
|
||||
Target Report Var(mflag_sel_sched_dont_check_control_spec) Init(0)
|
||||
Don't generate checks for control speculation in selective scheduling
|
||||
|
||||
; This comment is to ensure we retain the blank line above.
|
||||
|
|
|
|||
|
|
@ -1072,14 +1072,13 @@
|
|||
(define_bypass 3 "2_ialu" "2_mmalua,2_mmmul,2_mmshf")
|
||||
(define_bypass 3 "2_mmalua,2_mmmul,2_mmshf" "2_ialu,2_ilog,2_ishf,2_st,2_ld,2_ldc")
|
||||
(define_bypass 6 "2_tofr" "2_frfr,2_stf")
|
||||
(define_bypass 7 "2_fmac" "2_frfr,2_stf")
|
||||
|
||||
;; We don't use here fcmp because scall may be predicated.
|
||||
(define_bypass 0 "2_fcvtfx,2_fld,2_flda,2_fldc,2_fmac,2_fmisc,2_frar_i,2_frar_m,\
|
||||
2_frbr,2_frfr,2_frpr,2_ialu,2_ilog,2_ishf,2_ld,2_ldc,2_long_i,\
|
||||
2_mmalua,2_mmmul,2_mmshf,2_mmshfi,2_toar_m,2_tofr,\
|
||||
2_mmalua,2_mmmul,2_mmshf,2_mmshfi,2_toar_m,2_tobr,2_tofr,\
|
||||
2_xmpy,2_xtd"
|
||||
"2_scall")
|
||||
"2_br,2_scall")
|
||||
|
||||
(define_bypass 0 "2_unknown,2_ignore,2_stop_bit,2_br,2_fcmp,2_fcvtfx,2_fld,2_flda,2_fldc,\
|
||||
2_fmac,2_fmisc,2_frar_i,2_frar_m,2_frbr,2_frfr,2_frpr,\
|
||||
|
|
|
|||
|
|
@ -33,4 +33,4 @@ ia64-c.o: $(srcdir)/config/ia64/ia64-c.c $(CONFIG_H) $(SYSTEM_H) \
|
|||
# genattrtab generates very long string literals.
|
||||
insn-attrtab.o-warn = -Wno-error
|
||||
|
||||
ia64.o: debug.h $(PARAMS_H)
|
||||
ia64.o: debug.h $(PARAMS_H) sel-sched.h
|
||||
|
|
|
|||
|
|
@ -6390,6 +6390,29 @@ Deallocate internal data in target scheduling context pointed to by @var{tc}.
|
|||
Deallocate a store for target scheduling context pointed to by @var{tc}.
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Target Hook} void * TARGET_SCHED_ALLOC_SCHED_CONTEXT (void)
|
||||
Return a pointer to a store large enough to hold target scheduling context.
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Target Hook} void TARGET_SCHED_INIT_SCHED_CONTEXT (void *@var{tc}, bool @var{clean_p})
|
||||
Initialize store pointed to by @var{tc} to hold target scheduling context.
|
||||
It @var{clean_p} is true then initialize @var{tc} as if scheduler is at the
|
||||
beginning of the block. Overwise, make a copy of the current context in
|
||||
@var{tc}.
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Target Hook} void TARGET_SCHED_SET_SCHED_CONTEXT (void *@var{tc})
|
||||
Copy target scheduling context pointer to by @var{tc} to the current context.
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Target Hook} void TARGET_SCHED_CLEAR_SCHED_CONTEXT (void *@var{tc})
|
||||
Deallocate internal data in target scheduling context pointed to by @var{tc}.
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Target Hook} void TARGET_SCHED_FREE_SCHED_CONTEXT (void *@var{tc})
|
||||
Deallocate a store for target scheduling context pointed to by @var{tc}.
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Target Hook} int TARGET_SCHED_SPECULATE_INSN (rtx @var{insn}, int @var{request}, rtx *@var{new_pat})
|
||||
This hook is called by the insn scheduler when @var{insn} has only
|
||||
speculative dependencies and therefore can be scheduled speculatively.
|
||||
|
|
|
|||
|
|
@ -3949,7 +3949,7 @@ create_check_block_twin (rtx insn, bool mutate_p)
|
|||
todo_spec &= SPECULATIVE;
|
||||
|
||||
/* Create recovery block. */
|
||||
if (mutate_p || targetm.sched.needs_block_p (insn))
|
||||
if (mutate_p || targetm.sched.needs_block_p (todo_spec))
|
||||
{
|
||||
rec = sched_create_recovery_block (NULL);
|
||||
label = BB_HEAD (rec);
|
||||
|
|
@ -3961,7 +3961,7 @@ create_check_block_twin (rtx insn, bool mutate_p)
|
|||
}
|
||||
|
||||
/* Emit CHECK. */
|
||||
check = targetm.sched.gen_spec_check (insn, label, mutate_p);
|
||||
check = targetm.sched.gen_spec_check (insn, label, todo_spec);
|
||||
|
||||
if (rec != EXIT_BLOCK_PTR)
|
||||
{
|
||||
|
|
|
|||
|
|
@ -1817,7 +1817,7 @@ create_speculation_check (expr_t c_expr, ds_t check_ds, insn_t orig_insn)
|
|||
|
||||
/* Create a recovery block if target is going to emit branchy check, or if
|
||||
ORIG_INSN was speculative already. */
|
||||
if (targetm.sched.needs_block_p (EXPR_INSN_RTX (c_expr))
|
||||
if (targetm.sched.needs_block_p (check_ds)
|
||||
|| EXPR_SPEC_DONE_DS (INSN_EXPR (orig_insn)) != 0)
|
||||
{
|
||||
recovery_block = sel_create_recovery_block (orig_insn);
|
||||
|
|
|
|||
|
|
@ -397,7 +397,7 @@ struct gcc_target
|
|||
/* The following member value is a pointer to a function called
|
||||
by the insn scheduler. It should return true if the check instruction
|
||||
passed as the parameter needs a recovery block. */
|
||||
bool (* needs_block_p) (const_rtx);
|
||||
bool (* needs_block_p) (int);
|
||||
|
||||
/* The following member value is a pointer to a function called
|
||||
by the insn scheduler. It should return a pattern for the check
|
||||
|
|
@ -407,7 +407,7 @@ struct gcc_target
|
|||
simple check). If the mutation of the check is requested (e.g. from
|
||||
ld.c to chk.a), the third parameter is true - in this case the first
|
||||
parameter is the previous check. */
|
||||
rtx (* gen_spec_check) (rtx, rtx, bool);
|
||||
rtx (* gen_spec_check) (rtx, rtx, int);
|
||||
|
||||
/* The following member value is a pointer to a function controlling
|
||||
what insns from the ready insn queue will be considered for the
|
||||
|
|
|
|||
Loading…
Reference in New Issue