Enable bitwise operation for type mask.
Enable operator or/xor/and/andn/not for mask register, kxnor is not enabled since there's no corresponding instruction for general registers. gcc/ PR target/88808 * config/i386/i386.c (ix86_preferred_reload_class): Allow QImode data go into mask registers. * config/i386/i386.md: (*movhi_internal): Adjust constraints for mask registers. (*movqi_internal): Ditto. (*anddi_1): Support mask register operations (*and<mode>_1): Ditto. (*andqi_1): Ditto. (*andn<mode>_1): Ditto. (*<code><mode>_1): Ditto. (*<code>qi_1): Ditto. (*one_cmpl<mode>2_1): Ditto. (*one_cmplsi2_1_zext): Ditto. (*one_cmplqi2_1): Ditto. (define_peephole2): Move constant 0/-1 directly into mask registers. * config/i386/predicates.md (mask_reg_operand): New predicate. * config/i386/sse.md (define_split): Add post-reload splitters that would convert "generic" patterns to mask patterns. (*knotsi_1_zext): New define_insn. gcc/testsuite/ * gcc.target/i386/bitwise_mask_op-1.c: New test. * gcc.target/i386/bitwise_mask_op-2.c: New test. * gcc.target/i386/bitwise_mask_op-3.c: New test. * gcc.target/i386/avx512bw-pr88465.c: New testcase. * gcc.target/i386/avx512bw-kunpckwd-1.c: Adjust testcase. * gcc.target/i386/avx512bw-kunpckwd-3.c: Ditto. * gcc.target/i386/avx512dq-kmovb-5.c: Ditto. * gcc.target/i386/avx512f-kmovw-5.c: Ditto. * gcc.target/i386/pr55342.c: Ditto.
This commit is contained in:
liuhongt
parent
16516644d8
commit
388cb292a9
@ -18378,13 +18378,15 @@ ix86_preferred_reload_class (rtx x, reg_class_t regclass)
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return INTEGER_CLASS_P (regclass) ? regclass : NO_REGS;
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/* QImode constants are easy to load, but non-constant QImode data
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must go into Q_REGS. */
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must go into Q_REGS or ALL_MASK_REGS. */
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if (GET_MODE (x) == QImode && !CONSTANT_P (x))
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{
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if (Q_CLASS_P (regclass))
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return regclass;
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else if (reg_class_subset_p (Q_REGS, regclass))
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return Q_REGS;
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else if (MASK_CLASS_P (regclass))
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return regclass;
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else
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return NO_REGS;
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}
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@ -2403,8 +2403,8 @@
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(symbol_ref "true")))])
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(define_insn "*movhi_internal"
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[(set (match_operand:HI 0 "nonimmediate_operand" "=r,r ,r ,m ,k,k ,r,m,k")
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(match_operand:HI 1 "general_operand" "r ,rn,rm,rn,r,km,k,k,CBC"))]
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[(set (match_operand:HI 0 "nonimmediate_operand" "=r,r ,r ,m ,*k,*k ,*r,*m,*k")
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(match_operand:HI 1 "general_operand" "r ,rn,rm,rn,*r,*km,*k,*k,CBC"))]
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"!(MEM_P (operands[0]) && MEM_P (operands[1]))"
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{
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switch (get_attr_type (insn))
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@ -2491,9 +2491,9 @@
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(define_insn "*movqi_internal"
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[(set (match_operand:QI 0 "nonimmediate_operand"
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"=Q,R,r,q,q,r,r ,?r,m ,k,k,r,m,k,k,k")
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"=Q,R,r,q,q,r,r ,?r,m ,*k,*k,*r,*m,*k,*k,*k")
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(match_operand:QI 1 "general_operand"
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"Q ,R,r,n,m,q,rn, m,qn,r,k,k,k,m,C,BC"))]
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"Q ,R,r,n,m,q,rn, m,qn,*r,*k,*k,*k,*m,C,BC"))]
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"!(MEM_P (operands[0]) && MEM_P (operands[1]))"
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{
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char buf[128];
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@ -2624,6 +2624,19 @@
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]
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(const_string "QI")))])
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/* Reload dislikes loading 0/-1 directly into mask registers.
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Try to tidy things up here. */
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(define_peephole2
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[(set (match_operand:SWI 0 "general_reg_operand")
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(match_operand:SWI 1 "immediate_operand"))
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(set (match_operand:SWI 2 "mask_reg_operand")
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(match_dup 0))]
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"peep2_reg_dead_p (2, operands[0])
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&& (const0_operand (operands[1], <MODE>mode)
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|| (constm1_operand (operands[1], <MODE>mode)
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&& (<MODE_SIZE> > 1 || TARGET_AVX512DQ)))"
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[(set (match_dup 2) (match_dup 1))])
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;; Stores and loads of ax to arbitrary constant address.
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;; We fake an second form of instruction to force reload to load address
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;; into register when rax is not available
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@ -9044,19 +9057,21 @@
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})
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(define_insn "*anddi_1"
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[(set (match_operand:DI 0 "nonimmediate_operand" "=r,rm,r,r")
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[(set (match_operand:DI 0 "nonimmediate_operand" "=r,rm,r,r,k")
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(and:DI
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(match_operand:DI 1 "nonimmediate_operand" "%0,0,0,qm")
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(match_operand:DI 2 "x86_64_szext_general_operand" "Z,re,m,L")))
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(match_operand:DI 1 "nonimmediate_operand" "%0,0,0,qm,k")
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(match_operand:DI 2 "x86_64_szext_general_operand" "Z,re,m,L,k")))
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(clobber (reg:CC FLAGS_REG))]
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"TARGET_64BIT && ix86_binary_operator_ok (AND, DImode, operands)"
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"@
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and{l}\t{%k2, %k0|%k0, %k2}
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and{q}\t{%2, %0|%0, %2}
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and{q}\t{%2, %0|%0, %2}
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#
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#"
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[(set_attr "type" "alu,alu,alu,imovx")
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(set_attr "length_immediate" "*,*,*,0")
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[(set_attr "isa" "x64,x64,x64,x64,avx512bw")
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(set_attr "type" "alu,alu,alu,imovx,msklog")
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(set_attr "length_immediate" "*,*,*,0,*")
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(set (attr "prefix_rex")
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(if_then_else
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(and (eq_attr "type" "imovx")
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@ -9064,7 +9079,7 @@
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(match_operand 1 "ext_QIreg_operand")))
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(const_string "1")
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(const_string "*")))
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(set_attr "mode" "SI,DI,DI,SI")])
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(set_attr "mode" "SI,DI,DI,SI,DI")])
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(define_insn_and_split "*anddi_1_btr"
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[(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
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@ -9130,17 +9145,25 @@
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(set_attr "mode" "SI")])
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(define_insn "*and<mode>_1"
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[(set (match_operand:SWI24 0 "nonimmediate_operand" "=rm,r,Ya")
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(and:SWI24 (match_operand:SWI24 1 "nonimmediate_operand" "%0,0,qm")
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(match_operand:SWI24 2 "<general_operand>" "r<i>,m,L")))
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[(set (match_operand:SWI24 0 "nonimmediate_operand" "=rm,r,Ya,k")
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(and:SWI24 (match_operand:SWI24 1 "nonimmediate_operand" "%0,0,qm,k")
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(match_operand:SWI24 2 "<general_operand>" "r<i>,m,L,k")))
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(clobber (reg:CC FLAGS_REG))]
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"ix86_binary_operator_ok (AND, <MODE>mode, operands)"
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"@
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and{<imodesuffix>}\t{%2, %0|%0, %2}
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and{<imodesuffix>}\t{%2, %0|%0, %2}
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#
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#"
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[(set_attr "type" "alu,alu,imovx")
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(set_attr "length_immediate" "*,*,0")
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[(set (attr "isa")
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(cond [(eq_attr "alternative" "3")
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(if_then_else (eq_attr "mode" "SI")
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(const_string "avx512bw")
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(const_string "avx512f"))
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]
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(const_string "*")))
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(set_attr "type" "alu,alu,imovx,msklog")
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(set_attr "length_immediate" "*,*,0,*")
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(set (attr "prefix_rex")
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(if_then_else
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(and (eq_attr "type" "imovx")
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@ -9148,20 +9171,28 @@
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(match_operand 1 "ext_QIreg_operand")))
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(const_string "1")
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(const_string "*")))
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(set_attr "mode" "<MODE>,<MODE>,SI")])
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(set_attr "mode" "<MODE>,<MODE>,SI,<MODE>")])
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(define_insn "*andqi_1"
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[(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q,r")
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(and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
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(match_operand:QI 2 "general_operand" "qn,m,rn")))
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[(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q,r,k")
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(and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0,k")
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(match_operand:QI 2 "general_operand" "qn,m,rn,k")))
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(clobber (reg:CC FLAGS_REG))]
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"ix86_binary_operator_ok (AND, QImode, operands)"
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"@
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and{b}\t{%2, %0|%0, %2}
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and{b}\t{%2, %0|%0, %2}
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and{l}\t{%k2, %k0|%k0, %k2}"
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[(set_attr "type" "alu")
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(set_attr "mode" "QI,QI,SI")
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and{l}\t{%k2, %k0|%k0, %k2}
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#"
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[(set_attr "type" "alu,alu,alu,msklog")
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(set (attr "mode")
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(cond [(eq_attr "alternative" "2")
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(const_string "SI")
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(and (eq_attr "alternative" "3")
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(match_test "!TARGET_AVX512DQ"))
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(const_string "HI")
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]
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(const_string "QI")))
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;; Potential partial reg stall on alternative 2.
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(set (attr "preferred_for_speed")
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(cond [(eq_attr "alternative" "2")
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@ -9539,28 +9570,42 @@
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})
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(define_insn "*andn<mode>_1"
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[(set (match_operand:SWI48 0 "register_operand" "=r,r")
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[(set (match_operand:SWI48 0 "register_operand" "=r,r,k")
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(and:SWI48
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(not:SWI48 (match_operand:SWI48 1 "register_operand" "r,r"))
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(match_operand:SWI48 2 "nonimmediate_operand" "r,m")))
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(not:SWI48 (match_operand:SWI48 1 "register_operand" "r,r,k"))
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(match_operand:SWI48 2 "nonimmediate_operand" "r,m,k")))
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(clobber (reg:CC FLAGS_REG))]
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"TARGET_BMI"
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"andn\t{%2, %1, %0|%0, %1, %2}"
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[(set_attr "type" "bitmanip")
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(set_attr "btver2_decode" "direct, double")
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"TARGET_BMI || TARGET_AVX512BW"
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"@
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andn\t{%2, %1, %0|%0, %1, %2}
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andn\t{%2, %1, %0|%0, %1, %2}
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#"
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[(set_attr "isa" "bmi,bmi,avx512bw")
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(set_attr "type" "bitmanip,bitmanip,msklog")
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(set_attr "btver2_decode" "direct, double,*")
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(set_attr "mode" "<MODE>")])
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(define_insn "*andn<mode>_1"
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[(set (match_operand:SWI12 0 "register_operand" "=r")
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[(set (match_operand:SWI12 0 "register_operand" "=r,k")
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(and:SWI12
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(not:SWI12 (match_operand:SWI12 1 "register_operand" "r"))
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(match_operand:SWI12 2 "register_operand" "r")))
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(not:SWI12 (match_operand:SWI12 1 "register_operand" "r,k"))
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(match_operand:SWI12 2 "register_operand" "r,k")))
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(clobber (reg:CC FLAGS_REG))]
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"TARGET_BMI"
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"andn\t{%k2, %k1, %k0|%k0, %k1, %k2}"
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[(set_attr "type" "bitmanip")
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(set_attr "btver2_decode" "direct")
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(set_attr "mode" "SI")])
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"TARGET_BMI || TARGET_AVX512BW"
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"@
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andn\t{%k2, %k1, %k0|%k0, %k1, %k2}
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#"
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[(set_attr "isa" "bmi,avx512f")
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(set_attr "type" "bitmanip,msklog")
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(set_attr "btver2_decode" "direct,*")
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(set (attr "mode")
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(cond [(eq_attr "alternative" "0")
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(const_string "SI")
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(and (eq_attr "alternative" "1")
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(match_test "!TARGET_AVX512DQ"))
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(const_string "HI")
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]
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(const_string "<MODE>")))])
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(define_insn "*andn_<mode>_ccno"
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[(set (reg FLAGS_REG)
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@ -9631,14 +9676,24 @@
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})
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(define_insn "*<code><mode>_1"
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[(set (match_operand:SWI248 0 "nonimmediate_operand" "=rm,r")
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[(set (match_operand:SWI248 0 "nonimmediate_operand" "=rm,r,k")
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(any_or:SWI248
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(match_operand:SWI248 1 "nonimmediate_operand" "%0,0")
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(match_operand:SWI248 2 "<general_operand>" "r<i>,m")))
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(match_operand:SWI248 1 "nonimmediate_operand" "%0,0,k")
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(match_operand:SWI248 2 "<general_operand>" "r<i>,m,k")))
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(clobber (reg:CC FLAGS_REG))]
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"ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
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"<logic>{<imodesuffix>}\t{%2, %0|%0, %2}"
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[(set_attr "type" "alu")
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"@
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<logic>{<imodesuffix>}\t{%2, %0|%0, %2}
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<logic>{<imodesuffix>}\t{%2, %0|%0, %2}
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#"
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[(set (attr "isa")
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(cond [(eq_attr "alternative" "2")
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(if_then_else (eq_attr "mode" "SI,DI")
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(const_string "avx512bw")
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(const_string "avx512f"))
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]
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(const_string "*")))
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(set_attr "type" "alu, alu, msklog")
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(set_attr "mode" "<MODE>")])
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(define_insn_and_split "*iordi_1_bts"
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@ -9711,17 +9766,26 @@
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(set_attr "mode" "SI")])
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(define_insn "*<code>qi_1"
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[(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q,r")
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(any_or:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
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(match_operand:QI 2 "general_operand" "qn,m,rn")))
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[(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q,r,k")
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(any_or:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0,k")
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(match_operand:QI 2 "general_operand" "qn,m,rn,k")))
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(clobber (reg:CC FLAGS_REG))]
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"ix86_binary_operator_ok (<CODE>, QImode, operands)"
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"@
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<logic>{b}\t{%2, %0|%0, %2}
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<logic>{b}\t{%2, %0|%0, %2}
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<logic>{l}\t{%k2, %k0|%k0, %k2}"
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[(set_attr "type" "alu")
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(set_attr "mode" "QI,QI,SI")
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<logic>{l}\t{%k2, %k0|%k0, %k2}
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#"
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[(set_attr "isa" "*,*,*,avx512f")
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(set_attr "type" "alu,alu,alu,msklog")
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(set (attr "mode")
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(cond [(eq_attr "alternative" "2")
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(const_string "SI")
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(and (eq_attr "alternative" "3")
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(match_test "!TARGET_AVX512DQ"))
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(const_string "HI")
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]
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(const_string "QI")))
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;; Potential partial reg stall on alternative 2.
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(set (attr "preferred_for_speed")
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(cond [(eq_attr "alternative" "2")
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@ -10370,31 +10434,52 @@
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"split_double_mode (DImode, &operands[0], 2, &operands[0], &operands[2]);")
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(define_insn "*one_cmpl<mode>2_1"
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[(set (match_operand:SWI248 0 "nonimmediate_operand" "=rm")
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(not:SWI248 (match_operand:SWI248 1 "nonimmediate_operand" "0")))]
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[(set (match_operand:SWI248 0 "nonimmediate_operand" "=rm,k")
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(not:SWI248 (match_operand:SWI248 1 "nonimmediate_operand" "0,k")))]
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"ix86_unary_operator_ok (NOT, <MODE>mode, operands)"
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"not{<imodesuffix>}\t%0"
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[(set_attr "type" "negnot")
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"@
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not{<imodesuffix>}\t%0
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#"
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[(set (attr "isa")
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(cond [(eq_attr "alternative" "2")
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(if_then_else (eq_attr "mode" "SI,DI")
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(const_string "avx512bw")
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(const_string "avx512f"))
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]
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(const_string "*")))
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(set_attr "type" "negnot,msklog")
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(set_attr "mode" "<MODE>")])
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(define_insn "*one_cmplsi2_1_zext"
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[(set (match_operand:DI 0 "register_operand" "=r")
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[(set (match_operand:DI 0 "register_operand" "=r,k")
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(zero_extend:DI
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(not:SI (match_operand:SI 1 "register_operand" "0"))))]
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(not:SI (match_operand:SI 1 "register_operand" "0,k"))))]
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"TARGET_64BIT && ix86_unary_operator_ok (NOT, SImode, operands)"
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"not{l}\t%k0"
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[(set_attr "type" "negnot")
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(set_attr "mode" "SI")])
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"@
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not{l}\t%k0
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#"
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[(set_attr "isa" "x64,avx512bw")
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(set_attr "type" "negnot,msklog")
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(set_attr "mode" "SI,SI")])
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(define_insn "*one_cmplqi2_1"
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[(set (match_operand:QI 0 "nonimmediate_operand" "=qm,r")
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(not:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")))]
|
||||
[(set (match_operand:QI 0 "nonimmediate_operand" "=qm,r,k")
|
||||
(not:QI (match_operand:QI 1 "nonimmediate_operand" "0,0,k")))]
|
||||
"ix86_unary_operator_ok (NOT, QImode, operands)"
|
||||
"@
|
||||
not{b}\t%0
|
||||
not{l}\t%k0"
|
||||
[(set_attr "type" "negnot")
|
||||
(set_attr "mode" "QI,SI")
|
||||
not{l}\t%k0
|
||||
#"
|
||||
[(set_attr "isa" "*,*,avx512f")
|
||||
(set_attr "type" "negnot,negnot,msklog")
|
||||
(set (attr "mode")
|
||||
(cond [(eq_attr "alternative" "1")
|
||||
(const_string "SI")
|
||||
(and (eq_attr "alternative" "2")
|
||||
(match_test "!TARGET_AVX512DQ"))
|
||||
(const_string "HI")
|
||||
]
|
||||
(const_string "QI")))
|
||||
;; Potential partial reg stall on alternative 1.
|
||||
(set (attr "preferred_for_speed")
|
||||
(cond [(eq_attr "alternative" "1")
|
||||
|
||||
@ -87,6 +87,11 @@
|
||||
(and (match_code "reg")
|
||||
(match_test "REGNO (op) == FLAGS_REG")))
|
||||
|
||||
;; True if the operand is a MASK register.
|
||||
(define_predicate "mask_reg_operand"
|
||||
(and (match_code "reg")
|
||||
(match_test "MASK_REGNO_P (REGNO (op))")))
|
||||
|
||||
;; Match a DI, SI, HI or QImode nonimmediate_operand.
|
||||
(define_special_predicate "int_nonimmediate_operand"
|
||||
(and (match_operand 0 "nonimmediate_operand")
|
||||
|
||||
@ -1470,6 +1470,18 @@
|
||||
]
|
||||
(const_string "<MODE>")))])
|
||||
|
||||
(define_split
|
||||
[(set (match_operand:SWI1248_AVX512BW 0 "mask_reg_operand")
|
||||
(any_logic:SWI1248_AVX512BW
|
||||
(match_operand:SWI1248_AVX512BW 1 "mask_reg_operand")
|
||||
(match_operand:SWI1248_AVX512BW 2 "mask_reg_operand")))
|
||||
(clobber (reg:CC FLAGS_REG))]
|
||||
"TARGET_AVX512F && reload_completed"
|
||||
[(parallel
|
||||
[(set (match_dup 0)
|
||||
(any_logic:SWI1248_AVX512BW (match_dup 1) (match_dup 2)))
|
||||
(unspec [(const_int 0)] UNSPEC_MASKOP)])])
|
||||
|
||||
(define_insn "kandn<mode>"
|
||||
[(set (match_operand:SWI1248_AVX512BW 0 "register_operand" "=k")
|
||||
(and:SWI1248_AVX512BW
|
||||
@ -1493,6 +1505,21 @@
|
||||
]
|
||||
(const_string "<MODE>")))])
|
||||
|
||||
(define_split
|
||||
[(set (match_operand:SWI1248_AVX512BW 0 "mask_reg_operand")
|
||||
(and:SWI1248_AVX512BW
|
||||
(not:SWI1248_AVX512BW
|
||||
(match_operand:SWI1248_AVX512BW 1 "mask_reg_operand"))
|
||||
(match_operand:SWI1248_AVX512BW 2 "mask_reg_operand")))
|
||||
(clobber (reg:CC FLAGS_REG))]
|
||||
"TARGET_AVX512F && reload_completed"
|
||||
[(parallel
|
||||
[(set (match_dup 0)
|
||||
(and:SWI1248_AVX512BW
|
||||
(not:SWI1248_AVX512BW (match_dup 1))
|
||||
(match_dup 2)))
|
||||
(unspec [(const_int 0)] UNSPEC_MASKOP)])])
|
||||
|
||||
(define_insn "kxnor<mode>"
|
||||
[(set (match_operand:SWI1248_AVX512BW 0 "register_operand" "=k")
|
||||
(not:SWI1248_AVX512BW
|
||||
@ -1537,6 +1564,38 @@
|
||||
]
|
||||
(const_string "<MODE>")))])
|
||||
|
||||
(define_split
|
||||
[(set (match_operand:SWI1248_AVX512BW 0 "mask_reg_operand")
|
||||
(not:SWI1248_AVX512BW
|
||||
(match_operand:SWI1248_AVX512BW 1 "mask_reg_operand")))]
|
||||
"TARGET_AVX512F && reload_completed"
|
||||
[(parallel
|
||||
[(set (match_dup 0)
|
||||
(not:SWI1248_AVX512BW (match_dup 1)))
|
||||
(unspec [(const_int 0)] UNSPEC_MASKOP)])])
|
||||
|
||||
(define_insn "*knotsi_1_zext"
|
||||
[(set (match_operand:DI 0 "register_operand" "=k")
|
||||
(zero_extend:DI
|
||||
(not:SI (match_operand:SI 1 "register_operand" "k"))))
|
||||
(unspec [(const_int 0)] UNSPEC_MASKOP)]
|
||||
"TARGET_AVX512BW"
|
||||
"knotd\t{%1, %0|%0, %1}";
|
||||
[(set_attr "type" "msklog")
|
||||
(set_attr "prefix" "vex")
|
||||
(set_attr "mode" "SI")])
|
||||
|
||||
(define_split
|
||||
[(set (match_operand:DI 0 "mask_reg_operand")
|
||||
(zero_extend:DI
|
||||
(not:DI (match_operand:SI 1 "mask_reg_operand"))))]
|
||||
"TARGET_AVX512BW && reload_completed"
|
||||
[(parallel
|
||||
[(set (match_dup 0)
|
||||
(zero_extend:DI
|
||||
(not:SI (match_dup 1))))
|
||||
(unspec [(const_int 0)] UNSPEC_MASKOP)])])
|
||||
|
||||
(define_insn "kadd<mode>"
|
||||
[(set (match_operand:SWI1248_AVX512BWDQ2 0 "register_operand" "=k")
|
||||
(plus:SWI1248_AVX512BWDQ2
|
||||
|
||||
@ -1,6 +1,6 @@
|
||||
/* { dg-do compile } */
|
||||
/* { dg-options "-mavx512bw -O2" } */
|
||||
/* { dg-final { scan-assembler-times "kunpckwd\[ \\t\]+\[^\{\n\]*%k\[1-7\](?:\n|\[ \\t\]+#)" 1 } } */
|
||||
/* { dg-final { scan-assembler-times "kunpckwd\[ \\t\]+\[^\{\n\]*%k\[0-7\](?:\n|\[ \\t\]+#)" 1 } } */
|
||||
|
||||
#include <immintrin.h>
|
||||
|
||||
|
||||
@ -1,6 +1,6 @@
|
||||
/* { dg-do compile } */
|
||||
/* { dg-options "-mavx512bw -O2" } */
|
||||
/* { dg-final { scan-assembler-times "kunpckwd\[ \\t\]+\[^\{\n\]*%k\[1-7\](?:\n|\[ \\t\]+#)" 1 } } */
|
||||
/* { dg-final { scan-assembler-times "kunpckwd\[ \\t\]+\[^\{\n\]*%k\[0-7\](?:\n|\[ \\t\]+#)" 1 } } */
|
||||
|
||||
#include <immintrin.h>
|
||||
|
||||
|
||||
23
gcc/testsuite/gcc.target/i386/avx512bw-pr88465.c
Normal file
23
gcc/testsuite/gcc.target/i386/avx512bw-pr88465.c
Normal file
@ -0,0 +1,23 @@
|
||||
/* PR target/88465 */
|
||||
/* { dg-do compile { target { ! ia32 } } } */
|
||||
/* { dg-options "-O2 -mavx512bw" } */
|
||||
/* { dg-final { scan-assembler-times "kxor\[qd\]\[ \t]" 2 } } */
|
||||
/* { dg-final { scan-assembler-times "kxnor\[dq\]\[ \t]" 2 } } */
|
||||
|
||||
void
|
||||
foo (void)
|
||||
{
|
||||
unsigned int k = 0;
|
||||
__asm volatile ("" : : "k" (k));
|
||||
k = -1;
|
||||
__asm volatile ("" : : "k" (k));
|
||||
}
|
||||
|
||||
void
|
||||
bar (void)
|
||||
{
|
||||
unsigned long long k = 0;
|
||||
__asm volatile ("" : : "k" (k));
|
||||
k = -1;
|
||||
__asm volatile ("" : : "k" (k));
|
||||
}
|
||||
@ -1,5 +1,5 @@
|
||||
/* { dg-do compile } */
|
||||
/* { dg-options "-mavx512dq -O2" } */
|
||||
/* { dg-options "-mavx512dq -mno-avx512bw -O2" } */
|
||||
/* { dg-final { scan-assembler-times "kmovb\[ \\t\]+\[^\{\n\]*%k\[0-7\](?:\n|\[ \\t\]+#)" 1 } } */
|
||||
|
||||
#include <immintrin.h>
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
/* { dg-do compile } */
|
||||
/* { dg-options "-mavx512f -O2" } */
|
||||
/* { dg-options "-mavx512f -mno-avx512bw -O2" } */
|
||||
/* { dg-final { scan-assembler-times "kmovw\[ \\t\]+\[^\{\n\]*%k\[0-7\](?:\n|\[ \\t\]+#)" 1 } } */
|
||||
|
||||
#include <immintrin.h>
|
||||
|
||||
178
gcc/testsuite/gcc.target/i386/bitwise_mask_op-1.c
Normal file
178
gcc/testsuite/gcc.target/i386/bitwise_mask_op-1.c
Normal file
@ -0,0 +1,178 @@
|
||||
/* PR target/88808 */
|
||||
/* { dg-do compile } */
|
||||
/* { dg-options "-mavx512bw -mno-avx512dq -O2" } */
|
||||
|
||||
#include <immintrin.h>
|
||||
__m512i
|
||||
foo_orq (__m512i a, __m512i b, __m512i c, __m512i d)
|
||||
{
|
||||
__mmask64 m1 = _mm512_cmpeq_epi8_mask (a, b);
|
||||
__mmask64 m2 = _mm512_cmpeq_epi8_mask (c, d);
|
||||
return _mm512_mask_add_epi8 (c, m1 | m2, a, d);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler-times "korq" "1" { target { ! ia32 } } } } */
|
||||
|
||||
__m512i
|
||||
foo_ord (__m512i a, __m512i b, __m512i c, __m512i d)
|
||||
{
|
||||
__mmask32 m1 = _mm512_cmpeq_epi16_mask (a, b);
|
||||
__mmask32 m2 = _mm512_cmpeq_epi16_mask (c, d);
|
||||
return _mm512_mask_add_epi16 (c, m1 | m2, a, d);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler-times "kord" "1" } } */
|
||||
|
||||
__m512i
|
||||
foo_orw (__m512i a, __m512i b, __m512i c, __m512i d)
|
||||
{
|
||||
__mmask16 m1 = _mm512_cmpeq_epi32_mask (a, b);
|
||||
__mmask16 m2 = _mm512_cmpeq_epi32_mask (c, d);
|
||||
return _mm512_mask_add_epi32 (c, m1 | m2, a, d);
|
||||
}
|
||||
|
||||
__m512i
|
||||
foo_orb (__m512i a, __m512i b, __m512i c, __m512i d)
|
||||
{
|
||||
__mmask8 m1 = _mm512_cmpeq_epi64_mask (a, b);
|
||||
__mmask8 m2 = _mm512_cmpeq_epi64_mask (c, d);
|
||||
return _mm512_mask_add_epi64 (c, m1 | m2, a, d);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler-times "korw" "2" } } */
|
||||
|
||||
__m512i
|
||||
foo_xorq (__m512i a, __m512i b, __m512i c, __m512i d)
|
||||
{
|
||||
__mmask64 m1 = _mm512_cmpeq_epi8_mask (a, b);
|
||||
__mmask64 m2 = _mm512_cmpeq_epi8_mask (c, d);
|
||||
return _mm512_mask_add_epi8 (c, m1 ^ m2, a, d);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler-times "kxorq" "1" { target { ! ia32 } } } } */
|
||||
|
||||
__m512i
|
||||
foo_xord (__m512i a, __m512i b, __m512i c, __m512i d)
|
||||
{
|
||||
__mmask32 m1 = _mm512_cmpeq_epi16_mask (a, b);
|
||||
__mmask32 m2 = _mm512_cmpeq_epi16_mask (c, d);
|
||||
return _mm512_mask_add_epi16 (c, m1 ^ m2, a, d);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler-times "kxord" "1" } } */
|
||||
|
||||
__m512i
|
||||
foo_xorw (__m512i a, __m512i b, __m512i c, __m512i d)
|
||||
{
|
||||
__mmask16 m1 = _mm512_cmpeq_epi32_mask (a, b);
|
||||
__mmask16 m2 = _mm512_cmpeq_epi32_mask (c, d);
|
||||
return _mm512_mask_add_epi32 (c, m1 ^ m2, a, d);
|
||||
}
|
||||
|
||||
__m512i
|
||||
foo_xorb (__m512i a, __m512i b, __m512i c, __m512i d)
|
||||
{
|
||||
__mmask8 m1 = _mm512_cmpeq_epi64_mask (a, b);
|
||||
__mmask8 m2 = _mm512_cmpeq_epi64_mask (c, d);
|
||||
return _mm512_mask_add_epi64 (c, m1 ^ m2, a, d);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler-times "korw" "2" } } */
|
||||
|
||||
__m512i
|
||||
foo_andq (__m512i a, __m512i b, __m512i c, __m512i d)
|
||||
{
|
||||
__mmask64 m1 = _mm512_cmpeq_epi8_mask (a, b);
|
||||
__mmask64 m2 = _mm512_cmpeq_epi8_mask (c, d);
|
||||
return _mm512_mask_add_epi8 (c, m1 & m2, a, d);
|
||||
}
|
||||
|
||||
__m512i
|
||||
foo_andd (__m512i a, __m512i b, __m512i c, __m512i d)
|
||||
{
|
||||
__mmask32 m1 = _mm512_cmpeq_epi16_mask (a, b);
|
||||
__mmask32 m2 = _mm512_cmpeq_epi16_mask (c, d);
|
||||
return _mm512_mask_add_epi16 (c, m1 & m2, a, d);
|
||||
}
|
||||
|
||||
__m512i
|
||||
foo_andw (__m512i a, __m512i b, __m512i c, __m512i d)
|
||||
{
|
||||
__mmask16 m1 = _mm512_cmpeq_epi32_mask (a, b);
|
||||
__mmask16 m2 = _mm512_cmpeq_epi32_mask (c, d);
|
||||
return _mm512_mask_add_epi32 (c, m1 & m2, a, d);
|
||||
}
|
||||
|
||||
__m512i
|
||||
foo_andb (__m512i a, __m512i b, __m512i c, __m512i d)
|
||||
{
|
||||
__mmask8 m1 = _mm512_cmpeq_epi64_mask (a, b);
|
||||
__mmask8 m2 = _mm512_cmpeq_epi64_mask (c, d);
|
||||
return _mm512_mask_add_epi64 (c, m1 & m2, a, d);
|
||||
}
|
||||
|
||||
__m512i
|
||||
foo_andnq (__m512i a, __m512i b, __m512i c, __m512i d)
|
||||
{
|
||||
__mmask64 m1 = _mm512_cmpeq_epi8_mask (a, b);
|
||||
__mmask64 m2 = _mm512_cmpeq_epi8_mask (c, d);
|
||||
return _mm512_mask_add_epi8 (c, m1 & ~m2, a, d);
|
||||
}
|
||||
|
||||
__m512i
|
||||
foo_andnd (__m512i a, __m512i b, __m512i c, __m512i d)
|
||||
{
|
||||
__mmask32 m1 = _mm512_cmpeq_epi16_mask (a, b);
|
||||
__mmask32 m2 = _mm512_cmpeq_epi16_mask (c, d);
|
||||
return _mm512_mask_add_epi16 (c, m1 & ~m2, a, d);
|
||||
}
|
||||
|
||||
__m512i
|
||||
foo_andnw (__m512i a, __m512i b, __m512i c, __m512i d)
|
||||
{
|
||||
__mmask16 m1 = _mm512_cmpeq_epi32_mask (a, b);
|
||||
__mmask16 m2 = _mm512_cmpeq_epi32_mask (c, d);
|
||||
return _mm512_mask_add_epi32 (c, m1 & ~m2, a, d);
|
||||
}
|
||||
|
||||
__m512i
|
||||
foo_andnb (__m512i a, __m512i b, __m512i c, __m512i d)
|
||||
{
|
||||
__mmask8 m1 = _mm512_cmpeq_epi64_mask (a, b);
|
||||
__mmask8 m2 = _mm512_cmpeq_epi64_mask (c, d);
|
||||
return _mm512_mask_add_epi64 (c, m1 & ~m2, a, d);
|
||||
}
|
||||
|
||||
__m512i
|
||||
foo_notq (__m512i a, __m512i b, __m512i c, __m512i d)
|
||||
{
|
||||
__mmask64 m1 = _mm512_cmpeq_epi8_mask (a, b);
|
||||
return _mm512_mask_add_epi8 (c, ~m1, a, d);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler-times "knotq" "2" { target { ! ia32 } } } } */
|
||||
|
||||
__m512i
|
||||
foo_notd (__m512i a, __m512i b, __m512i c, __m512i d)
|
||||
{
|
||||
__mmask32 m1 = _mm512_cmpeq_epi16_mask (a, b);
|
||||
return _mm512_mask_add_epi16 (c, ~m1, a, d);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler-times "knotd" "2" { target { ! ia32 } } } } */
|
||||
|
||||
__m512i
|
||||
foo_notw (__m512i a, __m512i b, __m512i c, __m512i d)
|
||||
{
|
||||
__mmask16 m1 = _mm512_cmpeq_epi32_mask (a, b);
|
||||
return _mm512_mask_add_epi32 (c, ~m1, a, d);
|
||||
}
|
||||
|
||||
__m512i
|
||||
foo_notb (__m512i a, __m512i b, __m512i c, __m512i d)
|
||||
{
|
||||
__mmask8 m1 = _mm512_cmpeq_epi64_mask (a, b);
|
||||
return _mm512_mask_add_epi64 (c, ~m1, a, d);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler-times "knotw" "4" } } */
|
||||
8
gcc/testsuite/gcc.target/i386/bitwise_mask_op-2.c
Normal file
8
gcc/testsuite/gcc.target/i386/bitwise_mask_op-2.c
Normal file
@ -0,0 +1,8 @@
|
||||
/* PR target/88808 */
|
||||
/* { dg-do compile } */
|
||||
/* { dg-options "-mavx512bw -mavx512dq -O2" } */
|
||||
/* { dg-final { scan-assembler-times "knotb" "2" } } */
|
||||
/* { dg-final { scan-assembler-times "korb" "1" } } */
|
||||
/* { dg-final { scan-assembler-times "kxorb" "1" } } */
|
||||
#include "bitwise_mask_op-1.c"
|
||||
|
||||
44
gcc/testsuite/gcc.target/i386/bitwise_mask_op-3.c
Normal file
44
gcc/testsuite/gcc.target/i386/bitwise_mask_op-3.c
Normal file
@ -0,0 +1,44 @@
|
||||
/* PR target/88808 */
|
||||
/* { dg-do compile } */
|
||||
/* { dg-options "-mavx512bw -mavx512dq -O2" } */
|
||||
|
||||
#include <immintrin.h>
|
||||
volatile __mmask8 foo;
|
||||
void
|
||||
foo_orb (__m512i a, __m512i b)
|
||||
{
|
||||
__mmask8 m1 = _mm512_cmp_epi64_mask (a, b, 2);
|
||||
__mmask8 m2 = _mm512_cmp_epi64_mask (a, b, 4);
|
||||
foo = m1 | m2;
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler-times "korb\[\t \]" "1" } } */
|
||||
|
||||
void
|
||||
foo_xorb (__m512i a, __m512i b)
|
||||
{
|
||||
__mmask8 m1 = _mm512_cmp_epi64_mask (a, b, 2);
|
||||
__mmask8 m2 = _mm512_cmp_epi64_mask (a, b, 4);
|
||||
foo = m1 ^ m2;
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler-times "kxorb\[\t \]" "1" } } */
|
||||
|
||||
void
|
||||
foo_andb (__m512i a, __m512i b)
|
||||
{
|
||||
__mmask8 m1 = _mm512_cmp_epi64_mask (a, b, 2);
|
||||
__mmask8 m2 = _mm512_cmp_epi64_mask (a, b, 4);
|
||||
foo = m1 & m2;
|
||||
}
|
||||
|
||||
void
|
||||
foo_andnb (__m512i a, __m512i b)
|
||||
{
|
||||
__mmask8 m1 = _mm512_cmp_epi64_mask (a, b, 2);
|
||||
__mmask8 m2 = _mm512_cmp_epi64_mask (a, b, 4);
|
||||
foo = m1 & ~m2;
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler-times "knotb\[\t \]" "1" } } */
|
||||
/* { dg-final { scan-assembler-times "kmovb\[\t \]" "4"} } */
|
||||
@ -1,6 +1,6 @@
|
||||
/* PR rtl-optimization/55342 */
|
||||
/* { dg-do compile } */
|
||||
/* { dg-options "-O2" } */
|
||||
/* { dg-options "-O2 -mno-avx512dq" } */
|
||||
/* { dg-final { scan-assembler-not "notb" } } */
|
||||
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user