backport: re PR rtl-optimization/83628 (performance regression when accessing arrays on alpha)
Backport from mainline 2018-01-12 Uros Bizjak <ubizjak@gmail.com> PR target/83628 * config/alpha/alpha.md (*saddsi_1): New insn_ans_split pattern. (*saddl_se_1): Ditto. (*ssubsi_1): Ditto. (*ssubl_se_1): Ditto. Backport from mainline 2018-01-09 Uros Bizjak <ubizjak@gmail.com> PR target/83628 * combine.c (force_int_to_mode) <case ASHIFT>: Use mode instead of op_mode in the force_to_mode call. testsuite/ChangeLog: Backport from mainline 2018-01-12 Uros Bizjak <ubizjak@gmail.com> PR target/83628 * gcc.target/alpha/pr83628-3.c: New test. From-SVN: r256665
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Uros Bizjak
Uros Bizjak
parent
2d8d78a10d
commit
38c84ba5d6
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@ -1,3 +1,21 @@
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2018-01-14 Uros Bizjak <ubizjak@gmail.com>
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Backport from mainline
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2018-01-12 Uros Bizjak <ubizjak@gmail.com>
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PR target/83628
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* config/alpha/alpha.md (*saddsi_1): New insn_ans_split pattern.
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(*saddl_se_1): Ditto.
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(*ssubsi_1): Ditto.
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(*ssubl_se_1): Ditto.
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Backport from mainline
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2018-01-09 Uros Bizjak <ubizjak@gmail.com>
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PR target/83628
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* combine.c (force_int_to_mode) <case ASHIFT>: Use mode instead of
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op_mode in the force_to_mode call.
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2018-01-12 Oleg Endo <olegendo@gcc.gnu.org>
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Backport from mainline
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@ -8785,7 +8785,7 @@ force_to_mode (rtx x, machine_mode mode, unsigned HOST_WIDE_INT mask,
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mask = fuller_mask;
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op0 = gen_lowpart_or_truncate (op_mode,
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force_to_mode (XEXP (x, 0), op_mode,
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force_to_mode (XEXP (x, 0), mode,
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mask, next_select));
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if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
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@ -527,17 +527,50 @@
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s%P2add<modesuffix> %1,%3,%0
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s%P2sub<modesuffix> %1,%n3,%0")
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(define_insn_and_split "*saddsi_1"
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[(set (match_operand:SI 0 "register_operand" "=r,r")
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(plus:SI
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(subreg:SI
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(ashift:DI (match_operand:DI 1 "reg_not_elim_operand" "r,r")
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(match_operand:DI 2 "const23_operand" "I,I")) 0)
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(match_operand:SI 3 "sext_add_operand" "rI,O")))]
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""
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"#"
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""
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[(set (match_dup 0)
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(plus:SI (ashift:SI (match_dup 1) (match_dup 2))
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(match_dup 3)))]
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"operands[1] = gen_lowpart (SImode, operands[1]);")
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(define_insn "*saddl_se"
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[(set (match_operand:DI 0 "register_operand" "=r,r")
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(sign_extend:DI
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(plus:SI (ashift:SI (match_operand:SI 1 "reg_not_elim_operand" "r,r")
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(match_operand:SI 2 "const23_operand" "I,I"))
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(match_operand:SI 3 "sext_add_operand" "rI,O"))))]
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(plus:SI
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(ashift:SI (match_operand:SI 1 "reg_not_elim_operand" "r,r")
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(match_operand:SI 2 "const23_operand" "I,I"))
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(match_operand:SI 3 "sext_add_operand" "rI,O"))))]
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""
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"@
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s%P2addl %1,%3,%0
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s%P2subl %1,%n3,%0")
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(define_insn_and_split "*saddl_se_1"
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[(set (match_operand:DI 0 "register_operand" "=r,r")
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(sign_extend:DI
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(plus:SI
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(subreg:SI
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(ashift:DI (match_operand:DI 1 "reg_not_elim_operand" "r,r")
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(match_operand:DI 2 "const23_operand" "I,I")) 0)
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(match_operand:SI 3 "sext_add_operand" "rI,O"))))]
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""
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"#"
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""
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[(set (match_dup 0)
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(sign_extend:DI
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(plus:SI (ashift:SI (match_dup 1) (match_dup 2))
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(match_dup 3))))]
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"operands[1] = gen_lowpart (SImode, operands[1]);")
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(define_split
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[(set (match_operand:DI 0 "register_operand")
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(sign_extend:DI
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@ -627,15 +660,48 @@
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""
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"s%P2sub<modesuffix> %1,%3,%0")
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(define_insn_and_split "*ssubsi_1"
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[(set (match_operand:SI 0 "register_operand" "=r")
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(minus:SI
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(subreg:SI
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(ashift:DI (match_operand:DI 1 "reg_not_elim_operand" "r")
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(match_operand:DI 2 "const23_operand" "I")) 0)
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(match_operand:SI 3 "reg_or_8bit_operand" "rI")))]
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""
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"#"
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""
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[(set (match_dup 0)
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(minus:SI (ashift:SI (match_dup 1) (match_dup 2))
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(match_dup 3)))]
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"operands[1] = gen_lowpart (SImode, operands[1]);")
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(define_insn "*ssubl_se"
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[(set (match_operand:DI 0 "register_operand" "=r")
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(sign_extend:DI
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(minus:SI (ashift:SI (match_operand:SI 1 "reg_not_elim_operand" "r")
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(match_operand:SI 2 "const23_operand" "I"))
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(match_operand:SI 3 "reg_or_8bit_operand" "rI"))))]
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(minus:SI
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(ashift:SI (match_operand:SI 1 "reg_not_elim_operand" "r")
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(match_operand:SI 2 "const23_operand" "I"))
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(match_operand:SI 3 "reg_or_8bit_operand" "rI"))))]
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""
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"s%P2subl %1,%3,%0")
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(define_insn_and_split "*ssubl_se_1"
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[(set (match_operand:DI 0 "register_operand" "=r")
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(sign_extend:DI
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(minus:SI
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(subreg:SI
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(ashift:DI (match_operand:DI 1 "reg_not_elim_operand" "r")
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(match_operand:DI 2 "const23_operand" "I")) 0)
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(match_operand:SI 3 "reg_or_8bit_operand" "rI"))))]
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""
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"#"
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""
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[(set (match_dup 0)
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(sign_extend:DI
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(minus:SI (ashift:SI (match_dup 1) (match_dup 2))
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(match_dup 3))))]
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"operands[1] = gen_lowpart (SImode, operands[1]);")
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(define_insn "subv<mode>3"
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[(set (match_operand:I48MODE 0 "register_operand" "=r")
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(minus:I48MODE (match_operand:I48MODE 1 "reg_or_0_operand" "rJ")
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@ -1200,7 +1266,7 @@
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(subreg:SI (ashift:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
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(match_operand:DI 2 "const_int_operand" "P"))
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0)))]
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"INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 3"
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"IN_RANGE (INTVAL (operands[2]), 1, 3)"
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{
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if (operands[2] == const1_rtx)
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return "addl %r1,%r1,%0";
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@ -1,3 +1,11 @@
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2018-01-14 Uros Bizjak <ubizjak@gmail.com>
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Backport from mainline
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2018-01-12 Uros Bizjak <ubizjak@gmail.com>
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PR target/83628
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* gcc.target/alpha/pr83628-3.c: New test.
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2018-01-13 Steven G. Kargl <kargl@gcc.gnu.org>
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Backport from mainline
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@ -5,25 +5,25 @@
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int
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s4l (int a, int b)
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{
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return a + b * 4;
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return a * 4 + b;
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}
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int
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s8l (int a, int b)
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{
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return a + b * 8;
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return a * 8 + b;
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}
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long
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s4q (long a, long b)
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{
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return a + b * 4;
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return a * 4 + b;
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}
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long
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s8q (long a, long b)
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{
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return a + b * 8;
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return a * 8 + b;
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}
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/* { dg-final { scan-assembler-not "\[ \t\]add\[ql\]" } } */
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@ -0,0 +1,29 @@
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/* PR target/83628 */
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/* { dg-do compile } */
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/* { dg-options "-O2" } */
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int
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s4l (int a, int b)
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{
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return a * 4 - b;
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}
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int
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s8l (int a, int b)
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{
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return a * 8 - b;
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}
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long
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s4q (long a, long b)
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{
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return a * 4 - b;
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}
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long
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s8q (long a, long b)
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{
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return a * 8 - b;
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}
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/* { dg-final { scan-assembler-not "\[ \t\]sub\[ql\]" } } */
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