re PR bootstrap/49486 (Bootstrap failure)
PR target/49486 * config/sh/sh.md (negdi2): Move expansion into split to allow more combination options. Add T_REG clobber. (abssi2): New expander. (*negdi2, *abssi2, *negabssi2): New insns. (cneg): Change from insn to insn_and_split. Rename to negsi_cond. Add alternative for non-SH4. * gcc.target/sh/pr49468-si.c: New. From-SVN: r179320
This commit is contained in:
Oleg Endo
Kaz Kojima
parent
8c850a5a7f
commit
39f2bcb5e1
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@ -1,3 +1,13 @@
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2011-09-28 Oleg Endo <oleg.endo@t-online.de>
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PR target/49486
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* config/sh/sh.md (negdi2): Move expansion into split to
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allow more combination options. Add T_REG clobber.
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(abssi2): New expander.
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(*negdi2, *abssi2, *negabssi2): New insns.
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(cneg): Change from insn to insn_and_split. Rename to
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negsi_cond. Add alternative for non-SH4.
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2011-09-28 Richard Sandiford <richard.sandiford@linaro.org>
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* config/arm/neon.md (neon_move_lo_quad_<mode>): Delete.
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@ -4282,28 +4282,39 @@ label:
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"sub r63, %1, %0"
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[(set_attr "type" "arith_media")])
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;; Don't expand immediately because otherwise neg:DI (abs:DI) will not be
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;; combined.
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(define_expand "negdi2"
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[(set (match_operand:DI 0 "arith_reg_operand" "")
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(neg:DI (match_operand:DI 1 "arith_reg_operand" "")))]
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[(set (match_operand:DI 0 "arith_reg_dest" "")
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(neg:DI (match_operand:DI 1 "arith_reg_operand" "")))
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(clobber (reg:SI T_REG))]
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""
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"")
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(define_insn_and_split "*negdi2"
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[(set (match_operand:DI 0 "arith_reg_dest" "=r")
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(neg:DI (match_operand:DI 1 "arith_reg_operand" "r")))]
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"TARGET_SH1"
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"#"
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"TARGET_SH1"
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[(const_int 0)]
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"
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{
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if (TARGET_SH1)
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{
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int low_word = (TARGET_LITTLE_ENDIAN ? 0 : 1);
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int high_word = (TARGET_LITTLE_ENDIAN ? 1 : 0);
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int low_word = (TARGET_LITTLE_ENDIAN ? 0 : 1);
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int high_word = (TARGET_LITTLE_ENDIAN ? 1 : 0);
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rtx low_src = operand_subword (operands[1], low_word, 0, DImode);
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rtx high_src = operand_subword (operands[1], high_word, 0, DImode);
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rtx low_src = operand_subword (operands[1], low_word, 0, DImode);
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rtx high_src = operand_subword (operands[1], high_word, 0, DImode);
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rtx low_dst = operand_subword (operands[0], low_word, 1, DImode);
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rtx high_dst = operand_subword (operands[0], high_word, 1, DImode);
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rtx low_dst = operand_subword (operands[0], low_word, 1, DImode);
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rtx high_dst = operand_subword (operands[0], high_word, 1, DImode);
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emit_insn (gen_clrt ());
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emit_insn (gen_negc (low_dst, low_src));
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emit_insn (gen_negc (high_dst, high_src));
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DONE;
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}
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emit_insn (gen_clrt ());
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emit_insn (gen_negc (low_dst, low_src));
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emit_insn (gen_negc (high_dst, high_src));
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DONE;
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}")
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(define_insn "negsi2"
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@ -4326,27 +4337,77 @@ label:
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(const_int -1)))]
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"TARGET_SHMEDIA" "")
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/* The SH4 202 can do zero-offset branches without pipeline stalls.
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This can be used as some kind of conditional execution, which is useful
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for abs. */
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(define_split
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(define_expand "abssi2"
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[(set (match_operand:SI 0 "arith_reg_dest" "")
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(plus:SI (xor:SI (neg:SI (reg:SI T_REG))
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(match_operand:SI 1 "arith_reg_operand" ""))
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(reg:SI T_REG)))]
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"TARGET_HARD_SH4"
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[(const_int 0)]
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"emit_insn (gen_movsi_i (operands[0], operands[1]));
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emit_insn (gen_cneg (operands[0], operands[0], operands[0]));
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DONE;")
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(abs:SI (match_operand:SI 1 "arith_reg_operand" "")))
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(clobber (reg:SI T_REG))]
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""
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"")
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(define_insn "cneg"
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(define_insn_and_split "*abssi2"
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[(set (match_operand:SI 0 "arith_reg_dest" "=r")
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(if_then_else:SI (eq:SI (reg:SI T_REG) (const_int 0))
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(match_operand:SI 1 "arith_reg_operand" "0")
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(neg:SI (match_operand:SI 2 "arith_reg_operand" "r"))))]
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(abs:SI (match_operand:SI 1 "arith_reg_operand" "r")))]
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"TARGET_SH1"
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"#"
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"TARGET_SH1"
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[(const_int 0)]
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"
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{
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emit_insn (gen_cmpgesi_t (operands[1], const0_rtx));
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emit_insn (gen_negsi_cond (operands[0], operands[1], operands[1],
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const1_rtx));
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DONE;
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}")
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(define_insn_and_split "*negabssi2"
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[(set (match_operand:SI 0 "arith_reg_dest" "=r")
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(neg:SI (abs:SI (match_operand:SI 1 "arith_reg_operand" "r"))))]
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"TARGET_SH1"
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"#"
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"TARGET_SH1"
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[(const_int 0)]
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"
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{
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emit_insn (gen_cmpgesi_t (operands[1], const0_rtx));
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emit_insn (gen_negsi_cond (operands[0], operands[1], operands[1],
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const0_rtx));
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DONE;
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}")
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;; The SH4 202 can do zero-offset branches without pipeline stalls.
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;; This can be used as some kind of conditional execution, which is useful
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;; for abs.
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;; Actually the instruction scheduling should decide whether to use a
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;; zero-offset branch or not for any generic case involving a single
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;; instruction on SH4 202.
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(define_insn_and_split "negsi_cond"
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[(set (match_operand:SI 0 "arith_reg_dest" "=r,r")
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(if_then_else:SI (eq:SI (reg:SI T_REG)
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(match_operand:SI 3 "const_int_operand" "M,N"))
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(match_operand:SI 1 "arith_reg_operand" "0,0")
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(neg:SI (match_operand:SI 2 "arith_reg_operand" "r,r"))))]
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"TARGET_HARD_SH4"
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"bf 0f\;neg %2,%0\\n0:"
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"@
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bt\\t0f\;neg\\t%2,%0\\n0:
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bf\\t0f\;neg\\t%2,%0\\n0:"
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"!TARGET_HARD_SH4"
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[(const_int 0)]
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"
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{
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rtx skip_neg_label = gen_label_rtx ();
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emit_insn (gen_movsi (operands[0], operands[1]));
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emit_jump_insn (INTVAL (operands[3])
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? gen_branch_true (skip_neg_label)
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: gen_branch_false (skip_neg_label));
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emit_label_after (skip_neg_label,
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emit_insn (gen_negsi2 (operands[0], operands[1])));
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DONE;
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}"
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[(set_attr "type" "arith") ;; poor approximation
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(set_attr "length" "4")])
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@ -1,3 +1,8 @@
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2011-09-28 Oleg Endo <oleg.endo@t-online.de>
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PR target/49486
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* gcc.target/sh/pr49468-si.c: New.
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2011-09-28 Tom de Vries <tom@codesourcery.com>
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PR testsuite/50485
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@ -0,0 +1,22 @@
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/* Check that 32 bit integer abs is generated as neg instruction and
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conditional branch instead of default branch-free code. */
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/* { dg-do compile { target "sh*-*-*" } } */
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/* { dg-options "-O1" } */
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/* { dg-final { scan-assembler-times "neg" 2 } } */
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/* Normal integer absolute value. */
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int
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abs_0 (int i)
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{
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return (i < 0) ? -i : i;
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}
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/* Negated integer absolute value.
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The generated code should be the same, except that the branch
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condition is inverted. */
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int
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abs_1 (int i)
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{
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return (i > 0) ? -i : i;
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}
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