OpenE2K
/
gcc
2
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity

[AArch64] Implement some vca*_f[32,64] intrinsics. 

* config/aarch64/arm_neon.h (vcage_f64): New intrinsic.
	(vcagt_f64): Likewise.
	(vcale_f64): Likewise.
	(vcaled_f64): Likewise.
	(vcales_f32): Likewise.
	(vcalt_f64): Likewise.
	(vcaltd_f64): Likewise.
	(vcalts_f32): Likewise.

	* gcc.target/aarch64/simd/vcage_f64.c: New test.
	* gcc.target/aarch64/simd/vcagt_f64.c: Likewise.
	* gcc.target/aarch64/simd/vcale_f64.c: Likewise.
	* gcc.target/aarch64/simd/vcaled_f64.c: Likewise.
	* gcc.target/aarch64/simd/vcales_f32.c: Likewise.
	* gcc.target/aarch64/simd/vcalt_f64.c: Likewise.
	* gcc.target/aarch64/simd/vcaltd_f64.c: Likewise.
	* gcc.target/aarch64/simd/vcalts_f32.c: Likewise.

From-SVN: r212196
This commit is contained in:
Kyrylo Tkachov 2014-07-01 12:32:35 +00:00 committed by Kyrylo Tkachov
parent f280564356
commit 39f9091275
11 changed files with 366 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

11
gcc/ChangeLog
View File

@ -1,3 +1,14 @@
2014-07-01 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* config/aarch64/arm_neon.h (vcage_f64): New intrinsic.
(vcagt_f64): Likewise.
(vcale_f64): Likewise.
(vcaled_f64): Likewise.
(vcales_f32): Likewise.
(vcalt_f64): Likewise.
(vcaltd_f64): Likewise.
(vcalts_f32): Likewise.
2014-07-01 Marek Polacek <polacek@redhat.com>
* doc/invoke.texi: Document -Wint-conversion.

48
gcc/config/aarch64/arm_neon.h
View File

@ -13823,6 +13823,12 @@ vaesimcq_u8 (uint8x16_t data)
/* vcage */
__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
vcage_f64 (float64x1_t __a, float64x1_t __b)
{
return vabs_f64 (__a) >= vabs_f64 (__b);
}
__extension__ static __inline uint32_t __attribute__ ((__always_inline__))
vcages_f32 (float32_t __a, float32_t __b)
{
@ -13867,6 +13873,12 @@ vcagt_f32 (float32x2_t __a, float32x2_t __b)
return vabs_f32 (__a) > vabs_f32 (__b);
}
__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
vcagt_f64 (float64x1_t __a, float64x1_t __b)
{
return vabs_f64 (__a) > vabs_f64 (__b);
}
__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
vcagtq_f32 (float32x4_t __a, float32x4_t __b)
{
@ -13893,6 +13905,24 @@ vcale_f32 (float32x2_t __a, float32x2_t __b)
return vabs_f32 (__a) <= vabs_f32 (__b);
}
__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
vcale_f64 (float64x1_t __a, float64x1_t __b)
{
return vabs_f64 (__a) <= vabs_f64 (__b);
}
__extension__ static __inline uint64_t __attribute__ ((__always_inline__))
vcaled_f64 (float64_t __a, float64_t __b)
{
return __builtin_fabs (__a) <= __builtin_fabs (__b) ? -1 : 0;
}
__extension__ static __inline uint32_t __attribute__ ((__always_inline__))
vcales_f32 (float32_t __a, float32_t __b)
{
return __builtin_fabsf (__a) <= __builtin_fabsf (__b) ? -1 : 0;
}
__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
vcaleq_f32 (float32x4_t __a, float32x4_t __b)
{
@ -13913,6 +13943,18 @@ vcalt_f32 (float32x2_t __a, float32x2_t __b)
return vabs_f32 (__a) < vabs_f32 (__b);
}
__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
vcalt_f64 (float64x1_t __a, float64x1_t __b)
{
return vabs_f64 (__a) < vabs_f64 (__b);
}
__extension__ static __inline uint64_t __attribute__ ((__always_inline__))
vcaltd_f64 (float64_t __a, float64_t __b)
{
return __builtin_fabs (__a) < __builtin_fabs (__b) ? -1 : 0;
}
__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
vcaltq_f32 (float32x4_t __a, float32x4_t __b)
{
@ -13925,6 +13967,12 @@ vcaltq_f64 (float64x2_t __a, float64x2_t __b)
return vabsq_f64 (__a) < vabsq_f64 (__b);
}
__extension__ static __inline uint32_t __attribute__ ((__always_inline__))
vcalts_f32 (float32_t __a, float32_t __b)
{
return __builtin_fabsf (__a) < __builtin_fabsf (__b) ? -1 : 0;
}
/* vceq - vector. */
__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))

11
gcc/testsuite/ChangeLog
View File

@ -1,3 +1,14 @@
2014-07-01 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* gcc.target/aarch64/simd/vcage_f64.c: New test.
* gcc.target/aarch64/simd/vcagt_f64.c: Likewise.
* gcc.target/aarch64/simd/vcale_f64.c: Likewise.
* gcc.target/aarch64/simd/vcaled_f64.c: Likewise.
* gcc.target/aarch64/simd/vcales_f32.c: Likewise.
* gcc.target/aarch64/simd/vcalt_f64.c: Likewise.
* gcc.target/aarch64/simd/vcaltd_f64.c: Likewise.
* gcc.target/aarch64/simd/vcalts_f32.c: Likewise.
2014-07-01 Paolo Carlini <paolo.carlini@oracle.com>
* g++.dg/cpp1y/pr59867.C: Fix target selector.

38
gcc/testsuite/gcc.target/aarch64/simd/vcage_f64.c Normal file
View File

@ -0,0 +1,38 @@
/* Test the vcage_f64 AArch64 SIMD intrinsic. */
/* { dg-do run } */
/* { dg-options "-save-temps -O3" } */
#include "arm_neon.h"
#define SIZE 6
extern void abort (void);
volatile float64_t in[SIZE] = { -10.4, -3.14, 0.0, 1.5, 5.3, 532.3 };
int
main (void)
{
uint64_t expected;
uint64_t actual;
float64x1_t arg1, arg2;
int i, j;
for (i = 0; i < SIZE; ++i)
for (j = 0; j < SIZE; ++j)
{
expected = __builtin_fabs (in[i]) >= __builtin_fabs (in[j]) ? -1 : 0;
arg1 = (float64x1_t) { in[i] };
arg2 = (float64x1_t) { in[j] };
actual = vget_lane_u64 (vcage_f64 (arg1, arg2), 0);
if (actual != expected)
abort ();
}
return 0;
}
/* { dg-final { scan-assembler "facge\[ \t\]+\[dD\]\[0-9\]+, ?\[dD\]\[0-9\]+, ?\[dD\]\[0-9\]+\n" } } */
/* { dg-final { cleanup-saved-temps } } */

38
gcc/testsuite/gcc.target/aarch64/simd/vcagt_f64.c Normal file
View File

@ -0,0 +1,38 @@
/* Test the vcagt_f64 AArch64 SIMD intrinsic. */
/* { dg-do run } */
/* { dg-options "-save-temps -O3" } */
#include "arm_neon.h"
#define SIZE 6
extern void abort (void);
volatile float64_t in[SIZE] = { -10.4, -3.14, 0.0, 1.5, 5.3, 532.3 };
int
main (void)
{
uint64_t expected;
uint64_t actual;
float64x1_t arg1, arg2;
int i, j;
for (i = 0; i < SIZE; ++i)
for (j = 0; j < SIZE; ++j)
{
expected = __builtin_fabs (in[i]) > __builtin_fabs (in[j]) ? -1 : 0;
arg1 = (float64x1_t) { in[i] };
arg2 = (float64x1_t) { in[j] };
actual = vget_lane_u64 (vcagt_f64 (arg1, arg2), 0);
if (actual != expected)
abort ();
}
return 0;
}
/* { dg-final { scan-assembler "facgt\[ \t\]+\[dD\]\[0-9\]+, ?\[dD\]\[0-9\]+, ?\[dD\]\[0-9\]+\n" } } */
/* { dg-final { cleanup-saved-temps } } */

38
gcc/testsuite/gcc.target/aarch64/simd/vcale_f64.c Normal file
View File

@ -0,0 +1,38 @@
/* Test the vcale_f64 AArch64 SIMD intrinsic. */
/* { dg-do run } */
/* { dg-options "-save-temps -O3" } */
#include "arm_neon.h"
#define SIZE 6
extern void abort (void);
volatile float64_t in[SIZE] = { -10.4, -3.14, 0.0, 1.5, 5.3, 532.3 };
int
main (void)
{
uint64_t expected;
uint64_t actual;
float64x1_t arg1, arg2;
int i, j;
for (i = 0; i < SIZE; ++i)
for (j = 0; j < SIZE; ++j)
{
expected = __builtin_fabs (in[i]) <= __builtin_fabs (in[j]) ? -1 : 0;
arg1 = (float64x1_t) { in[i] };
arg2 = (float64x1_t) { in[j] };
actual = vget_lane_u64 (vcale_f64 (arg1, arg2), 0);
if (actual != expected)
abort ();
}
return 0;
}
/* { dg-final { scan-assembler "facge\[ \t\]+\[dD\]\[0-9\]+, ?\[dD\]\[0-9\]+, ?\[dD\]\[0-9\]+\n" } } */
/* { dg-final { cleanup-saved-temps } } */

36
gcc/testsuite/gcc.target/aarch64/simd/vcaled_f64.c Normal file
View File

@ -0,0 +1,36 @@
/* Test the vcaled_f64 AArch64 SIMD intrinsic. */
/* { dg-do run } */
/* { dg-options "-save-temps -O3" } */
#include "arm_neon.h"
#define SIZE 6
extern void abort (void);
volatile float64_t in[SIZE] = { -10.4, -3.14, 0.0, 1.5, 5.3, 532.3 };
int
main (void)
{
uint64_t expected;
uint64_t actual;
int i, j;
for (i = 0; i < SIZE; ++i)
for (j = 0; j < SIZE; ++j)
{
expected = __builtin_fabs (in[i]) <= __builtin_fabs (in[j]) ? -1 : 0;
actual = vcaled_f64 (in[i], in[j]);
if (actual != expected)
abort ();
}
return 0;
}
/* { dg-final { scan-assembler "facge\[ \t\]+\[dD\]\[0-9\]+, ?\[dD\]\[0-9\]+, ?\[dD\]\[0-9\]+\n" } } */
/* { dg-final { cleanup-saved-temps } } */

36
gcc/testsuite/gcc.target/aarch64/simd/vcales_f32.c Normal file
View File

@ -0,0 +1,36 @@
/* Test the vcales_f32 AArch64 SIMD intrinsic. */
/* { dg-do run } */
/* { dg-options "-save-temps -O3" } */
#include "arm_neon.h"
#define SIZE 6
extern void abort (void);
volatile float32_t in[SIZE] = { -10.4, -3.14, 0.0, 1.5, 5.3, 532.3 };
int
main (void)
{
uint32_t expected;
uint32_t actual;
int i, j;
for (i = 0; i < SIZE; ++i)
for (j = 0; j < SIZE; ++j)
{
expected = __builtin_fabs (in[i]) <= __builtin_fabs (in[j]) ? -1 : 0;
actual = vcales_f32 (in[i], in[j]);
if (actual != expected)
abort ();
}
return 0;
}
/* { dg-final { scan-assembler "facge\[ \t\]+\[sS\]\[0-9\]+, ?\[sS\]\[0-9\]+, ?\[sS\]\[0-9\]+\n" } } */
/* { dg-final { cleanup-saved-temps } } */

38
gcc/testsuite/gcc.target/aarch64/simd/vcalt_f64.c Normal file
View File

@ -0,0 +1,38 @@
/* Test the vcalt_f64 AArch64 SIMD intrinsic. */
/* { dg-do run } */
/* { dg-options "-save-temps -O3" } */
#include "arm_neon.h"
#define SIZE 6
extern void abort (void);
volatile float64_t in[SIZE] = { -10.4, -3.14, 0.0, 1.5, 5.3, 532.3 };
int
main (void)
{
uint64_t expected;
uint64_t actual;
float64x1_t arg1, arg2;
int i, j;
for (i = 0; i < SIZE; ++i)
for (j = 0; j < SIZE; ++j)
{
expected = __builtin_fabs (in[i]) < __builtin_fabs (in[j]) ? -1 : 0;
arg1 = (float64x1_t) { in[i] };
arg2 = (float64x1_t) { in[j] };
actual = vget_lane_u64 (vcalt_f64 (arg1, arg2), 0);
if (actual != expected)
abort ();
}
return 0;
}
/* { dg-final { scan-assembler "facgt\[ \t\]+\[dD\]\[0-9\]+, ?\[dD\]\[0-9\]+, ?\[dD\]\[0-9\]+\n" } } */
/* { dg-final { cleanup-saved-temps } } */

36
gcc/testsuite/gcc.target/aarch64/simd/vcaltd_f64.c Normal file
View File

@ -0,0 +1,36 @@
/* Test the vcaltd_f64 AArch64 SIMD intrinsic. */
/* { dg-do run } */
/* { dg-options "-save-temps -O3" } */
#include "arm_neon.h"
#define SIZE 6
extern void abort (void);
volatile float64_t in[SIZE] = { -10.4, -3.14, 0.0, 1.5, 5.3, 532.3 };
int
main (void)
{
uint64_t expected;
uint64_t actual;
int i, j;
for (i = 0; i < SIZE; ++i)
for (j = 0; j < SIZE; ++j)
{
expected = __builtin_fabs (in[i]) < __builtin_fabs (in[j]) ? -1 : 0;
actual = vcaltd_f64 (in[i], in[j]);
if (actual != expected)
abort ();
}
return 0;
}
/* { dg-final { scan-assembler "facgt\[ \t\]+\[dD\]\[0-9\]+, ?\[dD\]\[0-9\]+, ?\[dD\]\[0-9\]+\n" } } */
/* { dg-final { cleanup-saved-temps } } */

36
gcc/testsuite/gcc.target/aarch64/simd/vcalts_f32.c Normal file
View File

@ -0,0 +1,36 @@
/* Test the vcalts_f32 AArch64 SIMD intrinsic. */
/* { dg-do run } */
/* { dg-options "-save-temps -O3" } */
#include "arm_neon.h"
#define SIZE 6
extern void abort (void);
volatile float32_t in[SIZE] = { -10.4, -3.14, 0.0, 1.5, 5.3, 532.3 };
int
main (void)
{
uint32_t expected;
uint32_t actual;
int i, j;
for (i = 0; i < SIZE; ++i)
for (j = 0; j < SIZE; ++j)
{
expected = __builtin_fabs (in[i]) < __builtin_fabs (in[j]) ? -1 : 0;
actual = vcalts_f32 (in[i], in[j]);
if (actual != expected)
abort ();
}
return 0;
}
/* { dg-final { scan-assembler "facgt\[ \t\]+\[sS\]\[0-9\]+, ?\[sS\]\[0-9\]+, ?\[sS\]\[0-9\]+\n" } } */
/* { dg-final { cleanup-saved-temps } } */