[AArch64] Implement some vca*_f[32,64] intrinsics.
* config/aarch64/arm_neon.h (vcage_f64): New intrinsic. (vcagt_f64): Likewise. (vcale_f64): Likewise. (vcaled_f64): Likewise. (vcales_f32): Likewise. (vcalt_f64): Likewise. (vcaltd_f64): Likewise. (vcalts_f32): Likewise. * gcc.target/aarch64/simd/vcage_f64.c: New test. * gcc.target/aarch64/simd/vcagt_f64.c: Likewise. * gcc.target/aarch64/simd/vcale_f64.c: Likewise. * gcc.target/aarch64/simd/vcaled_f64.c: Likewise. * gcc.target/aarch64/simd/vcales_f32.c: Likewise. * gcc.target/aarch64/simd/vcalt_f64.c: Likewise. * gcc.target/aarch64/simd/vcaltd_f64.c: Likewise. * gcc.target/aarch64/simd/vcalts_f32.c: Likewise. From-SVN: r212196
This commit is contained in:
parent
f280564356
commit
39f9091275
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@ -1,3 +1,14 @@
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2014-07-01 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
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* config/aarch64/arm_neon.h (vcage_f64): New intrinsic.
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(vcagt_f64): Likewise.
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(vcale_f64): Likewise.
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(vcaled_f64): Likewise.
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(vcales_f32): Likewise.
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(vcalt_f64): Likewise.
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(vcaltd_f64): Likewise.
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(vcalts_f32): Likewise.
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2014-07-01 Marek Polacek <polacek@redhat.com>
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* doc/invoke.texi: Document -Wint-conversion.
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@ -13823,6 +13823,12 @@ vaesimcq_u8 (uint8x16_t data)
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/* vcage */
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__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
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vcage_f64 (float64x1_t __a, float64x1_t __b)
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{
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return vabs_f64 (__a) >= vabs_f64 (__b);
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}
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__extension__ static __inline uint32_t __attribute__ ((__always_inline__))
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vcages_f32 (float32_t __a, float32_t __b)
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{
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@ -13867,6 +13873,12 @@ vcagt_f32 (float32x2_t __a, float32x2_t __b)
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return vabs_f32 (__a) > vabs_f32 (__b);
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}
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__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
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vcagt_f64 (float64x1_t __a, float64x1_t __b)
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{
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return vabs_f64 (__a) > vabs_f64 (__b);
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}
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__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
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vcagtq_f32 (float32x4_t __a, float32x4_t __b)
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{
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@ -13893,6 +13905,24 @@ vcale_f32 (float32x2_t __a, float32x2_t __b)
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return vabs_f32 (__a) <= vabs_f32 (__b);
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}
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__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
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vcale_f64 (float64x1_t __a, float64x1_t __b)
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{
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return vabs_f64 (__a) <= vabs_f64 (__b);
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}
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__extension__ static __inline uint64_t __attribute__ ((__always_inline__))
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vcaled_f64 (float64_t __a, float64_t __b)
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{
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return __builtin_fabs (__a) <= __builtin_fabs (__b) ? -1 : 0;
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}
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__extension__ static __inline uint32_t __attribute__ ((__always_inline__))
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vcales_f32 (float32_t __a, float32_t __b)
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{
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return __builtin_fabsf (__a) <= __builtin_fabsf (__b) ? -1 : 0;
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}
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__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
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vcaleq_f32 (float32x4_t __a, float32x4_t __b)
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{
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@ -13913,6 +13943,18 @@ vcalt_f32 (float32x2_t __a, float32x2_t __b)
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return vabs_f32 (__a) < vabs_f32 (__b);
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}
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__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
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vcalt_f64 (float64x1_t __a, float64x1_t __b)
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{
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return vabs_f64 (__a) < vabs_f64 (__b);
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}
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__extension__ static __inline uint64_t __attribute__ ((__always_inline__))
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vcaltd_f64 (float64_t __a, float64_t __b)
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{
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return __builtin_fabs (__a) < __builtin_fabs (__b) ? -1 : 0;
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}
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__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
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vcaltq_f32 (float32x4_t __a, float32x4_t __b)
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{
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@ -13925,6 +13967,12 @@ vcaltq_f64 (float64x2_t __a, float64x2_t __b)
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return vabsq_f64 (__a) < vabsq_f64 (__b);
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}
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__extension__ static __inline uint32_t __attribute__ ((__always_inline__))
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vcalts_f32 (float32_t __a, float32_t __b)
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{
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return __builtin_fabsf (__a) < __builtin_fabsf (__b) ? -1 : 0;
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}
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/* vceq - vector. */
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__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
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2014-07-01 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
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* gcc.target/aarch64/simd/vcage_f64.c: New test.
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* gcc.target/aarch64/simd/vcagt_f64.c: Likewise.
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* gcc.target/aarch64/simd/vcale_f64.c: Likewise.
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* gcc.target/aarch64/simd/vcaled_f64.c: Likewise.
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* gcc.target/aarch64/simd/vcales_f32.c: Likewise.
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* gcc.target/aarch64/simd/vcalt_f64.c: Likewise.
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* gcc.target/aarch64/simd/vcaltd_f64.c: Likewise.
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* gcc.target/aarch64/simd/vcalts_f32.c: Likewise.
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2014-07-01 Paolo Carlini <paolo.carlini@oracle.com>
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* g++.dg/cpp1y/pr59867.C: Fix target selector.
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/* Test the vcage_f64 AArch64 SIMD intrinsic. */
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/* { dg-do run } */
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/* { dg-options "-save-temps -O3" } */
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#include "arm_neon.h"
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#define SIZE 6
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extern void abort (void);
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volatile float64_t in[SIZE] = { -10.4, -3.14, 0.0, 1.5, 5.3, 532.3 };
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int
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main (void)
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{
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uint64_t expected;
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uint64_t actual;
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float64x1_t arg1, arg2;
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int i, j;
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for (i = 0; i < SIZE; ++i)
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for (j = 0; j < SIZE; ++j)
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{
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expected = __builtin_fabs (in[i]) >= __builtin_fabs (in[j]) ? -1 : 0;
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arg1 = (float64x1_t) { in[i] };
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arg2 = (float64x1_t) { in[j] };
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actual = vget_lane_u64 (vcage_f64 (arg1, arg2), 0);
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if (actual != expected)
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abort ();
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}
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return 0;
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}
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/* { dg-final { scan-assembler "facge\[ \t\]+\[dD\]\[0-9\]+, ?\[dD\]\[0-9\]+, ?\[dD\]\[0-9\]+\n" } } */
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/* { dg-final { cleanup-saved-temps } } */
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/* Test the vcagt_f64 AArch64 SIMD intrinsic. */
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/* { dg-do run } */
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/* { dg-options "-save-temps -O3" } */
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#include "arm_neon.h"
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#define SIZE 6
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extern void abort (void);
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volatile float64_t in[SIZE] = { -10.4, -3.14, 0.0, 1.5, 5.3, 532.3 };
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int
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main (void)
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{
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uint64_t expected;
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uint64_t actual;
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float64x1_t arg1, arg2;
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int i, j;
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for (i = 0; i < SIZE; ++i)
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for (j = 0; j < SIZE; ++j)
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{
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expected = __builtin_fabs (in[i]) > __builtin_fabs (in[j]) ? -1 : 0;
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arg1 = (float64x1_t) { in[i] };
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arg2 = (float64x1_t) { in[j] };
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actual = vget_lane_u64 (vcagt_f64 (arg1, arg2), 0);
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if (actual != expected)
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abort ();
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}
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return 0;
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}
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/* { dg-final { scan-assembler "facgt\[ \t\]+\[dD\]\[0-9\]+, ?\[dD\]\[0-9\]+, ?\[dD\]\[0-9\]+\n" } } */
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/* { dg-final { cleanup-saved-temps } } */
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/* Test the vcale_f64 AArch64 SIMD intrinsic. */
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/* { dg-do run } */
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/* { dg-options "-save-temps -O3" } */
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#include "arm_neon.h"
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#define SIZE 6
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extern void abort (void);
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volatile float64_t in[SIZE] = { -10.4, -3.14, 0.0, 1.5, 5.3, 532.3 };
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int
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main (void)
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{
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uint64_t expected;
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uint64_t actual;
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float64x1_t arg1, arg2;
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int i, j;
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for (i = 0; i < SIZE; ++i)
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for (j = 0; j < SIZE; ++j)
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{
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expected = __builtin_fabs (in[i]) <= __builtin_fabs (in[j]) ? -1 : 0;
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arg1 = (float64x1_t) { in[i] };
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arg2 = (float64x1_t) { in[j] };
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actual = vget_lane_u64 (vcale_f64 (arg1, arg2), 0);
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if (actual != expected)
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abort ();
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}
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return 0;
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}
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/* { dg-final { scan-assembler "facge\[ \t\]+\[dD\]\[0-9\]+, ?\[dD\]\[0-9\]+, ?\[dD\]\[0-9\]+\n" } } */
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/* { dg-final { cleanup-saved-temps } } */
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@ -0,0 +1,36 @@
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/* Test the vcaled_f64 AArch64 SIMD intrinsic. */
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/* { dg-do run } */
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/* { dg-options "-save-temps -O3" } */
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#include "arm_neon.h"
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#define SIZE 6
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extern void abort (void);
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volatile float64_t in[SIZE] = { -10.4, -3.14, 0.0, 1.5, 5.3, 532.3 };
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int
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main (void)
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{
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uint64_t expected;
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uint64_t actual;
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int i, j;
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for (i = 0; i < SIZE; ++i)
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for (j = 0; j < SIZE; ++j)
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{
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expected = __builtin_fabs (in[i]) <= __builtin_fabs (in[j]) ? -1 : 0;
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actual = vcaled_f64 (in[i], in[j]);
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if (actual != expected)
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abort ();
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}
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return 0;
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}
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/* { dg-final { scan-assembler "facge\[ \t\]+\[dD\]\[0-9\]+, ?\[dD\]\[0-9\]+, ?\[dD\]\[0-9\]+\n" } } */
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/* { dg-final { cleanup-saved-temps } } */
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@ -0,0 +1,36 @@
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/* Test the vcales_f32 AArch64 SIMD intrinsic. */
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/* { dg-do run } */
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/* { dg-options "-save-temps -O3" } */
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#include "arm_neon.h"
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#define SIZE 6
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extern void abort (void);
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volatile float32_t in[SIZE] = { -10.4, -3.14, 0.0, 1.5, 5.3, 532.3 };
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int
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main (void)
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{
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uint32_t expected;
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uint32_t actual;
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int i, j;
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for (i = 0; i < SIZE; ++i)
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for (j = 0; j < SIZE; ++j)
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{
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expected = __builtin_fabs (in[i]) <= __builtin_fabs (in[j]) ? -1 : 0;
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actual = vcales_f32 (in[i], in[j]);
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if (actual != expected)
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abort ();
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}
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return 0;
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}
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/* { dg-final { scan-assembler "facge\[ \t\]+\[sS\]\[0-9\]+, ?\[sS\]\[0-9\]+, ?\[sS\]\[0-9\]+\n" } } */
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/* { dg-final { cleanup-saved-temps } } */
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@ -0,0 +1,38 @@
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/* Test the vcalt_f64 AArch64 SIMD intrinsic. */
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/* { dg-do run } */
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/* { dg-options "-save-temps -O3" } */
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#include "arm_neon.h"
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#define SIZE 6
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extern void abort (void);
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volatile float64_t in[SIZE] = { -10.4, -3.14, 0.0, 1.5, 5.3, 532.3 };
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int
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main (void)
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{
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uint64_t expected;
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uint64_t actual;
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float64x1_t arg1, arg2;
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int i, j;
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for (i = 0; i < SIZE; ++i)
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for (j = 0; j < SIZE; ++j)
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{
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expected = __builtin_fabs (in[i]) < __builtin_fabs (in[j]) ? -1 : 0;
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arg1 = (float64x1_t) { in[i] };
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arg2 = (float64x1_t) { in[j] };
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actual = vget_lane_u64 (vcalt_f64 (arg1, arg2), 0);
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if (actual != expected)
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abort ();
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}
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return 0;
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}
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/* { dg-final { scan-assembler "facgt\[ \t\]+\[dD\]\[0-9\]+, ?\[dD\]\[0-9\]+, ?\[dD\]\[0-9\]+\n" } } */
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/* { dg-final { cleanup-saved-temps } } */
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/* Test the vcaltd_f64 AArch64 SIMD intrinsic. */
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/* { dg-do run } */
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/* { dg-options "-save-temps -O3" } */
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#include "arm_neon.h"
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#define SIZE 6
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extern void abort (void);
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volatile float64_t in[SIZE] = { -10.4, -3.14, 0.0, 1.5, 5.3, 532.3 };
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int
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main (void)
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{
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uint64_t expected;
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uint64_t actual;
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int i, j;
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for (i = 0; i < SIZE; ++i)
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for (j = 0; j < SIZE; ++j)
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{
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expected = __builtin_fabs (in[i]) < __builtin_fabs (in[j]) ? -1 : 0;
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actual = vcaltd_f64 (in[i], in[j]);
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if (actual != expected)
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abort ();
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}
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return 0;
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}
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/* { dg-final { scan-assembler "facgt\[ \t\]+\[dD\]\[0-9\]+, ?\[dD\]\[0-9\]+, ?\[dD\]\[0-9\]+\n" } } */
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/* { dg-final { cleanup-saved-temps } } */
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@ -0,0 +1,36 @@
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/* Test the vcalts_f32 AArch64 SIMD intrinsic. */
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/* { dg-do run } */
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/* { dg-options "-save-temps -O3" } */
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#include "arm_neon.h"
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#define SIZE 6
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extern void abort (void);
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volatile float32_t in[SIZE] = { -10.4, -3.14, 0.0, 1.5, 5.3, 532.3 };
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int
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main (void)
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{
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uint32_t expected;
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uint32_t actual;
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int i, j;
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for (i = 0; i < SIZE; ++i)
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for (j = 0; j < SIZE; ++j)
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{
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expected = __builtin_fabs (in[i]) < __builtin_fabs (in[j]) ? -1 : 0;
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actual = vcalts_f32 (in[i], in[j]);
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if (actual != expected)
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abort ();
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}
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return 0;
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}
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/* { dg-final { scan-assembler "facgt\[ \t\]+\[sS\]\[0-9\]+, ?\[sS\]\[0-9\]+, ?\[sS\]\[0-9\]+\n" } } */
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/* { dg-final { cleanup-saved-temps } } */
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