Add sh2e support:
2002-08-12 Alexandre Oliva <aoliva@redhat.com> * config/sh/sh.c (output_branch) [TARGET_SH2E]: Handle med_cbranches. Fix logic in short_cbranches. 2002-04-03 Alexandre Oliva <aoliva@redhat.com> * config/sh/sh.md (delay for cbranch): Don't annul delay slots on SH2e. * config/sh/sh.c (sh_insn_length_adjustment): Add 2 for cbranch with unfilled delay slot on SH2e. (output_branch): Fill with a nop the delay slot of a branch that required a delay slot but didn't get one. 2002-04-02 Alexandre Oliva <aoliva@redhat.com> * doc/invoke.texi (SH options): Document -m2e. * config/sh/crt1.asm: Add __SH2E__ Next to __SH3E__. * config/sh/lib1funcs.asm: Likewise. * config/sh/sh.c: Replace all uses of TARGET_SH3E with SH2E. * config/sh/sh.h (CPP_SPEC): Define __SH2E__ for -m2e, and not __sh1__. (CONDITIONAL_REGISTER_USAGE): Don't disable FP regs from SH2E up. (SH3E_BIT): Renamed to... (SH_E_BIT): ... this. Replace all uses. (TARGET_SH2E): Define from SH_E_BIT and TARGET_SH2. Replace all uses of TARGET_SH3E with TARGET_SH2E. (TARGET_SWITCHES): Added 2e. (OVERRIDE_OPTIONS): Set sh_cpu for SH2E. (processor_type): Added PROCESSOR_SH2E. * config/sh/sh.md: Replace all uses of TARGET_SH3E with TARGET_SH2E, except in sqrtsf2_i. (attribute cpu): Added sh2e. * config/sh/t-sh (MULTILIB_OPTIONS): Replace m3e with m2e. (MULTILIB_MATCHES): Use m2e multilib for m3e. * config.gcc: Add sh2e target support. From-SVN: r61697
This commit is contained in:
parent
65ca2d606c
commit
3a8699c7ab
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@ -2207,6 +2207,7 @@ sh-*-elf* | sh[2346l]*-*-elf*)
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sh4*) target_cpu_default="SELECT_SH4" ;;
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sh3e*) target_cpu_default="SELECT_SH3E" ;;
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sh3*) target_cpu_default="SELECT_SH3" ;;
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sh2e*) target_cpu_default="SELECT_SH2E" ;;
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sh2*) target_cpu_default="SELECT_SH2" ;;
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esac
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case $machine in
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@ -2251,6 +2252,9 @@ sh-*-linux* | sh[2346lbe]*-*-linux*)
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sh3e[lb]*) target_cpu_default="SELECT_SH3" ;;
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sh3e*) target_cpu_default="SELECT_SH3E" ;;
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sh3*) target_cpu_default="SELECT_SH3" ;;
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sh2e[lb]e*) target_cpu_default="SELECT_SH2E" ;;
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sh2e[lb]*) target_cpu_default="SELECT_SH2" ;;
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sh2e*) target_cpu_default="SELECT_SH2E" ;;
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sh2*) target_cpu_default="SELECT_SH2" ;;
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esac
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case $machine in
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@ -2273,7 +2277,7 @@ sh-*-netbsdelf* | shl*-*-netbsdelf* | sh5-*-netbsd* | sh5l*-*-netbsd* | \
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case $machine in
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sh5*-*)
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# SHmedia, 32-bit ABI
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target_cpu_default="SH5_BIT|SH4_BIT|SH3E_BIT"
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target_cpu_default="SH5_BIT|SH4_BIT|SH3_BIT|SH_E_BIT"
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tmake_file="${tmake_file} sh/t-sh64 sh/t-netbsd-sh5"
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;;
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sh64*-*)
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@ -1,4 +1,4 @@
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/* Copyright (C) 2000, 2001 Free Software Foundation, Inc.
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/* Copyright (C) 2000, 2001, 2003 Free Software Foundation, Inc.
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This file was pretty much copied from newlib.
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This file is part of GNU CC.
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@ -116,12 +116,12 @@ start_l:
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cmp/ge r0,r1
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bt start_l
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#if defined (__SH3E__) || defined(__SH4_SINGLE__) || defined(__SH4__) || defined(__SH4_SINGLE_ONLY__)
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#if defined (__SH2E__) || defined (__SH3E__) || defined(__SH4_SINGLE__) || defined(__SH4__) || defined(__SH4_SINGLE_ONLY__)
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mov.l set_fpscr_k, r1
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jsr @r1
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mov #0,r4
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lds r3,fpscr
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#endif /* defined (__SH3E__) || defined(__SH4_SINGLE__) || defined(__SH4__) || defined(__SH4_SINGLE_ONLY__) */
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#endif /* defined (__SH2E__) || defined (__SH3E__) || defined(__SH4_SINGLE__) || defined(__SH4__) || defined(__SH4_SINGLE_ONLY__) */
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! arrange for exit to call fini
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mov.l atexit_k,r0
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@ -146,10 +146,11 @@ start_l:
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nop
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.align 2
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#if defined (__SH3E__) || defined(__SH4_SINGLE__) || defined(__SH4__) || defined(__SH4_SINGLE_ONLY__)
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#if defined (__SH2E__) || defined (__SH3E__) || defined(__SH4_SINGLE__) || defined(__SH4__) || defined(__SH4_SINGLE_ONLY__)
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set_fpscr_k:
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.long ___set_fpscr
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#endif /* defined (__SH3E__) || defined(__SH4_SINGLE__) || defined(__SH4__) || defined(__SH4_SINGLE_ONLY__) */
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#endif /* defined (__SH2E__) || defined (__SH3E__) || defined(__SH4_SINGLE__) || defined(__SH4__) || defined(__SH4_SINGLE_ONLY__) */
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stack_k:
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.long _stack
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edata_k:
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@ -1,4 +1,4 @@
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/* Copyright (C) 1994, 1995, 1997, 1998, 1999, 2000, 2001, 2002
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/* Copyright (C) 1994, 1995, 1997, 1998, 1999, 2000, 2001, 2002, 2003
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Free Software Foundation, Inc.
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This file is free software; you can redistribute it and/or modify it
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@ -1044,7 +1044,7 @@ GLOBAL(sdivsi3_i4):
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#ifdef L_sdivsi3
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/* __SH4_SINGLE_ONLY__ keeps this part for link compatibility with
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sh3e code. */
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sh2e/sh3e code. */
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#if (! defined(__SH4__) && ! defined (__SH4_SINGLE__)) || defined (__linux__)
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!!
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!! Steve Chamberlain
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@ -1433,7 +1433,7 @@ L1:
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#ifdef L_udivsi3
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/* __SH4_SINGLE_ONLY__ keeps this part for link compatibility with
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sh3e code. */
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sh2e/sh3e code. */
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#if (! defined(__SH4__) && ! defined (__SH4_SINGLE__)) || defined (__linux__)
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!! args in r4 and r5, result in r0, clobbers r4, pr, and t bit
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@ -1928,7 +1928,7 @@ GLOBAL(moddi3):
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#endif /* L_moddi3 */
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#ifdef L_set_fpscr
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#if defined (__SH3E__) || defined(__SH4_SINGLE__) || defined(__SH4__) || defined(__SH4_SINGLE_ONLY__) || __SH5__ == 32
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#if defined (__SH2E__) || defined (__SH3E__) || defined(__SH4_SINGLE__) || defined(__SH4__) || defined(__SH4_SINGLE_ONLY__) || __SH5__ == 32
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#ifdef __SH5__
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.mode SHcompact
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#endif
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@ -1945,7 +1945,7 @@ GLOBAL(set_fpscr):
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#if defined(__SH4__)
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swap.w r0,r3
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mov.l r3,@(4,r1)
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#else /* defined(__SH3E__) || defined(__SH4_SINGLE*__) */
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#else /* defined (__SH2E__) || defined(__SH3E__) || defined(__SH4_SINGLE*__) */
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swap.w r0,r2
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mov.l r2,@r1
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#endif
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@ -1958,7 +1958,7 @@ GLOBAL(set_fpscr):
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swap.w r0,r2
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rts
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mov.l r2,@r1
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#else /* defined(__SH3E__) || defined(__SH4_SINGLE*__) */
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#else /* defined(__SH2E__) || defined(__SH3E__) || defined(__SH4_SINGLE*__) */
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swap.w r0,r3
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rts
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mov.l r3,@(4,r1)
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@ -1975,7 +1975,7 @@ LOCAL(set_fpscr_L1):
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.comm GLOBAL(fpscr_values),8
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#endif /* ELF */
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#endif /* NO_FPSCR_VALUES */
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#endif /* SH3E / SH4 */
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#endif /* SH2E / SH3E / SH4 */
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#endif /* L_set_fpscr */
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#ifdef L_ic_invalidate
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#if __SH5__ == 32
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@ -1,5 +1,5 @@
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/* Output routines for GCC for Hitachi / SuperH SH.
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Copyright (C) 1993, 1994, 1995, 1997, 1997, 1998, 1999, 2000, 2001, 2002
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Copyright (C) 1993, 1994, 1995, 1997, 1997, 1998, 1999, 2000, 2001, 2002, 2003
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Free Software Foundation, Inc.
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Contributed by Steve Chamberlain (sac@cygnus.com).
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Improved by Jim Wilson (wilson@cygnus.com).
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@ -794,7 +794,7 @@ prepare_scc_operands (code)
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&& (sh_compare_op1 != const0_rtx
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|| code == GTU || code == GEU || code == LTU || code == LEU))
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|| (mode == DImode && sh_compare_op1 != const0_rtx)
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|| (TARGET_SH3E && GET_MODE_CLASS (mode) == MODE_FLOAT))
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|| (TARGET_SH2E && GET_MODE_CLASS (mode) == MODE_FLOAT))
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sh_compare_op1 = force_reg (mode, sh_compare_op1);
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if (TARGET_SH4 && GET_MODE_CLASS (mode) == MODE_FLOAT)
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@ -825,16 +825,16 @@ from_compare (operands, code)
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mode = GET_MODE (sh_compare_op1);
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if (code != EQ
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|| mode == DImode
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|| (TARGET_SH3E && GET_MODE_CLASS (mode) == MODE_FLOAT))
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|| (TARGET_SH2E && GET_MODE_CLASS (mode) == MODE_FLOAT))
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{
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/* Force args into regs, since we can't use constants here. */
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sh_compare_op0 = force_reg (mode, sh_compare_op0);
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if (sh_compare_op1 != const0_rtx
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|| code == GTU || code == GEU
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|| (TARGET_SH3E && GET_MODE_CLASS (mode) == MODE_FLOAT))
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|| (TARGET_SH2E && GET_MODE_CLASS (mode) == MODE_FLOAT))
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sh_compare_op1 = force_reg (mode, sh_compare_op1);
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}
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if (TARGET_SH3E && GET_MODE_CLASS (mode) == MODE_FLOAT && code == GE)
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if (TARGET_SH2E && GET_MODE_CLASS (mode) == MODE_FLOAT && code == GE)
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{
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from_compare (operands, GT);
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insn = gen_ieee_ccmpeqsf_t (sh_compare_op0, sh_compare_op1);
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will fix it up if it still doesn't fit after relaxation. */
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case 2:
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return logic ? "bt%.\t%l0" : "bf%.\t%l0";
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/* These are for SH2e, in which we have to account for the
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extra nop because of the hardware bug in annulled branches. */
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case 8:
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if (! TARGET_RELAX)
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{
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int label = lf++;
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if (final_sequence
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&& INSN_ANNULLED_BRANCH_P (XVECEXP (final_sequence, 0, 0)))
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abort ();
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asm_fprintf (asm_out_file, "b%s%ss\t%LLF%d\n",
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logic ? "f" : "t",
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ASSEMBLER_DIALECT ? "/" : ".", label);
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fprintf (asm_out_file, "\tnop\n");
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output_asm_insn ("bra\t%l0", operands);
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fprintf (asm_out_file, "\tnop\n");
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(*targetm.asm_out.internal_label) (asm_out_file, "LF", label);
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return "";
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}
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/* When relaxing, fall through. */
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case 4:
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{
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char buffer[10];
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sprintf (buffer, "b%s%ss\t%%l0",
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logic ? "t" : "f",
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ASSEMBLER_DIALECT ? "/" : ".");
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output_asm_insn (buffer, &operands[0]);
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return "nop";
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}
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default:
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/* There should be no longer branches now - that would
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indicate that something has destroyed the branches set
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@ -1945,7 +1978,7 @@ shl_sext_kind (left_rtx, size_rtx, costp)
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int *costp;
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{
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int left, size, insize, ext;
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int cost, best_cost;
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int cost = 0, best_cost;
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int kind;
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left = INTVAL (left_rtx);
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@ -2559,7 +2592,7 @@ broken_move (insn)
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|| (GET_CODE (SET_SRC (pat)) == UNSPEC
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&& XINT (SET_SRC (pat), 1) == UNSPEC_MOVA
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&& GET_CODE (XVECEXP (SET_SRC (pat), 0, 0)) == CONST))
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&& ! (TARGET_SH3E
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&& ! (TARGET_SH2E
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&& GET_CODE (SET_SRC (pat)) == CONST_DOUBLE
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&& (fp_zero_operand (SET_SRC (pat))
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|| fp_one_operand (SET_SRC (pat)))
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@ -2612,7 +2645,7 @@ find_barrier (num_mova, mova, from)
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int hi_align = 2;
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int si_align = 2;
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int leading_mova = num_mova;
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rtx barrier_before_mova, found_barrier = 0, good_barrier = 0;
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rtx barrier_before_mova = 0, found_barrier = 0, good_barrier = 0;
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int si_limit;
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int hi_limit;
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@ -3291,7 +3324,7 @@ barrier_align (barrier_or_label)
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rtx barrier_or_label;
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{
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rtx next = next_real_insn (barrier_or_label), pat, prev;
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int slot, credit, jump_to_next;
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int slot, credit, jump_to_next = 0;
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if (! next)
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return 0;
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@ -3437,7 +3470,7 @@ void
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machine_dependent_reorg (first)
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rtx first;
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{
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rtx insn, mova;
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rtx insn, mova = NULL_RTX;
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int num_mova;
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rtx r0_rtx = gen_rtx_REG (Pmode, 0);
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rtx r0_inc_rtx = gen_rtx_POST_INC (Pmode, r0_rtx);
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@ -3732,7 +3765,7 @@ machine_dependent_reorg (first)
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/* Scan ahead looking for a barrier to stick the constant table
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behind. */
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rtx barrier = find_barrier (num_mova, mova, insn);
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rtx last_float_move, last_float = 0, *last_float_addr;
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rtx last_float_move = NULL_RTX, last_float = 0, *last_float_addr = NULL;
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if (num_mova && ! mova_p (mova))
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{
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@ -4321,7 +4354,7 @@ push (rn)
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return NULL_RTX;
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x = gen_push_4 (gen_rtx_REG (DFmode, rn));
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}
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else if (TARGET_SH3E && FP_REGISTER_P (rn))
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else if (TARGET_SH2E && FP_REGISTER_P (rn))
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x = gen_push_e (gen_rtx_REG (SFmode, rn));
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else
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x = gen_push (gen_rtx_REG (SImode, rn));
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@ -4351,7 +4384,7 @@ pop (rn)
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return;
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x = gen_pop_4 (gen_rtx_REG (DFmode, rn));
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}
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else if (TARGET_SH3E && FP_REGISTER_P (rn))
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else if (TARGET_SH2E && FP_REGISTER_P (rn))
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x = gen_pop_e (gen_rtx_REG (SFmode, rn));
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else
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x = gen_pop (gen_rtx_REG (SImode, rn));
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@ -4590,8 +4623,8 @@ sh_expand_prologue ()
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/* Emit the code for SETUP_VARARGS. */
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if (current_function_stdarg)
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{
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/* This is not used by the SH3E calling convention */
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if (TARGET_SH1 && ! TARGET_SH3E && ! TARGET_SH5 && ! TARGET_HITACHI)
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/* This is not used by the SH2E calling convention */
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if (TARGET_SH1 && ! TARGET_SH2E && ! TARGET_SH5 && ! TARGET_HITACHI)
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{
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/* Push arg regs as if they'd been provided by caller in stack. */
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for (i = 0; i < NPARM_REGS(SImode); i++)
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@ -5246,7 +5279,7 @@ sh_builtin_saveregs ()
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return const0_rtx;
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}
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if (! TARGET_SH3E && ! TARGET_SH4 && ! TARGET_SH5)
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if (! TARGET_SH2E && ! TARGET_SH4 && ! TARGET_SH5)
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{
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error ("__builtin_saveregs not supported by this subtarget");
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return const0_rtx;
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@ -5349,7 +5382,7 @@ sh_build_va_list ()
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tree f_next_o, f_next_o_limit, f_next_fp, f_next_fp_limit, f_next_stack;
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tree record;
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if (TARGET_SH5 || (! TARGET_SH3E && ! TARGET_SH4) || TARGET_HITACHI)
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if (TARGET_SH5 || (! TARGET_SH2E && ! TARGET_SH4) || TARGET_HITACHI)
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return ptr_type_node;
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record = make_node (RECORD_TYPE);
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@ -5403,7 +5436,7 @@ sh_va_start (valist, nextarg)
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return;
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}
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if ((! TARGET_SH3E && ! TARGET_SH4) || TARGET_HITACHI)
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if ((! TARGET_SH2E && ! TARGET_SH4) || TARGET_HITACHI)
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{
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std_expand_builtin_va_start (valist, nextarg);
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return;
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@ -5481,7 +5514,7 @@ sh_va_arg (valist, type)
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if (pass_by_ref)
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type = build_pointer_type (type);
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if (! TARGET_SH5 && (TARGET_SH3E || TARGET_SH4) && ! TARGET_HITACHI)
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if (! TARGET_SH5 && (TARGET_SH2E || TARGET_SH4) && ! TARGET_HITACHI)
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{
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tree f_next_o, f_next_o_limit, f_next_fp, f_next_fp_limit, f_next_stack;
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tree next_o, next_o_limit, next_fp, next_fp_limit, next_stack;
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@ -6877,6 +6910,16 @@ sh_insn_length_adjustment (insn)
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&& get_attr_needs_delay_slot (insn) == NEEDS_DELAY_SLOT_YES)
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return 2;
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/* SH2e has a bug that prevents the use of annulled branches, so if
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the delay slot is not filled, we'll have to put a NOP in it. */
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if (sh_cpu == CPU_SH2E
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&& GET_CODE (insn) == JUMP_INSN
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&& GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC
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&& GET_CODE (PATTERN (insn)) != ADDR_VEC
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&& get_attr_type (insn) == TYPE_CBRANCH
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&& GET_CODE (PATTERN (NEXT_INSN (PREV_INSN (insn)))) != SEQUENCE)
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return 2;
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/* sh-dsp parallel processing insn take four bytes instead of two. */
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|
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if (GET_CODE (insn) == INSN)
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|
|
|
@ -45,6 +45,9 @@ do { \
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case PROCESSOR_SH2: \
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builtin_define ("__sh2__"); \
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break; \
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case PROCESSOR_SH2E: \
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builtin_define ("__SH2E__"); \
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break; \
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case PROCESSOR_SH3: \
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builtin_define ("__sh3__"); \
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builtin_define ("__SH3__"); \
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||||
|
@ -132,7 +135,7 @@ extern int target_flags;
|
|||
#define SH1_BIT (1<<8)
|
||||
#define SH2_BIT (1<<9)
|
||||
#define SH3_BIT (1<<10)
|
||||
#define SH3E_BIT (1<<11)
|
||||
#define SH_E_BIT (1<<11)
|
||||
#define HARD_SH4_BIT (1<<5)
|
||||
#define FPU_SINGLE_BIT (1<<7)
|
||||
#define SH4_BIT (1<<12)
|
||||
|
@ -161,11 +164,14 @@ extern int target_flags;
|
|||
/* Nonzero if we should generate code using type 2 insns. */
|
||||
#define TARGET_SH2 (target_flags & SH2_BIT)
|
||||
|
||||
/* Nonzero if we should generate code using type 2E insns. */
|
||||
#define TARGET_SH2E ((target_flags & SH_E_BIT) && TARGET_SH2)
|
||||
|
||||
/* Nonzero if we should generate code using type 3 insns. */
|
||||
#define TARGET_SH3 (target_flags & SH3_BIT)
|
||||
|
||||
/* Nonzero if we should generate code using type 3E insns. */
|
||||
#define TARGET_SH3E ((target_flags & SH3E_BIT) && (target_flags & SH1_BIT))
|
||||
#define TARGET_SH3E ((target_flags & SH_E_BIT) && TARGET_SH3)
|
||||
|
||||
/* Nonzero if the cache line size is 32. */
|
||||
#define TARGET_CACHE32 (target_flags & HARD_SH4_BIT || TARGET_SH5)
|
||||
|
@ -186,7 +192,7 @@ extern int target_flags;
|
|||
#define TARGET_FPU_DOUBLE (target_flags & SH4_BIT)
|
||||
|
||||
/* Nonzero if an FPU is available. */
|
||||
#define TARGET_FPU_ANY (TARGET_SH3E || TARGET_FPU_DOUBLE)
|
||||
#define TARGET_FPU_ANY (TARGET_SH2E || TARGET_FPU_DOUBLE)
|
||||
|
||||
/* Nonzero if we should generate code using type 4 insns. */
|
||||
#define TARGET_SH4 ((target_flags & SH4_BIT) && (target_flags & SH1_BIT))
|
||||
|
@ -205,12 +211,12 @@ extern int target_flags;
|
|||
/* Nonzero if we should generate code using the SHmedia ISA and 32-bit
|
||||
ABI. */
|
||||
#define TARGET_SHMEDIA32 (TARGET_SH5 && ! TARGET_SH1 \
|
||||
&& (target_flags & SH3E_BIT))
|
||||
&& (target_flags & SH_E_BIT))
|
||||
|
||||
/* Nonzero if we should generate code using the SHmedia ISA and 64-bit
|
||||
ABI. */
|
||||
#define TARGET_SHMEDIA64 (TARGET_SH5 && ! TARGET_SH1 \
|
||||
&& ! (target_flags & SH3E_BIT))
|
||||
&& ! (target_flags & SH_E_BIT))
|
||||
|
||||
/* Nonzero if we should generate code using SHmedia FPU instructions. */
|
||||
#define TARGET_SHMEDIA_FPU (TARGET_SHMEDIA && TARGET_FPU_DOUBLE)
|
||||
|
@ -252,42 +258,45 @@ extern int target_flags;
|
|||
/* Nonzero if we should prefer @GOT calls when generating PIC. */
|
||||
#define TARGET_PREFERGOT (target_flags & PREFERGOT_BIT)
|
||||
|
||||
#define SELECT_SH1 (SH1_BIT)
|
||||
#define SELECT_SH2 (SH2_BIT | SELECT_SH1)
|
||||
#define SELECT_SH3 (SH3_BIT | SELECT_SH2)
|
||||
#define SELECT_SH3E (SH3E_BIT | FPU_SINGLE_BIT | SELECT_SH3)
|
||||
#define SELECT_SH4_NOFPU (HARD_SH4_BIT | SELECT_SH3)
|
||||
#define SELECT_SH4_SINGLE_ONLY (HARD_SH4_BIT | SELECT_SH3E)
|
||||
#define SELECT_SH4 (SH4_BIT|SH3E_BIT|HARD_SH4_BIT | SELECT_SH3)
|
||||
#define SELECT_SH4_SINGLE (FPU_SINGLE_BIT | SELECT_SH4)
|
||||
#define SELECT_SH5_64 (SH5_BIT | SH4_BIT)
|
||||
#define SELECT_SH5_64_NOFPU (SH5_BIT)
|
||||
#define SELECT_SH5_32 (SH5_BIT | SH4_BIT | SH3E_BIT)
|
||||
#define SELECT_SH5_32_NOFPU (SH5_BIT | SH3E_BIT)
|
||||
#define SELECT_SH5_COMPACT (SH5_BIT | SH4_BIT | SELECT_SH3E)
|
||||
#define SELECT_SH1 (SH1_BIT)
|
||||
#define SELECT_SH2 (SH2_BIT | SELECT_SH1)
|
||||
#define SELECT_SH2E (SH_E_BIT | SH2_BIT | SH1_BIT | FPU_SINGLE_BIT)
|
||||
#define SELECT_SH3 (SH3_BIT | SELECT_SH2)
|
||||
#define SELECT_SH3E (SH_E_BIT | FPU_SINGLE_BIT | SELECT_SH3)
|
||||
#define SELECT_SH4_NOFPU (HARD_SH4_BIT | SELECT_SH3)
|
||||
#define SELECT_SH4_SINGLE_ONLY (HARD_SH4_BIT | SELECT_SH3E)
|
||||
#define SELECT_SH4 (SH4_BIT | SH_E_BIT | HARD_SH4_BIT | SELECT_SH3)
|
||||
#define SELECT_SH4_SINGLE (FPU_SINGLE_BIT | SELECT_SH4)
|
||||
#define SELECT_SH5_64 (SH5_BIT | SH4_BIT)
|
||||
#define SELECT_SH5_64_NOFPU (SH5_BIT)
|
||||
#define SELECT_SH5_32 (SH5_BIT | SH4_BIT | SH_E_BIT)
|
||||
#define SELECT_SH5_32_NOFPU (SH5_BIT | SH_E_BIT)
|
||||
#define SELECT_SH5_COMPACT (SH5_BIT | SH4_BIT | SELECT_SH3E)
|
||||
#define SELECT_SH5_COMPACT_NOFPU (SH5_BIT | SELECT_SH3)
|
||||
|
||||
/* Reset all target-selection flags. */
|
||||
#define TARGET_NONE -(SH1_BIT | SH2_BIT | SH3_BIT | SH3E_BIT | SH4_BIT \
|
||||
#define TARGET_NONE -(SH1_BIT | SH2_BIT | SH3_BIT | SH_E_BIT | SH4_BIT \
|
||||
| HARD_SH4_BIT | FPU_SINGLE_BIT | SH5_BIT)
|
||||
|
||||
#define TARGET_SWITCHES \
|
||||
{ {"1", TARGET_NONE, "" }, \
|
||||
{"1", SELECT_SH1, "" }, \
|
||||
{"1", SELECT_SH1, "" }, \
|
||||
{"2", TARGET_NONE, "" }, \
|
||||
{"2", SELECT_SH2, "" }, \
|
||||
{"2e", TARGET_NONE, "" }, \
|
||||
{"2e", SELECT_SH2E, "" }, \
|
||||
{"3", TARGET_NONE, "" }, \
|
||||
{"3", SELECT_SH3, "" }, \
|
||||
{"3", SELECT_SH3, "" }, \
|
||||
{"3e", TARGET_NONE, "" }, \
|
||||
{"3e", SELECT_SH3E, "" }, \
|
||||
{"3e", SELECT_SH3E, "" }, \
|
||||
{"4-single-only", TARGET_NONE, "" }, \
|
||||
{"4-single-only", SELECT_SH4_SINGLE_ONLY, "" }, \
|
||||
{"4-single", TARGET_NONE, "" }, \
|
||||
{"4-single", SELECT_SH4_SINGLE, "" },\
|
||||
{"4-single", SELECT_SH4_SINGLE, "" }, \
|
||||
{"4-nofpu", TARGET_NONE, "" }, \
|
||||
{"4-nofpu", SELECT_SH4_NOFPU, "" },\
|
||||
{"4-nofpu", SELECT_SH4_NOFPU, "" }, \
|
||||
{"4", TARGET_NONE, "" }, \
|
||||
{"4", SELECT_SH4, "" }, \
|
||||
{"4", SELECT_SH4, "" }, \
|
||||
{"5-64media", TARGET_NONE, "" }, \
|
||||
{"5-64media", SELECT_SH5_64, "Generate 64-bit SHmedia code" }, \
|
||||
{"5-64media-nofpu", TARGET_NONE, "" }, \
|
||||
|
@ -365,11 +374,11 @@ extern int target_flags;
|
|||
#define LINK_EMUL_PREFIX "sh%{ml:l}"
|
||||
|
||||
#if TARGET_CPU_DEFAULT & SH5_BIT
|
||||
#if TARGET_CPU_DEFAULT & SH3E_BIT
|
||||
#if TARGET_CPU_DEFAULT & SH_E_BIT
|
||||
#define LINK_DEFAULT_CPU_EMUL "32"
|
||||
#else
|
||||
#define LINK_DEFAULT_CPU_EMUL "64"
|
||||
#endif /* SH3E_BIT */
|
||||
#endif /* SH_E_BIT */
|
||||
#else
|
||||
#define LINK_DEFAULT_CPU_EMUL ""
|
||||
#endif /* SH5_BIT */
|
||||
|
@ -409,6 +418,8 @@ do { \
|
|||
assembler_dialect = 0; \
|
||||
if (TARGET_SH2) \
|
||||
sh_cpu = CPU_SH2; \
|
||||
if (TARGET_SH2E) \
|
||||
sh_cpu = CPU_SH2E; \
|
||||
if (TARGET_SH3) \
|
||||
sh_cpu = CPU_SH3; \
|
||||
if (TARGET_SH3E) \
|
||||
|
@ -737,7 +748,7 @@ extern char sh_additional_register_names[ADDREGNAMES_SIZE] \
|
|||
#define LAST_GENERAL_REG (FIRST_GENERAL_REG + (TARGET_SHMEDIA ? 63 : 15))
|
||||
#define FIRST_FP_REG DR0_REG
|
||||
#define LAST_FP_REG (FIRST_FP_REG + \
|
||||
(TARGET_SHMEDIA_FPU ? 63 : TARGET_SH3E ? 15 : -1))
|
||||
(TARGET_SHMEDIA_FPU ? 63 : TARGET_SH2E ? 15 : -1))
|
||||
#define FIRST_XD_REG XD0_REG
|
||||
#define LAST_XD_REG (FIRST_XD_REG + ((TARGET_SH4 && TARGET_FMOVD) ? 7 : -1))
|
||||
#define FIRST_TARGET_REG TR0_REG
|
||||
|
@ -778,7 +789,7 @@ extern char sh_additional_register_names[ADDREGNAMES_SIZE] \
|
|||
(SHMEDIA_REGISTER_P (REGNO) || XD_REGISTER_P (REGNO) \
|
||||
|| (REGNO) == AP_REG || (REGNO) == RAP_REG \
|
||||
|| (TARGET_SH1 && (SPECIAL_REGISTER_P (REGNO) || (REGNO) == PR_REG)) \
|
||||
|| (TARGET_SH3E && (REGNO) == FPUL_REG))
|
||||
|| (TARGET_SH2E && (REGNO) == FPUL_REG))
|
||||
|
||||
/* The mode that should be generally used to store a register by
|
||||
itself in the stack, or to load it back. */
|
||||
|
@ -927,7 +938,7 @@ extern char sh_additional_register_names[ADDREGNAMES_SIZE] \
|
|||
: (REGNO) == FIRST_XD_REG) \
|
||||
: FP_REGISTER_P (REGNO) \
|
||||
? ((MODE) == SFmode || (MODE) == SImode \
|
||||
|| ((TARGET_SH3E || TARGET_SHMEDIA) && (MODE) == SCmode) \
|
||||
|| ((TARGET_SH2E || TARGET_SHMEDIA) && (MODE) == SCmode) \
|
||||
|| (((TARGET_SH4 && (MODE) == DFmode) || (MODE) == DCmode \
|
||||
|| (TARGET_SHMEDIA && ((MODE) == DFmode || (MODE) == DImode \
|
||||
|| (MODE) == V2SFmode || (MODE) == TImode))) \
|
||||
|
@ -1468,7 +1479,7 @@ extern enum reg_class reg_class_from_letter[];
|
|||
: FIRST_RET_REG)
|
||||
|
||||
#define BASE_ARG_REG(MODE) \
|
||||
((TARGET_SH3E && ((MODE) == SFmode)) \
|
||||
((TARGET_SH2E && ((MODE) == SFmode)) \
|
||||
? FIRST_FP_PARM_REG \
|
||||
: TARGET_SH4 && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
|
||||
|| GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT)\
|
||||
|
@ -1504,7 +1515,7 @@ extern enum reg_class reg_class_from_letter[];
|
|||
|
||||
/* 1 if N is a possible register number for a function value. */
|
||||
#define FUNCTION_VALUE_REGNO_P(REGNO) \
|
||||
((REGNO) == FIRST_RET_REG || (TARGET_SH3E && (REGNO) == FIRST_FP_RET_REG) \
|
||||
((REGNO) == FIRST_RET_REG || (TARGET_SH2E && (REGNO) == FIRST_FP_RET_REG) \
|
||||
|| (TARGET_SHMEDIA_FPU && (REGNO) == FIRST_FP_RET_REG))
|
||||
|
||||
/* 1 if N is a possible register number for function argument passing. */
|
||||
|
@ -1838,7 +1849,7 @@ struct sh_args {
|
|||
|| (! TREE_ADDRESSABLE ((tree)(TYPE)) \
|
||||
&& (! TARGET_HITACHI || ! AGGREGATE_TYPE_P (TYPE)))) \
|
||||
&& ! (CUM).force_mem \
|
||||
&& (TARGET_SH3E \
|
||||
&& (TARGET_SH2E \
|
||||
? ((MODE) == BLKmode \
|
||||
? (((CUM).arg_count[(int) SH_ARG_INT] * UNITS_PER_WORD \
|
||||
+ int_size_in_bytes (TYPE)) \
|
||||
|
@ -2181,7 +2192,7 @@ while (0)
|
|||
|| TARGET_SHMEDIA64) \
|
||||
: (GET_CODE (X) != CONST_DOUBLE \
|
||||
|| GET_MODE (X) == DFmode || GET_MODE (X) == SFmode \
|
||||
|| (TARGET_SH3E && (fp_zero_operand (X) || fp_one_operand (X)))))
|
||||
|| (TARGET_SH2E && (fp_zero_operand (X) || fp_one_operand (X)))))
|
||||
|
||||
/* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
|
||||
and check its validity for a certain class.
|
||||
|
@ -2336,7 +2347,7 @@ while (0)
|
|||
|
||||
#define MODE_DISP_OK_4(X,MODE) \
|
||||
(GET_MODE_SIZE (MODE) == 4 && (unsigned) INTVAL (X) < 64 \
|
||||
&& ! (INTVAL (X) & 3) && ! (TARGET_SH3E && (MODE) == SFmode))
|
||||
&& ! (INTVAL (X) & 3) && ! (TARGET_SH2E && (MODE) == SFmode))
|
||||
|
||||
#define MODE_DISP_OK_8(X,MODE) \
|
||||
((GET_MODE_SIZE(MODE)==8) && ((unsigned)INTVAL(X)<60) \
|
||||
|
@ -2367,7 +2378,7 @@ while (0)
|
|||
REG++
|
||||
--REG */
|
||||
|
||||
/* ??? The SH3e does not have the REG+disp addressing mode when loading values
|
||||
/* ??? The SH2e does not have the REG+disp addressing mode when loading values
|
||||
into the FRx registers. We implement this by setting the maximum offset
|
||||
to zero when the value is SFmode. This also restricts loading of SFmode
|
||||
values into the integer registers, but that can't be helped. */
|
||||
|
@ -2453,7 +2464,7 @@ while (0)
|
|||
&& BASE_REGISTER_RTX_P (XEXP ((X), 0)) \
|
||||
&& ! TARGET_SHMEDIA \
|
||||
&& ! (TARGET_SH4 && (MODE) == DFmode) \
|
||||
&& ! (TARGET_SH3E && (MODE) == SFmode)) \
|
||||
&& ! (TARGET_SH2E && (MODE) == SFmode)) \
|
||||
{ \
|
||||
rtx index_rtx = XEXP ((X), 1); \
|
||||
HOST_WIDE_INT offset = INTVAL (index_rtx), offset_base; \
|
||||
|
@ -2508,7 +2519,7 @@ while (0)
|
|||
HOST_WIDE_INT offset = INTVAL (index_rtx), offset_base; \
|
||||
rtx sum; \
|
||||
\
|
||||
if (TARGET_SH3E && MODE == SFmode) \
|
||||
if (TARGET_SH2E && MODE == SFmode) \
|
||||
{ \
|
||||
X = copy_rtx (X); \
|
||||
push_reload (index_rtx, NULL_RTX, &XEXP (X, 1), NULL, \
|
||||
|
@ -2547,7 +2558,7 @@ while (0)
|
|||
&& BASE_REGISTER_RTX_P (XEXP (XEXP (X, 0), 0)) \
|
||||
&& GET_CODE (XEXP (X, 1)) == CONST_INT \
|
||||
&& ! TARGET_SHMEDIA \
|
||||
&& ! (TARGET_SH3E && MODE == SFmode)) \
|
||||
&& ! (TARGET_SH2E && MODE == SFmode)) \
|
||||
{ \
|
||||
/* Because this address is so complex, we know it must have \
|
||||
been created by LEGITIMIZE_RELOAD_ADDRESS before; thus, \
|
||||
|
@ -2593,9 +2604,9 @@ while (0)
|
|||
/* Define it here, so that it doesn't get bumped to 64-bits on SHmedia. */
|
||||
#define FLOAT_TYPE_SIZE 32
|
||||
|
||||
/* Since the SH3e has only `float' support, it is desirable to make all
|
||||
/* Since the SH2e has only `float' support, it is desirable to make all
|
||||
floating point types equivalent to `float'. */
|
||||
#define DOUBLE_TYPE_SIZE ((TARGET_SH3E && ! TARGET_SH4) ? 32 : 64)
|
||||
#define DOUBLE_TYPE_SIZE ((TARGET_SH2E && ! TARGET_SH4) ? 32 : 64)
|
||||
|
||||
/* 'char' is signed by default. */
|
||||
#define DEFAULT_SIGNED_CHAR 1
|
||||
|
@ -3138,6 +3149,7 @@ extern struct rtx_def *sh_compare_op1;
|
|||
enum processor_type {
|
||||
PROCESSOR_SH1,
|
||||
PROCESSOR_SH2,
|
||||
PROCESSOR_SH2E,
|
||||
PROCESSOR_SH3,
|
||||
PROCESSOR_SH3E,
|
||||
PROCESSOR_SH4,
|
||||
|
@ -3286,7 +3298,7 @@ extern int rtx_equal_function_value_matters;
|
|||
: TARGET_FPU_SINGLE ? FP_MODE_SINGLE \
|
||||
: FP_MODE_DOUBLE)
|
||||
|
||||
#define EPILOGUE_USES(REGNO) ((TARGET_SH3E || TARGET_SH4) \
|
||||
#define EPILOGUE_USES(REGNO) ((TARGET_SH2E || TARGET_SH4) \
|
||||
&& (REGNO) == FPSCR_REG)
|
||||
|
||||
#define MODE_NEEDED(ENTITY, INSN) \
|
||||
|
|
|
@ -1,5 +1,5 @@
|
|||
;;- Machine description for Hitachi / SuperH SH.
|
||||
;; Copyright (C) 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002
|
||||
;; Copyright (C) 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003
|
||||
;; Free Software Foundation, Inc.
|
||||
;; Contributed by Steve Chamberlain (sac@cygnus.com).
|
||||
;; Improved by Jim Wilson (wilson@cygnus.com).
|
||||
|
@ -154,7 +154,7 @@
|
|||
;; Target CPU.
|
||||
|
||||
(define_attr "cpu"
|
||||
"sh1,sh2,sh3,sh3e,sh4,sh5"
|
||||
"sh1,sh2,sh2e,sh3,sh3e,sh4,sh5"
|
||||
(const (symbol_ref "sh_cpu_attr")))
|
||||
|
||||
(define_attr "endian" "big,little"
|
||||
|
@ -609,7 +609,10 @@
|
|||
(define_delay
|
||||
(and (eq_attr "type" "cbranch")
|
||||
(ne (symbol_ref "TARGET_SH2") (const_int 0)))
|
||||
[(eq_attr "in_delay_slot" "yes") (eq_attr "cond_delay_slot" "yes") (nil)])
|
||||
;; SH2e has a hardware bug that pretty much prohibits the use of
|
||||
;; annuled delay slots.
|
||||
[(eq_attr "in_delay_slot" "yes") (and (eq_attr "cond_delay_slot" "yes")
|
||||
(not (eq_attr "cpu" "sh2e"))) (nil)])
|
||||
|
||||
;; -------------------------------------------------------------------------
|
||||
;; SImode signed integer comparisons
|
||||
|
@ -1346,7 +1349,7 @@
|
|||
|
||||
operands[3] = gen_reg_rtx (Pmode);
|
||||
/* Emit the move of the address to a pseudo outside of the libcall. */
|
||||
if (TARGET_HARD_SH4 && TARGET_SH3E)
|
||||
if (TARGET_HARD_SH4 && TARGET_SH2E)
|
||||
{
|
||||
emit_move_insn (operands[3],
|
||||
gen_rtx_SYMBOL_REF (SImode, \"__udivsi3_i4\"));
|
||||
|
@ -1496,7 +1499,7 @@
|
|||
|
||||
operands[3] = gen_reg_rtx (Pmode);
|
||||
/* Emit the move of the address to a pseudo outside of the libcall. */
|
||||
if (TARGET_HARD_SH4 && TARGET_SH3E)
|
||||
if (TARGET_HARD_SH4 && TARGET_SH2E)
|
||||
{
|
||||
emit_move_insn (operands[3],
|
||||
gen_rtx_SYMBOL_REF (SImode, \"__sdivsi3_i4\"));
|
||||
|
@ -3297,7 +3300,7 @@
|
|||
|
||||
(define_insn "push_fpul"
|
||||
[(set (mem:SF (pre_dec:SI (reg:SI SP_REG))) (reg:SF FPUL_REG))]
|
||||
"TARGET_SH3E && ! TARGET_SH5"
|
||||
"TARGET_SH2E && ! TARGET_SH5"
|
||||
"sts.l fpul,@-r15"
|
||||
[(set_attr "type" "store")
|
||||
(set_attr "late_fp_use" "yes")
|
||||
|
@ -3323,7 +3326,7 @@
|
|||
|
||||
(define_insn "pop_fpul"
|
||||
[(set (reg:SF FPUL_REG) (mem:SF (post_inc:SI (reg:SI SP_REG))))]
|
||||
"TARGET_SH3E && ! TARGET_SH5"
|
||||
"TARGET_SH2E && ! TARGET_SH5"
|
||||
"lds.l @r15+,fpul"
|
||||
[(set_attr "type" "load")
|
||||
(set_attr "hit_stack" "yes")])
|
||||
|
@ -3383,7 +3386,7 @@
|
|||
[(set (match_operand:SI 0 "general_movdst_operand" "=r,r,t,r,r,r,r,m,<,<,x,l,x,l,r")
|
||||
(match_operand:SI 1 "general_movsrc_operand" "Q,rI,r,mr,x,l,t,r,x,l,r,r,>,>,i"))]
|
||||
"TARGET_SH1
|
||||
&& ! TARGET_SH3E
|
||||
&& ! TARGET_SH2E
|
||||
&& (register_operand (operands[0], SImode)
|
||||
|| register_operand (operands[1], SImode))"
|
||||
"@
|
||||
|
@ -3414,7 +3417,7 @@
|
|||
(define_insn "movsi_ie"
|
||||
[(set (match_operand:SI 0 "general_movdst_operand" "=r,r,t,r,r,r,r,m,<,<,x,l,x,l,y,<,r,y,r,*f,y,*f,y")
|
||||
(match_operand:SI 1 "general_movsrc_operand" "Q,rI,r,mr,x,l,t,r,x,l,r,r,>,>,>,y,i,r,y,y,*f,*f,y"))]
|
||||
"TARGET_SH3E
|
||||
"TARGET_SH2E
|
||||
&& (register_operand (operands[0], SImode)
|
||||
|| register_operand (operands[1], SImode))"
|
||||
"@
|
||||
|
@ -4354,7 +4357,7 @@
|
|||
(match_operand:SF 1 "register_operand" ""))
|
||||
(use (match_operand:PSI 2 "fpscr_operand" ""))
|
||||
(clobber (match_scratch:SI 3 "X"))]
|
||||
"TARGET_SH3E && reload_completed
|
||||
"TARGET_SH2E && reload_completed
|
||||
&& true_regnum (operands[0]) == true_regnum (operands[1])"
|
||||
[(set (match_dup 0) (match_dup 0))]
|
||||
"")
|
||||
|
@ -4843,7 +4846,7 @@
|
|||
[(set (match_operand:SF 0 "general_movdst_operand" "=r,r,r,r,m,l,r")
|
||||
(match_operand:SF 1 "general_movsrc_operand" "r,I,FQ,mr,r,r,l"))]
|
||||
"TARGET_SH1
|
||||
&& (! TARGET_SH3E
|
||||
&& (! TARGET_SH2E
|
||||
/* ??? We provide some insn so that direct_{load,store}[SFmode] get set */
|
||||
|| (GET_CODE (operands[0]) == REG && REGNO (operands[0]) == 3)
|
||||
|| (GET_CODE (operands[1]) == REG && REGNO (operands[1]) == 3))
|
||||
|
@ -4870,7 +4873,7 @@
|
|||
(use (match_operand:PSI 2 "fpscr_operand" "c,c,c,c,c,c,c,c,c,c,c,c,c,c,c,c,c,c,c"))
|
||||
(clobber (match_scratch:SI 3 "=X,X,X,X,&z,X,X,X,X,X,X,X,X,y,X,X,X,X,X"))]
|
||||
|
||||
"TARGET_SH3E
|
||||
"TARGET_SH2E
|
||||
&& (arith_reg_operand (operands[0], SFmode)
|
||||
|| arith_reg_operand (operands[1], SFmode)
|
||||
|| arith_reg_operand (operands[3], SImode)
|
||||
|
@ -4937,7 +4940,7 @@
|
|||
emit_insn (gen_movsf_media_nofpu (operands[0], operands[1]));
|
||||
DONE;
|
||||
}
|
||||
if (TARGET_SH3E)
|
||||
if (TARGET_SH2E)
|
||||
{
|
||||
emit_sf_insn (gen_movsf_ie (operands[0], operands[1], get_fpscr_rtx ()));
|
||||
DONE;
|
||||
|
@ -4946,7 +4949,7 @@
|
|||
|
||||
(define_insn "mov_nop"
|
||||
[(set (match_operand 0 "any_register_operand" "") (match_dup 0))]
|
||||
"TARGET_SH3E"
|
||||
"TARGET_SH2E"
|
||||
""
|
||||
[(set_attr "length" "0")
|
||||
(set_attr "type" "nil")])
|
||||
|
@ -4970,7 +4973,7 @@
|
|||
[(set (match_operand:SI 0 "register_operand" "=y,y")
|
||||
(match_operand:SI 1 "immediate_operand" "Qi,I"))
|
||||
(clobber (match_scratch:SI 2 "=&z,r"))]
|
||||
"TARGET_SH3E
|
||||
"TARGET_SH2E
|
||||
&& (reload_in_progress || reload_completed)"
|
||||
"#"
|
||||
[(set_attr "length" "4")
|
||||
|
@ -5290,7 +5293,7 @@
|
|||
DONE;
|
||||
}
|
||||
|
||||
if (TARGET_SH3E
|
||||
if (TARGET_SH2E
|
||||
&& TARGET_IEEE
|
||||
&& GET_MODE_CLASS (GET_MODE (sh_compare_op0)) == MODE_FLOAT)
|
||||
{
|
||||
|
@ -5331,7 +5334,7 @@
|
|||
DONE;
|
||||
}
|
||||
|
||||
if (TARGET_SH3E
|
||||
if (TARGET_SH2E
|
||||
&& ! TARGET_IEEE
|
||||
&& GET_MODE_CLASS (GET_MODE (sh_compare_op0)) == MODE_FLOAT)
|
||||
{
|
||||
|
@ -6487,7 +6490,7 @@
|
|||
(const_int 0))
|
||||
(match_operand 1 "" "")
|
||||
(match_operand 2 "" "")])]
|
||||
"TARGET_SH3E || TARGET_SHMEDIA"
|
||||
"TARGET_SH2E || TARGET_SHMEDIA"
|
||||
"
|
||||
{
|
||||
int i;
|
||||
|
@ -7991,10 +7994,10 @@
|
|||
[(set (match_operand:SF 0 "arith_reg_operand" "")
|
||||
(plus:SF (match_operand:SF 1 "arith_reg_operand" "")
|
||||
(match_operand:SF 2 "arith_reg_operand" "")))]
|
||||
"TARGET_SH3E || TARGET_SHMEDIA_FPU"
|
||||
"TARGET_SH2E || TARGET_SHMEDIA_FPU"
|
||||
"
|
||||
{
|
||||
if (TARGET_SH3E)
|
||||
if (TARGET_SH2E)
|
||||
{
|
||||
expand_sf_binop (&gen_addsf3_i, operands);
|
||||
DONE;
|
||||
|
@ -8080,7 +8083,7 @@
|
|||
(plus:SF (match_operand:SF 1 "arith_reg_operand" "%0")
|
||||
(match_operand:SF 2 "arith_reg_operand" "f")))
|
||||
(use (match_operand:PSI 3 "fpscr_operand" "c"))]
|
||||
"TARGET_SH3E"
|
||||
"TARGET_SH2E"
|
||||
"fadd %2,%0"
|
||||
[(set_attr "type" "fp")
|
||||
(set_attr "fp_mode" "single")])
|
||||
|
@ -8089,10 +8092,10 @@
|
|||
[(set (match_operand:SF 0 "fp_arith_reg_operand" "")
|
||||
(minus:SF (match_operand:SF 1 "fp_arith_reg_operand" "")
|
||||
(match_operand:SF 2 "fp_arith_reg_operand" "")))]
|
||||
"TARGET_SH3E || TARGET_SHMEDIA_FPU"
|
||||
"TARGET_SH2E || TARGET_SHMEDIA_FPU"
|
||||
"
|
||||
{
|
||||
if (TARGET_SH3E)
|
||||
if (TARGET_SH2E)
|
||||
{
|
||||
expand_sf_binop (&gen_subsf3_i, operands);
|
||||
DONE;
|
||||
|
@ -8112,7 +8115,7 @@
|
|||
(minus:SF (match_operand:SF 1 "fp_arith_reg_operand" "0")
|
||||
(match_operand:SF 2 "fp_arith_reg_operand" "f")))
|
||||
(use (match_operand:PSI 3 "fpscr_operand" "c"))]
|
||||
"TARGET_SH3E"
|
||||
"TARGET_SH2E"
|
||||
"fsub %2,%0"
|
||||
[(set_attr "type" "fp")
|
||||
(set_attr "fp_mode" "single")])
|
||||
|
@ -8126,12 +8129,12 @@
|
|||
[(set (match_operand:SF 0 "fp_arith_reg_operand" "")
|
||||
(mult:SF (match_operand:SF 1 "fp_arith_reg_operand" "")
|
||||
(match_operand:SF 2 "fp_arith_reg_operand" "")))]
|
||||
"TARGET_SH3E || TARGET_SHMEDIA_FPU"
|
||||
"TARGET_SH2E || TARGET_SHMEDIA_FPU"
|
||||
"
|
||||
{
|
||||
if (TARGET_SH4)
|
||||
expand_sf_binop (&gen_mulsf3_i4, operands);
|
||||
else if (TARGET_SH3E)
|
||||
else if (TARGET_SH2E)
|
||||
emit_insn (gen_mulsf3_ie (operands[0], operands[1], operands[2]));
|
||||
if (! TARGET_SHMEDIA)
|
||||
DONE;
|
||||
|
@ -8150,7 +8153,7 @@
|
|||
(mult:SF (match_operand:SF 1 "fp_arith_reg_operand" "%0")
|
||||
(match_operand:SF 2 "fp_arith_reg_operand" "f")))
|
||||
(use (match_operand:PSI 3 "fpscr_operand" "c"))]
|
||||
"TARGET_SH3E"
|
||||
"TARGET_SH2E"
|
||||
"fmul %2,%0"
|
||||
[(set_attr "type" "fp")
|
||||
(set_attr "fp_mode" "single")])
|
||||
|
@ -8159,7 +8162,7 @@
|
|||
[(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
|
||||
(mult:SF (match_operand:SF 1 "fp_arith_reg_operand" "%0")
|
||||
(match_operand:SF 2 "fp_arith_reg_operand" "f")))]
|
||||
"TARGET_SH3E && ! TARGET_SH4"
|
||||
"TARGET_SH2E && ! TARGET_SH4"
|
||||
"fmul %2,%0"
|
||||
[(set_attr "type" "fp")])
|
||||
|
||||
|
@ -8178,7 +8181,7 @@
|
|||
(match_operand:SF 2 "fp_arith_reg_operand" "f"))
|
||||
(match_operand:SF 3 "arith_reg_operand" "0")))
|
||||
(use (match_operand:PSI 4 "fpscr_operand" "c"))]
|
||||
"TARGET_SH3E && ! TARGET_SH4"
|
||||
"TARGET_SH2E && ! TARGET_SH4"
|
||||
"fmac fr0,%2,%0"
|
||||
[(set_attr "type" "fp")
|
||||
(set_attr "fp_mode" "single")])
|
||||
|
@ -8187,10 +8190,10 @@
|
|||
[(set (match_operand:SF 0 "arith_reg_operand" "")
|
||||
(div:SF (match_operand:SF 1 "arith_reg_operand" "")
|
||||
(match_operand:SF 2 "arith_reg_operand" "")))]
|
||||
"TARGET_SH3E || TARGET_SHMEDIA_FPU"
|
||||
"TARGET_SH2E || TARGET_SHMEDIA_FPU"
|
||||
"
|
||||
{
|
||||
if (TARGET_SH3E)
|
||||
if (TARGET_SH2E)
|
||||
{
|
||||
expand_sf_binop (&gen_divsf3_i, operands);
|
||||
DONE;
|
||||
|
@ -8210,7 +8213,7 @@
|
|||
(div:SF (match_operand:SF 1 "arith_reg_operand" "0")
|
||||
(match_operand:SF 2 "arith_reg_operand" "f")))
|
||||
(use (match_operand:PSI 3 "fpscr_operand" "c"))]
|
||||
"TARGET_SH3E"
|
||||
"TARGET_SH2E"
|
||||
"fdiv %2,%0"
|
||||
[(set_attr "type" "fdiv")
|
||||
(set_attr "fp_mode" "single")])
|
||||
|
@ -8225,7 +8228,7 @@
|
|||
(define_expand "floatsisf2"
|
||||
[(set (match_operand:SF 0 "fp_arith_reg_operand" "")
|
||||
(float:SF (match_operand:SI 1 "fpul_operand" "")))]
|
||||
"TARGET_SH3E || TARGET_SHMEDIA_FPU"
|
||||
"TARGET_SH2E || TARGET_SHMEDIA_FPU"
|
||||
"
|
||||
{
|
||||
if (TARGET_SH4)
|
||||
|
@ -8254,7 +8257,7 @@
|
|||
(define_insn "*floatsisf2_ie"
|
||||
[(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
|
||||
(float:SF (match_operand:SI 1 "fpul_operand" "y")))]
|
||||
"TARGET_SH3E && ! TARGET_SH4"
|
||||
"TARGET_SH2E && ! TARGET_SH4"
|
||||
"float %1,%0"
|
||||
[(set_attr "type" "fp")])
|
||||
|
||||
|
@ -8268,7 +8271,7 @@
|
|||
(define_expand "fix_truncsfsi2"
|
||||
[(set (match_operand:SI 0 "fpul_operand" "=y")
|
||||
(fix:SI (match_operand:SF 1 "fp_arith_reg_operand" "f")))]
|
||||
"TARGET_SH3E || TARGET_SHMEDIA_FPU"
|
||||
"TARGET_SH2E || TARGET_SHMEDIA_FPU"
|
||||
"
|
||||
{
|
||||
if (TARGET_SH4)
|
||||
|
@ -8319,7 +8322,7 @@
|
|||
(define_insn "*fixsfsi"
|
||||
[(set (match_operand:SI 0 "fpul_operand" "=y")
|
||||
(fix:SI (match_operand:SF 1 "fp_arith_reg_operand" "f")))]
|
||||
"TARGET_SH3E && ! TARGET_SH4"
|
||||
"TARGET_SH2E && ! TARGET_SH4"
|
||||
"ftrc %1,%0"
|
||||
[(set_attr "type" "fp")])
|
||||
|
||||
|
@ -8327,7 +8330,7 @@
|
|||
[(set (reg:SI T_REG)
|
||||
(gt:SI (match_operand:SF 0 "fp_arith_reg_operand" "f")
|
||||
(match_operand:SF 1 "fp_arith_reg_operand" "f")))]
|
||||
"TARGET_SH3E && ! TARGET_SH4"
|
||||
"TARGET_SH2E && ! TARGET_SH4"
|
||||
"fcmp/gt %1,%0"
|
||||
[(set_attr "type" "fp")
|
||||
(set_attr "fp_mode" "single")])
|
||||
|
@ -8336,7 +8339,7 @@
|
|||
[(set (reg:SI T_REG)
|
||||
(eq:SI (match_operand:SF 0 "fp_arith_reg_operand" "f")
|
||||
(match_operand:SF 1 "fp_arith_reg_operand" "f")))]
|
||||
"TARGET_SH3E && ! TARGET_SH4"
|
||||
"TARGET_SH2E && ! TARGET_SH4"
|
||||
"fcmp/eq %1,%0"
|
||||
[(set_attr "type" "fp")
|
||||
(set_attr "fp_mode" "single")])
|
||||
|
@ -8346,7 +8349,7 @@
|
|||
(ior:SI (reg:SI T_REG)
|
||||
(eq:SI (match_operand:SF 0 "fp_arith_reg_operand" "f")
|
||||
(match_operand:SF 1 "fp_arith_reg_operand" "f"))))]
|
||||
"TARGET_SH3E && TARGET_IEEE && ! TARGET_SH4"
|
||||
"TARGET_SH2E && TARGET_IEEE && ! TARGET_SH4"
|
||||
"* return output_ieee_ccmpeq (insn, operands);"
|
||||
[(set_attr "length" "4")])
|
||||
|
||||
|
@ -8418,7 +8421,7 @@
|
|||
[(set (reg:SI T_REG)
|
||||
(compare (match_operand:SF 0 "arith_operand" "")
|
||||
(match_operand:SF 1 "arith_operand" "")))]
|
||||
"TARGET_SH3E || TARGET_SHMEDIA_FPU"
|
||||
"TARGET_SH2E || TARGET_SHMEDIA_FPU"
|
||||
"
|
||||
{
|
||||
sh_compare_op0 = operands[0];
|
||||
|
@ -8429,10 +8432,10 @@
|
|||
(define_expand "negsf2"
|
||||
[(set (match_operand:SF 0 "fp_arith_reg_operand" "")
|
||||
(neg:SF (match_operand:SF 1 "fp_arith_reg_operand" "")))]
|
||||
"TARGET_SH3E || TARGET_SHMEDIA_FPU"
|
||||
"TARGET_SH2E || TARGET_SHMEDIA_FPU"
|
||||
"
|
||||
{
|
||||
if (TARGET_SH3E)
|
||||
if (TARGET_SH2E)
|
||||
{
|
||||
expand_sf_unop (&gen_negsf2_i, operands);
|
||||
DONE;
|
||||
|
@ -8450,7 +8453,7 @@
|
|||
[(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
|
||||
(neg:SF (match_operand:SF 1 "fp_arith_reg_operand" "0")))
|
||||
(use (match_operand:PSI 2 "fpscr_operand" "c"))]
|
||||
"TARGET_SH3E"
|
||||
"TARGET_SH2E"
|
||||
"fneg %0"
|
||||
[(set_attr "type" "fmove")
|
||||
(set_attr "fp_mode" "single")])
|
||||
|
@ -8487,10 +8490,10 @@
|
|||
(define_expand "abssf2"
|
||||
[(set (match_operand:SF 0 "fp_arith_reg_operand" "")
|
||||
(abs:SF (match_operand:SF 1 "fp_arith_reg_operand" "")))]
|
||||
"TARGET_SH3E || TARGET_SHMEDIA_FPU"
|
||||
"TARGET_SH2E || TARGET_SHMEDIA_FPU"
|
||||
"
|
||||
{
|
||||
if (TARGET_SH3E)
|
||||
if (TARGET_SH2E)
|
||||
{
|
||||
expand_sf_unop (&gen_abssf2_i, operands);
|
||||
DONE;
|
||||
|
@ -8508,7 +8511,7 @@
|
|||
[(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
|
||||
(abs:SF (match_operand:SF 1 "fp_arith_reg_operand" "0")))
|
||||
(use (match_operand:PSI 2 "fpscr_operand" "c"))]
|
||||
"TARGET_SH3E"
|
||||
"TARGET_SH2E"
|
||||
"fabs %0"
|
||||
[(set_attr "type" "fmove")
|
||||
(set_attr "fp_mode" "single")])
|
||||
|
@ -9143,7 +9146,7 @@
|
|||
(plus:SI (match_dup 0) (match_operand:SI 1 "register_operand" "r")))
|
||||
(set (mem:SF (match_dup 0))
|
||||
(match_operand:SF 2 "general_movsrc_operand" ""))]
|
||||
"TARGET_SH3E && REGNO (operands[0]) == 0
|
||||
"TARGET_SH2E && REGNO (operands[0]) == 0
|
||||
&& ((GET_CODE (operands[2]) == REG
|
||||
&& FP_OR_XD_REGISTER_P (REGNO (operands[2])))
|
||||
|| (GET_CODE (operands[2]) == SUBREG
|
||||
|
@ -9157,7 +9160,7 @@
|
|||
(set (match_operand:SF 2 "general_movdst_operand" "")
|
||||
|
||||
(mem:SF (match_dup 0)))]
|
||||
"TARGET_SH3E && REGNO (operands[0]) == 0
|
||||
"TARGET_SH2E && REGNO (operands[0]) == 0
|
||||
&& ((GET_CODE (operands[2]) == REG
|
||||
&& FP_OR_XD_REGISTER_P (REGNO (operands[2])))
|
||||
|| (GET_CODE (operands[2]) == SUBREG
|
||||
|
|
|
@ -1,5 +1,5 @@
|
|||
/* Definitions of target machine for GNU compiler for SuperH SH 5.
|
||||
Copyright 2000, 2001, 2002 Free Software Foundation, Inc.
|
||||
Copyright 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
|
||||
Contributed by Alexandre Oliva <aoliva@redhat.com>
|
||||
|
||||
This file is part of GNU CC.
|
||||
|
@ -35,7 +35,7 @@ Boston, MA 02111-1307, USA. */
|
|||
#define LINK_DEFAULT_CPU_EMUL "32"
|
||||
|
||||
#undef TARGET_DEFAULT
|
||||
#define TARGET_DEFAULT (SH5_BIT|SH4_BIT|SH3E_BIT|TARGET_ENDIAN_DEFAULT)
|
||||
#define TARGET_DEFAULT (SH5_BIT|SH4_BIT|SH_E_BIT|TARGET_ENDIAN_DEFAULT)
|
||||
|
||||
#undef SH_ELF_WCHAR_TYPE
|
||||
#define SH_ELF_WCHAR_TYPE "int"
|
||||
|
|
|
@ -31,9 +31,9 @@ fp-bit.c: $(srcdir)/config/fp-bit.c
|
|||
cat $(srcdir)/config/fp-bit.c >> fp-bit.c
|
||||
|
||||
MULTILIB_ENDIAN = ml
|
||||
MULTILIB_OPTIONS= $(MULTILIB_ENDIAN) m2/m3e/m4-single-only/m4-single/m4
|
||||
MULTILIB_OPTIONS= $(MULTILIB_ENDIAN) m2/m2e/m4-single-only/m4-single/m4
|
||||
MULTILIB_DIRNAMES=
|
||||
MULTILIB_MATCHES = m2=m3 m2=m4-nofpu
|
||||
MULTILIB_MATCHES = m2=m3 m2e=m3e m2=m4-nofpu
|
||||
MULTILIB_EXCEPTIONS = ml
|
||||
|
||||
LIBGCC = stmp-multilib
|
||||
|
|
|
@ -557,7 +557,7 @@ in the following sections.
|
|||
|
||||
@emph{SH Options}
|
||||
@gccoptlist{
|
||||
-m1 -m2 -m3 -m3e @gol
|
||||
-m1 -m2 -m2e -m3 -m3e @gol
|
||||
-m4-nofpu -m4-single-only -m4-single -m4 @gol
|
||||
-m5-64media -m5-64media-nofpu @gol
|
||||
-m5-32media -m5-32media-nofpu @gol
|
||||
|
@ -8793,6 +8793,9 @@ Generate code for the SH1.
|
|||
@opindex m2
|
||||
Generate code for the SH2.
|
||||
|
||||
@item -m2e
|
||||
Generate code for the SH2e.
|
||||
|
||||
@item -m3
|
||||
@opindex m3
|
||||
Generate code for the SH3.
|
||||
|
|
Loading…
Reference in New Issue