elf.h: Fix comment formatting.
* config/xtensa/elf.h: Fix comment formatting. * config/xtensa/xtensa-protos.h: Likewise. * config/xtensa/xtensa.c: Likewise. * config/xtensa/xtensa.h: Likewise. From-SVN: r75018
This commit is contained in:
parent
be88628621
commit
3bbc2af6e7
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@ -1,3 +1,10 @@
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2003-12-24 Kazu Hirata <kazu@cs.umass.edu>
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* config/xtensa/elf.h: Fix comment formatting.
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* config/xtensa/xtensa-protos.h: Likewise.
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* config/xtensa/xtensa.c: Likewise.
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* config/xtensa/xtensa.h: Likewise.
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2003-12-24 Kazu Hirata <kazu@cs.umass.edu>
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* config/avr/avr.c: Fix comment formatting.
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@ -21,7 +21,7 @@ Software Foundation, 59 Temple Place - Suite 330, Boston, MA
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#define TARGET_SECTION_TYPE_FLAGS xtensa_multibss_section_type_flags
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/* Don't assume anything about the header files. */
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/* Don't assume anything about the header files. */
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#define NO_IMPLICIT_EXTERN_C
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#undef ASM_APP_ON
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@ -22,7 +22,7 @@ Software Foundation, 59 Temple Place - Suite 330, Boston, MA
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#ifndef __XTENSA_PROTOS_H__
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#define __XTENSA_PROTOS_H__
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/* Functions to test whether an immediate fits in a given field. */
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/* Functions to test whether an immediate fits in a given field. */
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extern int xtensa_simm7 (int);
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extern int xtensa_simm8 (int);
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extern int xtensa_simm8x256 (int);
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@ -600,7 +600,7 @@ move_operand (rtx op, enum machine_mode mode)
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case SImode:
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if (TARGET_CONST16)
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return CONSTANT_P (op);
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/* fall through */
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/* Fall through. */
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case HImode:
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case QImode:
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@ -652,12 +652,12 @@ constantpool_address_p (rtx addr)
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{
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rtx offset;
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/* only handle (PLUS (SYM, OFFSET)) form */
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/* Only handle (PLUS (SYM, OFFSET)) form. */
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addr = XEXP (addr, 0);
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if (GET_CODE (addr) != PLUS)
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return FALSE;
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/* make sure the address is word aligned */
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/* Make sure the address is word aligned. */
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offset = XEXP (addr, 1);
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if ((GET_CODE (offset) != CONST_INT)
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|| ((INTVAL (offset) & 3) != 0))
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@ -728,7 +728,7 @@ xtensa_extend_reg (rtx dst, rtx src)
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rtx temp = gen_reg_rtx (SImode);
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rtx shift = GEN_INT (BITS_PER_WORD - GET_MODE_BITSIZE (GET_MODE (src)));
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/* generate paradoxical subregs as needed so that the modes match */
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/* Generate paradoxical subregs as needed so that the modes match. */
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src = simplify_gen_subreg (SImode, src, GET_MODE (src), 0);
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dst = simplify_gen_subreg (SImode, dst, GET_MODE (dst), 0);
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@ -1080,14 +1080,14 @@ gen_conditional_move (rtx cmp)
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if (boolean_operator (cmp, VOIDmode))
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{
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/* swap the operands to make const0 second */
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/* Swap the operands to make const0 second. */
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if (op0 == const0_rtx)
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{
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op0 = op1;
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op1 = const0_rtx;
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}
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/* if not comparing against zero, emit a comparison (subtract) */
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/* If not comparing against zero, emit a comparison (subtract). */
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if (op1 != const0_rtx)
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{
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op0 = expand_binop (SImode, sub_optab, op0, op1,
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@ -1097,7 +1097,7 @@ gen_conditional_move (rtx cmp)
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}
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else if (branch_operator (cmp, VOIDmode))
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{
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/* swap the operands to make const0 second */
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/* Swap the operands to make const0 second. */
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if (op0 == const0_rtx)
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{
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op0 = op1;
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@ -1379,26 +1379,26 @@ xtensa_expand_block_move (rtx *operands)
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int align = XINT (operands[3], 0);
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int num_pieces, move_ratio;
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/* If this is not a fixed size move, just call memcpy */
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/* If this is not a fixed size move, just call memcpy. */
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if (!optimize || (GET_CODE (operands[2]) != CONST_INT))
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return 0;
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/* Anything to move? */
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/* Anything to move? */
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if (bytes <= 0)
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return 1;
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if (align > MOVE_MAX)
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align = MOVE_MAX;
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/* decide whether to expand inline based on the optimization level */
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/* Decide whether to expand inline based on the optimization level. */
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move_ratio = 4;
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if (optimize > 2)
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move_ratio = LARGEST_MOVE_RATIO;
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num_pieces = (bytes / align) + (bytes % align); /* close enough anyway */
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num_pieces = (bytes / align) + (bytes % align); /* Close enough anyway. */
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if (num_pieces >= move_ratio)
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return 0;
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/* make sure the memory addresses are valid */
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/* Make sure the memory addresses are valid. */
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operands[0] = validize_mem (dest);
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operands[1] = validize_mem (src);
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@ -1408,10 +1408,10 @@ xtensa_expand_block_move (rtx *operands)
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}
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/* Emit a sequence of instructions to implement a block move, trying
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to hide load delay slots as much as possible. Load N values into
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temporary registers, store those N values, and repeat until the
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complete block has been moved. N=delay_slots+1 */
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/* Emit a sequence of instructions to implement a block move, trying
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to hide load delay slots as much as possible. Load N values into
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temporary registers, store those N values, and repeat until the
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complete block has been moved. N=delay_slots+1. */
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struct meminsnbuf
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{
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@ -1467,7 +1467,7 @@ xtensa_emit_block_move (rtx *operands, rtx *tmpregs, int delay_slots)
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if (bytes < item_size)
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{
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/* find a smaller item_size which we can load & store */
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/* Find a smaller item_size which we can load & store. */
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item_size = bytes;
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mode = xtensa_find_mode_for_size (item_size);
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item_size = GET_MODE_SIZE (mode);
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stname = xtensa_st_opcodes[(int) mode];
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}
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/* record the load instruction opcode and operands */
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/* Record the load instruction opcode and operands. */
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addr = plus_constant (from_addr, offset);
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mem = gen_rtx_MEM (mode, addr);
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if (! memory_address_p (mode, addr))
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ldinsns[n].operands[1] = mem;
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sprintf (ldinsns[n].template, "%s\t%%0, %%1", ldname);
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/* record the store instruction opcode and operands */
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/* Record the store instruction opcode and operands. */
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addr = plus_constant (to_addr, offset);
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mem = gen_rtx_MEM (mode, addr);
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if (! memory_address_p (mode, addr))
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bytes -= item_size;
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}
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/* now output the loads followed by the stores */
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/* Now output the loads followed by the stores. */
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for (n = 0; n < chunk_size; n++)
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output_asm_insn (ldinsns[n].template, ldinsns[n].operands);
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for (n = 0; n < chunk_size; n++)
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@ -1517,7 +1517,7 @@ xtensa_find_mode_for_size (unsigned item_size)
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{
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mode = VOIDmode;
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/* find mode closest to but not bigger than item_size */
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/* Find mode closest to but not bigger than item_size. */
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for (tmode = GET_CLASS_NARROWEST_MODE (MODE_INT);
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tmode != VOIDmode; tmode = GET_MODE_WIDER_MODE (tmode))
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if (GET_MODE_SIZE (tmode) <= item_size)
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@ -1531,7 +1531,7 @@ xtensa_find_mode_for_size (unsigned item_size)
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&& xtensa_st_opcodes[(int) mode])
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break;
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/* cannot load & store this mode; try something smaller */
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/* Cannot load & store this mode; try something smaller. */
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item_size -= 1;
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}
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@ -1545,8 +1545,8 @@ xtensa_expand_nonlocal_goto (rtx *operands)
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rtx goto_handler = operands[1];
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rtx containing_fp = operands[3];
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/* generate a call to "__xtensa_nonlocal_goto" (in libgcc); the code
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is too big to generate in-line */
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/* Generate a call to "__xtensa_nonlocal_goto" (in libgcc); the code
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is too big to generate in-line. */
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if (GET_CODE (containing_fp) != REG)
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containing_fp = force_reg (Pmode, containing_fp);
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@ -1789,7 +1789,7 @@ override_options (void)
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if (!TARGET_BOOLEANS && TARGET_HARD_FLOAT)
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error ("boolean registers required for the floating-point option");
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/* set up the tables of ld/st opcode names for block moves */
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/* Set up the tables of ld/st opcode names for block moves. */
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xtensa_ld_opcodes[(int) SImode] = "l32i";
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xtensa_ld_opcodes[(int) HImode] = "l16ui";
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xtensa_ld_opcodes[(int) QImode] = "l8ui";
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@ -2366,7 +2366,7 @@ xtensa_builtin_saveregs (void)
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if (gp_left == 0)
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return const0_rtx;
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/* allocate the general-purpose register space */
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/* Allocate the general-purpose register space. */
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gp_regs = assign_stack_local
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(BLKmode, MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD, -1);
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set_mem_alias_set (gp_regs, get_varargs_alias_set ());
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@ -2662,8 +2662,8 @@ order_regs_for_local_alloc (void)
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int i, num_arg_regs;
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int nxt = 0;
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/* use the AR registers in increasing order (skipping a0 and a1)
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but save the incoming argument registers for a last resort */
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/* Use the AR registers in increasing order (skipping a0 and a1)
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but save the incoming argument registers for a last resort. */
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num_arg_regs = current_function_args_info.arg_words;
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if (num_arg_regs > MAX_ARGS_IN_REGISTERS)
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num_arg_regs = MAX_ARGS_IN_REGISTERS;
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for (i = 0; i < num_arg_regs; i++)
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reg_alloc_order[nxt++] = GP_ARG_FIRST + i;
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/* list the coprocessor registers in order */
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/* List the coprocessor registers in order. */
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for (i = 0; i < BR_REG_NUM; i++)
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reg_alloc_order[nxt++] = BR_REG_FIRST + i;
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/* list the FP registers in order for now */
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/* List the FP registers in order for now. */
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for (i = 0; i < 16; i++)
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reg_alloc_order[nxt++] = FP_REG_FIRST + i;
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case LSHIFTRT:
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case ROTATE:
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case ROTATERT:
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/* no way to tell if X is the 2nd operand so be conservative */
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/* No way to tell if X is the 2nd operand so be conservative. */
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default: break;
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}
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if (xtensa_simm12b (INTVAL (x)))
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return true;
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}
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}
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/* fall through */
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/* Fall through. */
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case UDIV:
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case UMOD:
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@ -142,10 +142,10 @@ extern unsigned xtensa_current_frame_size;
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in instructions that operate on numbered bit-fields. */
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#define BITS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
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/* Define this if most significant byte of a word is the lowest numbered. */
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/* Define this if most significant byte of a word is the lowest numbered. */
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#define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
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/* Define this if most significant word of a multiword number is the lowest. */
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/* Define this if most significant word of a multiword number is the lowest. */
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#define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
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#define MAX_BITS_PER_WORD 32
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@ -271,11 +271,11 @@ extern unsigned xtensa_current_frame_size;
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#define FIRST_PSEUDO_REGISTER 36
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/* Return the stabs register number to use for REGNO. */
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/* Return the stabs register number to use for REGNO. */
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#define DBX_REGISTER_NUMBER(REGNO) xtensa_dbx_register_number (REGNO)
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/* 1 for registers that have pervasive standard uses
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and are not available for the register allocator. */
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and are not available for the register allocator. */
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#define FIXED_REGISTERS \
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{ \
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1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
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@ -326,18 +326,18 @@ extern unsigned xtensa_current_frame_size;
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giving preference to call-used registers. To minimize window
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overflows for the AR registers, we want to give preference to the
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lower-numbered AR registers. For other register files, which are
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not windowed, we still prefer call-used registers, if there are any. */
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not windowed, we still prefer call-used registers, if there are any. */
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extern const char xtensa_leaf_regs[FIRST_PSEUDO_REGISTER];
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#define LEAF_REGISTERS xtensa_leaf_regs
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/* For Xtensa, no remapping is necessary, but this macro must be
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defined if LEAF_REGISTERS is defined. */
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defined if LEAF_REGISTERS is defined. */
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#define LEAF_REG_REMAP(REGNO) (REGNO)
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/* this must be declared if LEAF_REGISTERS is set */
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/* This must be declared if LEAF_REGISTERS is set. */
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extern int leaf_function;
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/* Internal macros to classify a register number. */
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/* Internal macros to classify a register number. */
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/* 16 address registers + fake registers */
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#define GP_REG_FIRST 0
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@ -372,7 +372,7 @@ extern int leaf_function;
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((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
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/* Value is 1 if hard register REGNO can hold a value of machine-mode
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MODE. */
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MODE. */
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extern char xtensa_hard_regno_mode_ok[][FIRST_PSEUDO_REGISTER];
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#define HARD_REGNO_MODE_OK(REGNO, MODE) \
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@ -397,7 +397,7 @@ extern char xtensa_hard_regno_mode_ok[][FIRST_PSEUDO_REGISTER];
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/* The register number of the frame pointer register, which is used to
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access automatic variables in the stack frame. For Xtensa, this
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register never appears in the output. It is always eliminated to
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either the stack pointer or the hard frame pointer. */
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either the stack pointer or the hard frame pointer. */
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#define FRAME_POINTER_REGNUM (GP_REG_FIRST + 16)
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/* Value should be nonzero if functions must have frame pointers.
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@ -518,7 +518,7 @@ extern const enum reg_class xtensa_regno_to_class[FIRST_PSEUDO_REGISTER];
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/* SMALL_REGISTER_CLASSES is required for Xtensa, because all of the
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16 AR registers may be explicitly used in the RTL, as either
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incoming or outgoing arguments. */
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incoming or outgoing arguments. */
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#define SMALL_REGISTER_CLASSES 1
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@ -599,7 +599,7 @@ extern enum reg_class xtensa_char_to_class[256];
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the meantime, the constraints are checked and none match. The
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solution seems to be to simply skip the offset check here. The
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address will be checked anyway because of the code in
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GO_IF_LEGITIMATE_ADDRESS. */
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GO_IF_LEGITIMATE_ADDRESS. */
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#define EXTRA_CONSTRAINT(OP, CODE) \
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((GET_CODE (OP) != MEM) ? \
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@ -714,7 +714,7 @@ extern enum reg_class xtensa_char_to_class[256];
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/* Define how to find the value returned by a library function
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assuming the value has mode MODE. Because we have defined
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PROMOTE_FUNCTION_RETURN, we have to perform the same promotions as
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PROMOTE_MODE. */
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PROMOTE_MODE. */
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#define XTENSA_LIBCALL_VALUE(MODE, OUTGOINGP) \
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gen_rtx_REG ((GET_MODE_CLASS (MODE) == MODE_INT \
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&& GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
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@ -750,7 +750,7 @@ extern enum reg_class xtensa_char_to_class[256];
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be recognized by this macro. If the machine has register windows,
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so that the caller and the called function use different registers
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for the return value, this macro should recognize only the caller's
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register numbers. */
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register numbers. */
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#define FUNCTION_VALUE_REGNO_P(N) \
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((N) == GP_RETURN)
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@ -759,7 +759,7 @@ extern enum reg_class xtensa_char_to_class[256];
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does *not* include implicit arguments such as the static chain and
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the structure-value address. On many machines, no registers can be
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used for this purpose since all function arguments are pushed on
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the stack. */
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the stack. */
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#define FUNCTION_ARG_REGNO_P(N) \
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((N) >= GP_OUTGOING_ARG_FIRST && (N) <= GP_OUTGOING_ARG_LAST)
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@ -767,14 +767,14 @@ extern enum reg_class xtensa_char_to_class[256];
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during the scan of that argument list. This data type should
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hold all necessary information about the function itself
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and about the args processed so far, enough to enable macros
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such as FUNCTION_ARG to determine where the next arg should go. */
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such as FUNCTION_ARG to determine where the next arg should go. */
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typedef struct xtensa_args {
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int arg_words; /* # total words the arguments take */
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} CUMULATIVE_ARGS;
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/* Initialize a variable CUM of type CUMULATIVE_ARGS
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for a call to a function whose data type is FNTYPE.
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For a library call, FNTYPE is 0. */
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For a library call, FNTYPE is 0. */
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#define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT) \
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init_cumulative_args (&CUM, FNTYPE, LIBNAME)
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@ -816,7 +816,7 @@ typedef struct xtensa_args {
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|||
|
||||
This differs from the default in that it does not check if the padding
|
||||
and mode of the type are such that a copy into a register would put it
|
||||
into the wrong part of the register. */
|
||||
into the wrong part of the register. */
|
||||
|
||||
#define MUST_PASS_IN_STACK(MODE, TYPE) \
|
||||
((TYPE) != 0 \
|
||||
|
@ -835,7 +835,7 @@ typedef struct xtensa_args {
|
|||
values contain window size information in the two most significant
|
||||
bits; we assume that _mcount will mask off those bits. The call to
|
||||
_mcount uses a window size of 8 to make sure that it doesn't clobber
|
||||
any incoming argument values. */
|
||||
any incoming argument values. */
|
||||
|
||||
#define NO_PROFILE_COUNTERS 1
|
||||
|
||||
|
@ -865,7 +865,7 @@ typedef struct xtensa_args {
|
|||
from the entry instruction at the target and the current frame is
|
||||
adjusted to match. The trampoline then transfers control to the
|
||||
instruction following the entry at the target. Note: this assumes
|
||||
that the target begins with an entry instruction. */
|
||||
that the target begins with an entry instruction. */
|
||||
|
||||
/* minimum frame = reg save area (4 words) plus static chain (1 word)
|
||||
and the total number of words must be a multiple of 128 bits */
|
||||
|
@ -934,7 +934,7 @@ typedef struct xtensa_args {
|
|||
code for a call to '__builtin_saveregs'. This code will be moved
|
||||
to the very beginning of the function, before any parameter access
|
||||
are made. The return value of this function should be an RTX that
|
||||
contains the value to use as the return of '__builtin_saveregs'. */
|
||||
contains the value to use as the return of '__builtin_saveregs'. */
|
||||
#define EXPAND_BUILTIN_SAVEREGS \
|
||||
xtensa_builtin_saveregs
|
||||
|
||||
|
@ -962,7 +962,7 @@ typedef struct xtensa_args {
|
|||
specify whether to start from the stack pointer or frame pointer. That
|
||||
would also allow us to skip the machine->accesses_prev_frame stuff that
|
||||
we currently need to ensure that there is a frame pointer when these
|
||||
builtin functions are used. */
|
||||
builtin functions are used. */
|
||||
|
||||
#define SETUP_FRAME_ADDRESSES xtensa_setup_frame_addresses
|
||||
|
||||
|
@ -976,14 +976,14 @@ typedef struct xtensa_args {
|
|||
macro is used for continuing to walk back up the stack, so it must
|
||||
return the stack pointer address. Thus, there is some inconsistency
|
||||
here in that __builtin_frame_address will return the frame pointer
|
||||
when count == 0 and the stack pointer when count > 0. */
|
||||
when count == 0 and the stack pointer when count > 0. */
|
||||
|
||||
#define DYNAMIC_CHAIN_ADDRESS(frame) \
|
||||
gen_rtx (PLUS, Pmode, frame, \
|
||||
gen_rtx_CONST_INT (VOIDmode, -3 * UNITS_PER_WORD))
|
||||
|
||||
/* Define this if the return address of a particular stack frame is
|
||||
accessed from the frame pointer of the previous stack frame. */
|
||||
accessed from the frame pointer of the previous stack frame. */
|
||||
#define RETURN_ADDR_IN_PREVIOUS_FRAME
|
||||
|
||||
/* A C expression whose value is RTL representing the value of the
|
||||
|
@ -998,7 +998,7 @@ typedef struct xtensa_args {
|
|||
be either a suitable hard register or a pseudo register that has
|
||||
been allocated such a hard register. The difference between an
|
||||
index register and a base register is that the index register may
|
||||
be scaled. */
|
||||
be scaled. */
|
||||
|
||||
#define REGNO_OK_FOR_BASE_P(NUM) \
|
||||
(GP_REG_P (NUM) || GP_REG_P ((unsigned) reg_renumber[NUM]))
|
||||
|
@ -1012,7 +1012,7 @@ typedef struct xtensa_args {
|
|||
must be controlled by `REG_OK_STRICT'. This usually requires two
|
||||
variant definitions, of which `REG_OK_STRICT' controls the one
|
||||
actually used. The difference between an index register and a base
|
||||
register is that the index register may be scaled. */
|
||||
register is that the index register may be scaled. */
|
||||
|
||||
#ifdef REG_OK_STRICT
|
||||
|
||||
|
@ -1091,7 +1091,7 @@ typedef struct xtensa_args {
|
|||
|| (GET_CODE (X) == CONST)))
|
||||
|
||||
/* Nonzero if the constant value X is a legitimate general operand.
|
||||
It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
|
||||
It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
|
||||
#define LEGITIMATE_CONSTANT_P(X) 1
|
||||
|
||||
/* A C expression that is nonzero if X is a legitimate immediate
|
||||
|
@ -1179,7 +1179,7 @@ typedef struct xtensa_args {
|
|||
#define SHIFT_COUNT_TRUNCATED 1
|
||||
|
||||
/* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
|
||||
is done just by pretending it is already truncated. */
|
||||
is done just by pretending it is already truncated. */
|
||||
#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
|
||||
|
||||
/* Specify the machine mode that pointers have.
|
||||
|
@ -1245,7 +1245,7 @@ typedef struct xtensa_args {
|
|||
/* Control the assembler format that we output. */
|
||||
|
||||
/* How to refer to registers in assembler output.
|
||||
This sequence is indexed by compiler's hard-register-number (see above). */
|
||||
This sequence is indexed by compiler's hard-register-number (see above). */
|
||||
#define REGISTER_NAMES \
|
||||
{ \
|
||||
"a0", "sp", "a2", "a3", "a4", "a5", "a6", "a7", \
|
||||
|
@ -1259,7 +1259,7 @@ typedef struct xtensa_args {
|
|||
/* If defined, a C initializer for an array of structures containing a
|
||||
name and a register number. This macro defines additional names
|
||||
for hard registers, thus allowing the 'asm' option in declarations
|
||||
to refer to registers using alternate names. */
|
||||
to refer to registers using alternate names. */
|
||||
#define ADDITIONAL_REGISTER_NAMES \
|
||||
{ \
|
||||
{ "a1", 1 + GP_REG_FIRST } \
|
||||
|
@ -1302,7 +1302,7 @@ typedef struct xtensa_args {
|
|||
LOCAL_LABEL_PREFIX, VALUE)
|
||||
|
||||
/* This is how to output an element of a case-vector that is relative.
|
||||
This is used for pc-relative code. */
|
||||
This is used for pc-relative code. */
|
||||
#define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \
|
||||
do { \
|
||||
fprintf (STREAM, "%s%sL%u-%sL%u\n", integer_asm_op (4, TRUE), \
|
||||
|
@ -1332,7 +1332,7 @@ typedef struct xtensa_args {
|
|||
/* Define output to appear before the constant pool. If the function
|
||||
has been assigned to a specific ELF section, or if it goes into a
|
||||
unique section, set the name of that section to be the literal
|
||||
prefix. */
|
||||
prefix. */
|
||||
#define ASM_OUTPUT_POOL_PROLOGUE(FILE, FUNNAME, FUNDECL, SIZE) \
|
||||
do { \
|
||||
tree fnsection; \
|
||||
|
@ -1367,7 +1367,7 @@ typedef struct xtensa_args {
|
|||
goto JUMPTO; \
|
||||
} while (0)
|
||||
|
||||
/* How to start an assembler comment. */
|
||||
/* How to start an assembler comment. */
|
||||
#define ASM_COMMENT_START "#"
|
||||
|
||||
/* Exception handling TODO!! */
|
||||
|
|
Loading…
Reference in New Issue