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expr.c (expand_expr_real_1): Do not load mem targets into register. 

* expr.c (expand_expr_real_1): Do not load mem targets into register.
	* i386.c (ix86_fixup_binary_operands): Likewise.
	(ix86_expand_unary_operator): Likewise.
	(ix86_expand_fp_absneg_operator): Likewise.
	* optabs.c (expand_vec_cond_expr): Validate dest.

From-SVN: r102570
This commit is contained in:
Jan Hubicka 2005-07-30 00:22:41 +02:00 committed by Jan Hubicka
parent 0bab7d3f43
commit 3bc751bdfe
4 changed files with 10 additions and 34 deletions
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8
gcc/ChangeLog
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@ -1,3 +1,11 @@
2005-07-30 Jan Hubicka <jh@suse.cz>
* expr.c (expand_expr_real_1): Do not load mem targets into register.
* i386.c (ix86_fixup_binary_operands): Likewise.
(ix86_expand_unary_operator): Likewise.
(ix86_expand_fp_absneg_operator): Likewise.
* optabs.c (expand_vec_cond_expr): Validate dest.
2005-07-29 Joseph S. Myers <joseph@codesourcery.com>
PR c/21720

22
gcc/config/i386/i386.c
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@ -8154,17 +8154,6 @@ ix86_fixup_binary_operands (enum rtx_code code, enum machine_mode mode,
&& GET_RTX_CLASS (code) != RTX_COMM_ARITH)
src1 = force_reg (mode, src1);
/* If optimizing, copy to regs to improve CSE */
if (optimize && ! no_new_pseudos)
{
if (GET_CODE (dst) == MEM)
dst = gen_reg_rtx (mode);
if (GET_CODE (src1) == MEM)
src1 = force_reg (mode, src1);
if (GET_CODE (src2) == MEM)
src2 = force_reg (mode, src2);
}
src1 = operands[1] = src1;
src2 = operands[2] = src2;
return dst;
@ -8274,15 +8263,6 @@ ix86_expand_unary_operator (enum rtx_code code, enum machine_mode mode,
if (MEM_P (src) && !matching_memory)
src = force_reg (mode, src);
/* If optimizing, copy to regs to improve CSE. */
if (optimize && ! no_new_pseudos)
{
if (GET_CODE (dst) == MEM)
dst = gen_reg_rtx (mode);
if (GET_CODE (src) == MEM)
src = force_reg (mode, src);
}
/* Emit the instruction. */
op = gen_rtx_SET (VOIDmode, dst, gen_rtx_fmt_e (code, mode, src));
@ -8410,7 +8390,7 @@ ix86_expand_fp_absneg_operator (enum rtx_code code, enum machine_mode mode,
matching_memory = false;
if (MEM_P (dst))
{
if (rtx_equal_p (dst, src) && (!optimize || no_new_pseudos))
if (rtx_equal_p (dst, src))
matching_memory = true;
else
dst = gen_reg_rtx (mode);

12
gcc/expr.c
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@ -6578,18 +6578,6 @@ expand_expr_real_1 (tree exp, rtx target, enum machine_mode tmode,
target = 0;
}
/* If will do cse, generate all results into pseudo registers
since 1) that allows cse to find more things
and 2) otherwise cse could produce an insn the machine
cannot support. An exception is a CONSTRUCTOR into a multi-word
MEM: that's much more likely to be most efficient into the MEM.
Another is a CALL_EXPR which must return in memory. */
if (! cse_not_expected && mode != BLKmode && target
&& (!REG_P (target) || REGNO (target) < FIRST_PSEUDO_REGISTER)
&& ! (code == CONSTRUCTOR && GET_MODE_SIZE (mode) > UNITS_PER_WORD)
&& ! (code == CALL_EXPR && aggregate_value_p (exp, exp)))
target = 0;
switch (code)
{

2
gcc/optabs.c
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@ -5475,7 +5475,7 @@ expand_vec_cond_expr (tree vec_cond_expr, rtx target)
if (icode == CODE_FOR_nothing)
return 0;
if (!target)
if (!target || !insn_data[icode].operand[0].predicate (target, mode))
target = gen_reg_rtx (mode);
/* Get comparison rtx. First expand both cond expr operands. */