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re PR tree-optimization/34046 (verify_flow_info failed)

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PR tree-optimization/34046
	* cfg.c (update_bb_profile_for_threading): Avoid the division for the
	scaling if the old probability is greater than the new base.

From-SVN: r130185
This commit is contained in:
Eric Botcazou 2007-11-14 20:06:10 +01:00 committed by Eric Botcazou
parent a01e283ff5
commit 3bc8ba2577
4 changed files with 131 additions and 2 deletions
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6
gcc/ChangeLog
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@ -1,3 +1,9 @@
2007-11-14 Eric Botcazou <ebotcazou@libertysurf.fr>
PR tree-optimization/34046
* cfg.c (update_bb_profile_for_threading): Avoid the division for the
scaling if the old probability is greater than the new base.
2007-11-14 Sebastian Pop <sebastian.pop@amd.com>
* tree-ssa-loop-ivcanon.c (try_unroll_loop_completely): Remove

10
gcc/cfg.c
View File

@ -990,9 +990,15 @@ update_bb_profile_for_threading (basic_block bb, int edge_frequency,
FOR_EACH_EDGE (c, ei, bb->succs)
{
c->probability = RDIV (c->probability * scale, 65536);
if (c->probability > REG_BR_PROB_BASE)
/* Protect from overflow due to additional scaling. */
if (c->probability > prob)
c->probability = REG_BR_PROB_BASE;
else
{
c->probability = RDIV (c->probability * scale, 65536);
if (c->probability > REG_BR_PROB_BASE)
c->probability = REG_BR_PROB_BASE;
}
}
}

4
gcc/testsuite/ChangeLog
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@ -1,3 +1,7 @@
2007-11-14 Eric Botcazou <ebotcazou@libertysurf.fr>
* gcc.c-torture/compile/20071114-1.c: New test.
2007-11-13 Jerry DeLisle <jvdelisle@gcc.gnu.org>
PR fortran/31608

113
gcc/testsuite/gcc.c-torture/compile/20071114-1.c Normal file
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@ -0,0 +1,113 @@
/* PR tree-optimization/34046 */
/* Origin: dcb <dcb314@hotmail.com> */
typedef unsigned char bool8;
typedef unsigned char uint8_t;
typedef unsigned short int uint16_t;
typedef unsigned int uint32_t;
typedef uint8_t uint8;
typedef uint16_t uint16;
typedef uint32_t uint32;
struct SIAPU
{
uint8 *PC;
uint8 *RAM;
uint8 Bit;
uint32 Address;
uint8 *WaitAddress1;
uint8 *WaitAddress2;
uint8 _Carry;
};
struct SAPU
{
bool8 ShowROM;
uint8 OutPorts [4];
uint8 ExtraRAM [64];
uint16 TimerTarget [3];
};
struct SAPU APU;
struct SIAPU IAPU;
void S9xSetAPUControl (uint8 byte);
void S9xSetAPUDSP (uint8 byte);
uint8 S9xGetAPUDSP ();
uint8 S9xAPUGetByte (uint32 Address)
{
Address &= 0xffff;
if (Address <= 0xff && Address >= 0xf0)
{
if (Address >= 0xf4 && Address <= 0xf7)
{
IAPU.WaitAddress2 = IAPU.WaitAddress1;
IAPU.WaitAddress1 = IAPU.PC;
return (IAPU.RAM [Address]);
}
else if (Address == 0xf3)
return (S9xGetAPUDSP ());
if (Address >= 0xfd)
{
IAPU.WaitAddress2 = IAPU.WaitAddress1;
IAPU.WaitAddress1 = IAPU.PC;
uint8 t = IAPU.RAM [Address];
IAPU.RAM [Address] = 0;
return (t);
}
return (IAPU.RAM [Address]);
}
else
return (IAPU.RAM [Address]);
}
void S9xAPUSetByte (uint8 byte, uint32 Address)
{
Address &= 0xffff;
if (Address <= 0xff && Address >= 0xf0)
{
if (Address == 0xf3)
S9xSetAPUDSP (byte);
else if (Address >= 0xf4 && Address <= 0xf7)
APU.OutPorts [Address - 0xf4] = byte;
else if (Address == 0xf1)
S9xSetAPUControl (byte);
else if (Address < 0xfd)
{
IAPU.RAM [Address] = byte;
if (Address >= 0xfa)
{
if (byte == 0)
APU.TimerTarget [Address - 0xfa] = 0x100;
else
APU.TimerTarget [Address - 0xfa] = byte;
}
}
}
else
{
if (Address < 0xffc0)
IAPU.RAM [Address] = byte;
else
{
APU.ExtraRAM [Address - 0xffc0] = byte;
if (!APU.ShowROM)
IAPU.RAM [Address] = byte;
}
}
}
void ApuCA ()
{
IAPU.Address = *(uint16 *) (IAPU.PC + 1);
IAPU.Bit = (uint8)(IAPU.Address >> 13);
if ((IAPU._Carry))
S9xAPUSetByte (S9xAPUGetByte (IAPU.Address) | (1 << IAPU.Bit), IAPU.Address);
else
S9xAPUSetByte (S9xAPUGetByte (IAPU.Address) & ~(1 << IAPU.Bit), IAPU.Address);
}