i386: Add vashlm3/vashrm3/vlshrm3 to enable vectorization of vector shift vector. [PR98434]
Add expanders for vashl<VI12_AVX512BW>, vlshr<VI12_AVX512BW>, vashr<VI1_AVX512BW> and vashr<v32hi,v16hi,v4di,v8di>. Besides there's some assumption in expand_mult_const that mul and add must be available at the same time, but for i386, addv8qi is restricted under TARGET_64BIT, but mulv8qi not, that could cause ICE. So restrict mulv8qi and shiftv8qi under TARGET_64BIT. gcc/ChangeLog: PR target/98434 * config/i386/i386-expand.c (ix86_expand_vec_interleave): Adjust comments for ix86_expand_vecop_qihi2. (ix86_expand_vecmul_qihi): Renamed to .. (ix86_expand_vecop_qihi2): Adjust function prototype to support shift operation, add static to definition. (ix86_expand_vec_shift_qihi_constant): Add static to definition. (ix86_expand_vecop_qihi): Call ix86_expand_vecop_qihi2 and ix86_expand_vec_shift_qihi_constant. * config/i386/i386-protos.h (ix86_expand_vecmul_qihi): Deleted. (ix86_expand_vec_shift_qihi_constant): Deleted. * config/i386/sse.md (VI12_256_512_AVX512VL): New mode iterator. (mulv8qi3): Call ix86_expand_vecop_qihi directly, add condition TARGET_64BIT. (mul<mode>3): Ditto. (<insn><mode>3): Ditto. (vlshr<mode>3): Extend to support avx512 vlshr. (v<insn><mode>3): New expander for vashr/vlshr/vashl. (v<insn>v8qi3): Ditto. (vashrv8hi3<mask_name>): Renamed to .. (vashr<mode>3): And extend to support V16QImode for avx512. (vashrv16qi3): Deleted. (vashrv2di3<mask_name>): Extend expander to support avx512 instruction. gcc/testsuite/ChangeLog: PR target/98434 * gcc.target/i386/pr98434-1.c: New test. * gcc.target/i386/pr98434-2.c: New test. * gcc.target/i386/avx512vl-pr95488-1.c: Adjust testcase.
This commit is contained in:
liuhongt
parent
fcf617f0d2
commit
3bd86940c4
@ -20705,8 +20705,9 @@ ix86_expand_vec_interleave (rtx targ, rtx op0, rtx op1, bool high_p)
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gcc_assert (ok);
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}
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/* Optimize vector MUL generation for V8QI, V16QI and V32QI
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under TARGET_AVX512BW. i.e. for v16qi a * b, it has
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/* This function is similar as ix86_expand_vecop_qihi,
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but optimized under AVX512BW by using vpmovwb.
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For example, optimize vector MUL generation like
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vpmovzxbw ymm2, xmm0
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vpmovzxbw ymm3, xmm1
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@ -20716,13 +20717,14 @@ ix86_expand_vec_interleave (rtx targ, rtx op0, rtx op1, bool high_p)
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it would take less instructions than ix86_expand_vecop_qihi.
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Return true if success. */
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bool
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ix86_expand_vecmul_qihi (rtx dest, rtx op1, rtx op2)
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static bool
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ix86_expand_vecop_qihi2 (enum rtx_code code, rtx dest, rtx op1, rtx op2)
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{
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machine_mode himode, qimode = GET_MODE (dest);
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rtx hop1, hop2, hdest;
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rtx (*gen_extend)(rtx, rtx);
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rtx (*gen_truncate)(rtx, rtx);
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bool uns_p = (code == ASHIFTRT) ? false : true;
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/* There's no V64HImode multiplication instruction. */
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if (qimode == E_V64QImode)
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@ -20743,17 +20745,17 @@ ix86_expand_vecmul_qihi (rtx dest, rtx op1, rtx op2)
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{
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case E_V8QImode:
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himode = V8HImode;
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gen_extend = gen_zero_extendv8qiv8hi2;
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gen_extend = uns_p ? gen_zero_extendv8qiv8hi2 : gen_extendv8qiv8hi2;
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gen_truncate = gen_truncv8hiv8qi2;
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break;
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case E_V16QImode:
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himode = V16HImode;
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gen_extend = gen_zero_extendv16qiv16hi2;
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gen_extend = uns_p ? gen_zero_extendv16qiv16hi2 : gen_extendv16qiv16hi2;
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gen_truncate = gen_truncv16hiv16qi2;
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break;
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case E_V32QImode:
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himode = V32HImode;
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gen_extend = gen_zero_extendv32qiv32hi2;
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gen_extend = uns_p ? gen_zero_extendv32qiv32hi2 : gen_extendv32qiv32hi2;
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gen_truncate = gen_truncv32hiv32qi2;
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break;
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default:
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@ -20765,7 +20767,7 @@ ix86_expand_vecmul_qihi (rtx dest, rtx op1, rtx op2)
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hdest = gen_reg_rtx (himode);
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emit_insn (gen_extend (hop1, op1));
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emit_insn (gen_extend (hop2, op2));
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emit_insn (gen_rtx_SET (hdest, simplify_gen_binary (MULT, himode,
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emit_insn (gen_rtx_SET (hdest, simplify_gen_binary (code, himode,
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hop1, hop2)));
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emit_insn (gen_truncate (dest, hdest));
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return true;
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@ -20773,8 +20775,9 @@ ix86_expand_vecmul_qihi (rtx dest, rtx op1, rtx op2)
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/* Expand a vector operation shift by constant for a V*QImode in terms of the
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same operation on V*HImode. Return true if success. */
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bool
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ix86_expand_vec_shift_qihi_constant (enum rtx_code code, rtx dest, rtx op1, rtx op2)
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static bool
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ix86_expand_vec_shift_qihi_constant (enum rtx_code code,
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rtx dest, rtx op1, rtx op2)
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{
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machine_mode qimode, himode;
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HOST_WIDE_INT and_constant, xor_constant;
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@ -20886,6 +20889,16 @@ ix86_expand_vecop_qihi (enum rtx_code code, rtx dest, rtx op1, rtx op2)
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bool uns_p = false;
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int i;
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if (CONST_INT_P (op2)
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&& (code == ASHIFT || code == LSHIFTRT || code == ASHIFTRT)
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&& ix86_expand_vec_shift_qihi_constant (code, dest, op1, op2))
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return;
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if (TARGET_AVX512BW
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&& VECTOR_MODE_P (GET_MODE (op2))
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&& ix86_expand_vecop_qihi2 (code, dest, op1, op2))
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return;
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switch (qimode)
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{
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case E_V16QImode:
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@ -20907,7 +20920,6 @@ ix86_expand_vecop_qihi (enum rtx_code code, rtx dest, rtx op1, rtx op2)
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gcc_unreachable ();
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}
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op2_l = op2_h = op2;
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switch (code)
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{
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case MULT:
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@ -20936,17 +20948,46 @@ ix86_expand_vecop_qihi (enum rtx_code code, rtx dest, rtx op1, rtx op2)
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op1_h = gen_reg_rtx (himode);
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ix86_expand_sse_unpack (op1_l, op1, uns_p, false);
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ix86_expand_sse_unpack (op1_h, op1, uns_p, true);
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/* vashr/vlshr/vashl */
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if (GET_MODE_CLASS (GET_MODE (op2)) == MODE_VECTOR_INT)
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{
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rtx tmp = force_reg (qimode, op2);
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op2_l = gen_reg_rtx (himode);
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op2_h = gen_reg_rtx (himode);
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ix86_expand_sse_unpack (op2_l, tmp, uns_p, false);
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ix86_expand_sse_unpack (op2_h, tmp, uns_p, true);
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}
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else
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op2_l = op2_h = op2;
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full_interleave = true;
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break;
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default:
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gcc_unreachable ();
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}
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/* Perform the operation. */
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res_l = expand_simple_binop (himode, code, op1_l, op2_l, NULL_RTX,
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1, OPTAB_DIRECT);
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res_h = expand_simple_binop (himode, code, op1_h, op2_h, NULL_RTX,
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1, OPTAB_DIRECT);
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/* Perform vashr/vlshr/vashl. */
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if (code != MULT
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&& GET_MODE_CLASS (GET_MODE (op2)) == MODE_VECTOR_INT)
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{
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res_l = gen_reg_rtx (himode);
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res_h = gen_reg_rtx (himode);
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emit_insn (gen_rtx_SET (res_l,
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simplify_gen_binary (code, himode,
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op1_l, op2_l)));
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emit_insn (gen_rtx_SET (res_h,
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simplify_gen_binary (code, himode,
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op1_h, op2_h)));
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}
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/* Performance mult/ashr/lshr/ashl. */
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else
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{
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res_l = expand_simple_binop (himode, code, op1_l, op2_l, NULL_RTX,
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1, OPTAB_DIRECT);
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res_h = expand_simple_binop (himode, code, op1_h, op2_h, NULL_RTX,
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1, OPTAB_DIRECT);
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}
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gcc_assert (res_l && res_h);
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/* Merge the data back into the right place. */
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@ -208,10 +208,7 @@ extern void ix86_expand_round (rtx, rtx);
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extern void ix86_expand_rounddf_32 (rtx, rtx);
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extern void ix86_expand_round_sse4 (rtx, rtx);
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extern bool ix86_expand_vecmul_qihi (rtx, rtx, rtx);
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extern void ix86_expand_vecop_qihi (enum rtx_code, rtx, rtx, rtx);
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extern bool ix86_expand_vec_shift_qihi_constant (enum rtx_code, rtx, rtx, rtx);
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extern rtx ix86_split_stack_guard (void);
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extern void ix86_move_vector_high_sse_to_mmx (rtx);
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@ -397,6 +397,10 @@
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(define_mode_iterator VI1_AVX512F
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[(V64QI "TARGET_AVX512F") (V32QI "TARGET_AVX") V16QI])
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(define_mode_iterator VI12_256_512_AVX512VL
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[V64QI (V32QI "TARGET_AVX512VL")
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V32HI (V16HI "TARGET_AVX512VL")])
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(define_mode_iterator VI2_AVX2
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[(V32HI "TARGET_AVX512BW") (V16HI "TARGET_AVX2") V8HI])
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@ -11780,9 +11784,9 @@
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[(set (match_operand:V8QI 0 "register_operand")
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(mult:V8QI (match_operand:V8QI 1 "register_operand")
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(match_operand:V8QI 2 "register_operand")))]
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"TARGET_AVX512VL && TARGET_AVX512BW"
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"TARGET_AVX512VL && TARGET_AVX512BW && TARGET_64BIT"
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{
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gcc_assert (ix86_expand_vecmul_qihi (operands[0], operands[1], operands[2]));
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ix86_expand_vecop_qihi (MULT, operands[0], operands[1], operands[2]);
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DONE;
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})
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@ -11792,8 +11796,6 @@
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(match_operand:VI1_AVX512 2 "register_operand")))]
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"TARGET_SSE2"
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{
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if (ix86_expand_vecmul_qihi (operands[0], operands[1], operands[2]))
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DONE;
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ix86_expand_vecop_qihi (MULT, operands[0], operands[1], operands[2]);
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DONE;
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})
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@ -20239,12 +20241,20 @@
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(lshiftrt:VI12_128
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(match_operand:VI12_128 1 "register_operand")
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(match_operand:VI12_128 2 "nonimmediate_operand")))]
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"TARGET_XOP"
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"TARGET_XOP || (TARGET_AVX512BW && TARGET_AVX512VL)"
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{
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rtx neg = gen_reg_rtx (<MODE>mode);
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emit_insn (gen_neg<mode>2 (neg, operands[2]));
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emit_insn (gen_xop_shl<mode>3 (operands[0], operands[1], neg));
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DONE;
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if (TARGET_XOP)
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{
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rtx neg = gen_reg_rtx (<MODE>mode);
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emit_insn (gen_neg<mode>2 (neg, operands[2]));
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emit_insn (gen_xop_shl<mode>3 (operands[0], operands[1], neg));
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DONE;
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}
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else if (<MODE>mode == V16QImode)
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{
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ix86_expand_vecop_qihi (LSHIFTRT, operands[0], operands[1], operands[2]);
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DONE;
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}
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})
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(define_expand "vlshr<mode>3"
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@ -20263,6 +20273,31 @@
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}
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})
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(define_expand "v<insn><mode>3"
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[(set (match_operand:VI12_256_512_AVX512VL 0 "register_operand")
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(any_shift:VI12_256_512_AVX512VL
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(match_operand:VI12_256_512_AVX512VL 1 "register_operand")
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(match_operand:VI12_256_512_AVX512VL 2 "nonimmediate_operand")))]
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"TARGET_AVX512BW"
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{
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if (<MODE>mode == V32QImode || <MODE>mode == V64QImode)
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{
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ix86_expand_vecop_qihi (<CODE>, operands[0], operands[1], operands[2]);
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DONE;
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}
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})
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(define_expand "v<insn>v8qi3"
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[(set (match_operand:V8QI 0 "register_operand")
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(any_shift:V8QI
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(match_operand:V8QI 1 "register_operand")
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(match_operand:V8QI 2 "nonimmediate_operand")))]
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"TARGET_AVX512BW && TARGET_AVX512VL && TARGET_64BIT"
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{
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ix86_expand_vecop_qihi (<CODE>, operands[0], operands[1], operands[2]);
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DONE;
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})
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(define_expand "vlshr<mode>3"
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[(set (match_operand:VI48_512 0 "register_operand")
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(lshiftrt:VI48_512
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@ -20277,33 +20312,32 @@
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(match_operand:VI48_256 2 "nonimmediate_operand")))]
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"TARGET_AVX2")
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(define_expand "vashrv8hi3<mask_name>"
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[(set (match_operand:V8HI 0 "register_operand")
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(ashiftrt:V8HI
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(match_operand:V8HI 1 "register_operand")
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(match_operand:V8HI 2 "nonimmediate_operand")))]
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(define_expand "vashr<mode>3"
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[(set (match_operand:VI8_256_512 0 "register_operand")
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(ashiftrt:VI8_256_512
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(match_operand:VI8_256_512 1 "register_operand")
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(match_operand:VI8_256_512 2 "nonimmediate_operand")))]
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"TARGET_AVX512F")
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(define_expand "vashr<mode>3"
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[(set (match_operand:VI12_128 0 "register_operand")
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(ashiftrt:VI12_128
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(match_operand:VI12_128 1 "register_operand")
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(match_operand:VI12_128 2 "nonimmediate_operand")))]
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"TARGET_XOP || (TARGET_AVX512BW && TARGET_AVX512VL)"
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{
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if (TARGET_XOP)
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{
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rtx neg = gen_reg_rtx (V8HImode);
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emit_insn (gen_negv8hi2 (neg, operands[2]));
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emit_insn (gen_xop_shav8hi3 (operands[0], operands[1], neg));
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rtx neg = gen_reg_rtx (<MODE>mode);
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emit_insn (gen_neg<mode>2 (neg, operands[2]));
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emit_insn (gen_xop_sha<mode>3 (operands[0], operands[1], neg));
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DONE;
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}
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else if(<MODE>mode == V16QImode)
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{
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ix86_expand_vecop_qihi (ASHIFTRT, operands[0],operands[1], operands[2]);
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DONE;
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}
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})
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(define_expand "vashrv16qi3"
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[(set (match_operand:V16QI 0 "register_operand")
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(ashiftrt:V16QI
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(match_operand:V16QI 1 "register_operand")
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(match_operand:V16QI 2 "nonimmediate_operand")))]
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"TARGET_XOP"
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{
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rtx neg = gen_reg_rtx (V16QImode);
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emit_insn (gen_negv16qi2 (neg, operands[2]));
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emit_insn (gen_xop_shav16qi3 (operands[0], operands[1], neg));
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DONE;
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})
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(define_expand "vashrv2di3<mask_name>"
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@ -20354,10 +20388,18 @@
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(ashift:VI12_128
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(match_operand:VI12_128 1 "register_operand")
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(match_operand:VI12_128 2 "nonimmediate_operand")))]
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"TARGET_XOP"
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"TARGET_XOP || (TARGET_AVX512BW && TARGET_AVX512VL)"
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{
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emit_insn (gen_xop_sha<mode>3 (operands[0], operands[1], operands[2]));
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DONE;
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if (TARGET_XOP)
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{
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emit_insn (gen_xop_sha<mode>3 (operands[0], operands[1], operands[2]));
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DONE;
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}
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else if (<MODE>mode == V16QImode)
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{
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ix86_expand_vecop_qihi (ASHIFT, operands[0], operands[1], operands[2]);
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DONE;
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}
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})
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(define_expand "vashl<mode>3"
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@ -20461,8 +20503,7 @@
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gen = (<CODE> == LSHIFTRT ? gen_xop_shlv16qi3 : gen_xop_shav16qi3);
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emit_insn (gen (operands[0], operands[1], tmp));
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}
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else if (!ix86_expand_vec_shift_qihi_constant (<CODE>, operands[0],
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operands[1], operands[2]))
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else
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ix86_expand_vecop_qihi (<CODE>, operands[0], operands[1], operands[2]);
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DONE;
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})
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@ -1,10 +1,10 @@
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/* PR target/pr95488 */
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/* { dg-do compile } */
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/* { dg-options "-O2 -mavx512bw -mavx512vl" } */
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/* { dg-final { scan-assembler-times "vpmovzxbw" 8 } } */
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/* { dg-final { scan-assembler-times "vpmovzxbw" 8 { target { ! ia32 } } } } */
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/* { dg-final { scan-assembler-times "vpmullw\[^\n\]*ymm" 2 } } */
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/* { dg-final { scan-assembler-times "vpmullw\[^\n\]*xmm" 2 } } */
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/* { dg-final { scan-assembler-times "vpmovwb" 4 } } */
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/* { dg-final { scan-assembler-times "vpmullw\[^\n\]*xmm" 2 { target { ! ia32 } } } } */
|
||||
/* { dg-final { scan-assembler-times "vpmovwb" 4 { target { ! ia32 } } } } */
|
||||
|
||||
typedef char v16qi __attribute__ ((vector_size (16)));
|
||||
typedef char v8qi __attribute__ ((vector_size (8)));
|
||||
|
||||
64
gcc/testsuite/gcc.target/i386/pr98434-1.c
Normal file
64
gcc/testsuite/gcc.target/i386/pr98434-1.c
Normal file
@ -0,0 +1,64 @@
|
||||
/* { dg-do compile } */
|
||||
/* { dg-options "-mavx512bw -mavx512vl -O2 -mprefer-vector-width=512" } */
|
||||
/* { dg-final { scan-assembler-times {vpsravw[\t ]*%xmm} 2 { target { ! ia32 } } } } */
|
||||
/* { dg-final { scan-assembler-times {vpsrlvw[\t ]*%ymm} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vpsllvw[\t ]*%zmm} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {vpsllvq[\t ]*%xmm} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vpsravq[\t ]*%ymm} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vpsrlvq[\t ]*%zmm} 1 } } */
|
||||
|
||||
int n;
|
||||
|
||||
typedef char v8qi __attribute__((vector_size (8)));
|
||||
typedef char v16qi __attribute__((vector_size (16)));
|
||||
typedef char v32qi __attribute__((vector_size (32)));
|
||||
typedef short v8hi __attribute__((vector_size (16)));
|
||||
typedef short v16hi __attribute__((vector_size (32)));
|
||||
typedef short v32hi __attribute__((vector_size (64)));
|
||||
typedef long long v2di __attribute__((vector_size (16)));
|
||||
typedef long long v4di __attribute__((vector_size (32)));
|
||||
typedef long long v8di __attribute__((vector_size (64)));
|
||||
typedef unsigned char v8uqi __attribute__((vector_size (8)));
|
||||
typedef unsigned char v16uqi __attribute__((vector_size (16)));
|
||||
typedef unsigned char v32uqi __attribute__((vector_size (32)));
|
||||
typedef unsigned short v8uhi __attribute__((vector_size (16)));
|
||||
typedef unsigned short v16uhi __attribute__((vector_size (32)));
|
||||
typedef unsigned short v32uhi __attribute__((vector_size (64)));
|
||||
typedef unsigned long long v2udi __attribute__((vector_size (16)));
|
||||
typedef unsigned long long v4udi __attribute__((vector_size (32)));
|
||||
typedef unsigned long long v8udi __attribute__((vector_size (64)));
|
||||
|
||||
#define FOO(TYPE, OP, NAME) \
|
||||
__attribute__((noipa)) TYPE \
|
||||
foo_##TYPE##_##NAME (TYPE a, TYPE b) \
|
||||
{ \
|
||||
return a OP b; \
|
||||
} \
|
||||
|
||||
FOO (v8qi, <<, vashl);
|
||||
FOO (v8qi, >>, vashr);
|
||||
FOO (v8uqi, >>, vlshr);
|
||||
FOO (v16qi, <<, vashl);
|
||||
FOO (v16qi, >>, vashr);
|
||||
FOO (v16uqi, >>, vlshr);
|
||||
FOO (v32qi, <<, vashl);
|
||||
FOO (v32qi, >>, vashr);
|
||||
FOO (v32uqi, >>, vlshr);
|
||||
FOO (v8hi, <<, vashl);
|
||||
FOO (v8hi, >>, vashr);
|
||||
FOO (v8uhi, >>, vlshr);
|
||||
FOO (v16hi, <<, vashl);
|
||||
FOO (v16hi, >>, vashr);
|
||||
FOO (v16uhi, >>, vlshr);
|
||||
FOO (v32hi, <<, vashl);
|
||||
FOO (v32hi, >>, vashr);
|
||||
FOO (v32uhi, >>, vlshr);
|
||||
FOO (v2di, <<, vashl);
|
||||
FOO (v2di, >>, vashr);
|
||||
FOO (v2udi, >>, vlshr);
|
||||
FOO (v4di, <<, vashl);
|
||||
FOO (v4di, >>, vashr);
|
||||
FOO (v4udi, >>, vlshr);
|
||||
FOO (v8di, <<, vashl);
|
||||
FOO (v8di, >>, vashr);
|
||||
FOO (v8udi, >>, vlshr);
|
||||
129
gcc/testsuite/gcc.target/i386/pr98434-2.c
Normal file
129
gcc/testsuite/gcc.target/i386/pr98434-2.c
Normal file
@ -0,0 +1,129 @@
|
||||
/* { dg-do run } */
|
||||
/* { dg-options "-O2 -mprefer-vector-width=512 -mavx512vl -mavx512bw" } */
|
||||
/* { dg-require-effective-target avx512bw } */
|
||||
/* { dg-require-effective-target avx512vl } */
|
||||
|
||||
#include "pr98434-1.c"
|
||||
void test (void);
|
||||
#define DO_TEST test
|
||||
#define AVX512VL
|
||||
#define AVX512BW
|
||||
#include "avx512-check.h"
|
||||
|
||||
|
||||
typedef char int8;
|
||||
typedef unsigned char uint8;
|
||||
typedef short int16;
|
||||
typedef unsigned short uint16;
|
||||
typedef long long int64;
|
||||
typedef unsigned long long uint64;
|
||||
|
||||
#define F_EMULATE(TYPE, SIZE, OP, NAME) \
|
||||
__attribute__((noipa, optimize("-fno-tree-vectorize"))) void \
|
||||
emulate_##SIZE##_##TYPE##_##NAME (TYPE *a, \
|
||||
TYPE *b, \
|
||||
TYPE *c) \
|
||||
{ \
|
||||
int i; \
|
||||
for (i = 0; i < SIZE; i++) \
|
||||
{ \
|
||||
a[i] = b[i] OP c[i]; \
|
||||
} \
|
||||
}
|
||||
|
||||
F_EMULATE (int8, 8, <<, vashl);
|
||||
F_EMULATE (int8, 8, >>, vashr);
|
||||
F_EMULATE (uint8, 8, >>, vlshr);
|
||||
F_EMULATE (int8, 16, <<, vashl);
|
||||
F_EMULATE (int8, 16, >>, vashr);
|
||||
F_EMULATE (uint8, 16, >>, vlshr);
|
||||
F_EMULATE (int8, 32, <<, vashl);
|
||||
F_EMULATE (int8, 32, >>, vashr);
|
||||
F_EMULATE (uint8, 32, >>, vlshr);
|
||||
F_EMULATE (int16, 8, <<, vashl);
|
||||
F_EMULATE (int16, 8, >>, vashr);
|
||||
F_EMULATE (uint16, 8, >>, vlshr);
|
||||
F_EMULATE (int16, 16, <<, vashl);
|
||||
F_EMULATE (int16, 16, >>, vashr);
|
||||
F_EMULATE (uint16, 16, >>, vlshr);
|
||||
F_EMULATE (int16, 32, <<, vashl);
|
||||
F_EMULATE (int16, 32, >>, vashr);
|
||||
F_EMULATE (uint16, 32, >>, vlshr);
|
||||
F_EMULATE (int64, 2, <<, vashl);
|
||||
F_EMULATE (int64, 2, >>, vashr);
|
||||
F_EMULATE (uint64, 2, >>, vlshr);
|
||||
F_EMULATE (int64, 4, <<, vashl);
|
||||
F_EMULATE (int64, 4, >>, vashr);
|
||||
F_EMULATE (uint64, 4, >>, vlshr);
|
||||
F_EMULATE (int64, 8, <<, vashl);
|
||||
F_EMULATE (int64, 8, >>, vashr);
|
||||
F_EMULATE (uint64, 8, >>, vlshr);
|
||||
|
||||
#define VSHIFT(VTYPE, NAME, src1, src2) \
|
||||
foo_##VTYPE##_##NAME (src1, src2)
|
||||
|
||||
#define EMULATE(SIZE, TYPE, NAME, dst, src1, src2) \
|
||||
emulate_##SIZE##_##TYPE##_##NAME (dst, src1, src2)
|
||||
|
||||
#define F_TEST_SHIFT(VTYPE, VTYPEU, TYPE, TYPEU, SIZE) \
|
||||
__attribute__((noipa, optimize("-fno-tree-vectorize"))) void \
|
||||
test_##VTYPE ()\
|
||||
{\
|
||||
TYPE src1[SIZE], src2[SIZE], ref[SIZE]; \
|
||||
TYPEU usrc1[SIZE], usrc2[SIZE], uref[SIZE]; \
|
||||
VTYPE dst; \
|
||||
VTYPEU udst; \
|
||||
int i;\
|
||||
for (i = 0; i < SIZE; i++)\
|
||||
{\
|
||||
dst[i] = ref[i] = -i; \
|
||||
src1[i] = -(i + SIZE); \
|
||||
src2[i] = i % 8; \
|
||||
udst[i] = uref[i] = i; \
|
||||
usrc1[i] = (i + SIZE); \
|
||||
usrc2[i] = (i % 8); \
|
||||
}\
|
||||
EMULATE(SIZE, TYPE, vashl, ref, src1, src2); \
|
||||
dst = VSHIFT(VTYPE, vashl, *((VTYPE* )&src1[0]), *((VTYPE*) &src2[0])); \
|
||||
for (i = 0; i < SIZE; i++)\
|
||||
{\
|
||||
if(dst[i] != ref[i]) __builtin_abort();\
|
||||
}\
|
||||
EMULATE(SIZE, TYPE, vashr, ref, src1, src2); \
|
||||
dst = VSHIFT(VTYPE, vashr, *((VTYPE* )&src1[0]), *((VTYPE*) &src2[0])); \
|
||||
for (i = 0; i < SIZE; i++)\
|
||||
{\
|
||||
if(dst[i] != ref[i]) __builtin_abort();\
|
||||
}\
|
||||
EMULATE(SIZE, TYPEU, vlshr, uref, usrc1, usrc2); \
|
||||
udst = VSHIFT(VTYPEU, vlshr, *((VTYPEU* )&usrc1[0]), *((VTYPEU*) &usrc2[0])); \
|
||||
for (i = 0; i < SIZE; i++)\
|
||||
{\
|
||||
if(udst[i] != uref[i]) __builtin_abort();\
|
||||
}\
|
||||
}
|
||||
|
||||
F_TEST_SHIFT (v8qi, v8uqi, int8, uint8, 8);
|
||||
F_TEST_SHIFT (v16qi, v16uqi, int8, uint8, 16);
|
||||
F_TEST_SHIFT (v32qi, v32uqi, int8, uint8, 32);
|
||||
F_TEST_SHIFT (v8hi, v8uhi, int16, uint16, 8);
|
||||
F_TEST_SHIFT (v16hi, v16uhi, int16, uint16, 16);
|
||||
F_TEST_SHIFT (v32hi, v32uhi, int16, uint16, 32);
|
||||
F_TEST_SHIFT (v2di, v2udi, int64, uint64, 2);
|
||||
F_TEST_SHIFT (v4di, v4udi, int64, uint64, 4);
|
||||
F_TEST_SHIFT (v8di, v8udi, int64, uint64, 8);
|
||||
|
||||
|
||||
void
|
||||
test (void)
|
||||
{
|
||||
test_v8qi ();
|
||||
test_v16qi ();
|
||||
test_v32qi ();
|
||||
test_v8hi ();
|
||||
test_v16hi ();
|
||||
test_v32hi ();
|
||||
test_v2di ();
|
||||
test_v4di ();
|
||||
test_v8di ();
|
||||
}
|
||||
Loading…
Reference in New Issue
Block a user