Preparatory work for PR target/21623:
* alpha.c (secondary_reload_class): Rename to: (alpha_secondary_reload_class). * alpha.h, alpha-protos.h: Likewise. * mn10300.c (secondary_reload_class): Rename to: (mn10300_secondary_reload_class). * mn10300.h, mn10300-protos.h: Likewise. * pa.c (secondary_reload_class): Rename to: (pa_secondary_reload_class). * pa.h, pa-protos.h: Likewise. * rs6000.c (secondary_reload_class): Rename to: rs6000_secondary_reload_class. * rs6000.h, rs6000-protos.h: Likewise. From-SVN: r107381
This commit is contained in:
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3c4774e08c
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@ -1,3 +1,19 @@
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2005-11-22 J"orn Rennecke <joern.rennecke@st.com>
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Preparatory work for PR target/21623:
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* alpha.c (secondary_reload_class): Rename to:
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(alpha_secondary_reload_class).
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* alpha.h, alpha-protos.h: Likewise.
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* mn10300.c (secondary_reload_class): Rename to:
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(mn10300_secondary_reload_class).
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* mn10300.h, mn10300-protos.h: Likewise.
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* pa.c (secondary_reload_class): Rename to:
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(pa_secondary_reload_class).
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* pa.h, pa-protos.h: Likewise.
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* rs6000.c (secondary_reload_class): Rename to:
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rs6000_secondary_reload_class.
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* rs6000.h, rs6000-protos.h: Likewise.
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2005-11-22 Eric Botcazou <ebotcazou@adacore.com>
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PR middle-end/22561
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@ -53,8 +53,9 @@ extern rtx split_small_symbolic_operand (rtx);
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extern void get_aligned_mem (rtx, rtx *, rtx *);
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extern rtx get_unaligned_address (rtx, int);
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extern enum reg_class alpha_preferred_reload_class (rtx, enum reg_class);
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extern enum reg_class secondary_reload_class (enum reg_class,
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enum machine_mode, rtx, int);
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extern enum reg_class alpha_secondary_reload_class (enum reg_class,
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enum machine_mode, rtx,
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int);
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extern void alpha_set_memflags (rtx, rtx);
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extern bool alpha_split_const_mov (enum machine_mode, rtx *);
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@ -1597,7 +1597,7 @@ alpha_preferred_reload_class(rtx x, enum reg_class class)
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from register elimination into a DImode fp register. */
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enum reg_class
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secondary_reload_class (enum reg_class class, enum machine_mode mode,
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alpha_secondary_reload_class (enum reg_class class, enum machine_mode mode,
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rtx x, int in)
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{
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if ((mode == QImode || mode == HImode) && ! TARGET_BWX)
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@ -672,10 +672,10 @@ enum reg_class {
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FP register. */
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#define SECONDARY_INPUT_RELOAD_CLASS(CLASS,MODE,IN) \
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secondary_reload_class((CLASS), (MODE), (IN), 1)
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alpha_secondary_reload_class((CLASS), (MODE), (IN), 1)
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#define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS,MODE,OUT) \
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secondary_reload_class((CLASS), (MODE), (OUT), 0)
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alpha_secondary_reload_class((CLASS), (MODE), (OUT), 0)
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/* If we are copying between general and FP registers, we need a memory
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location unless the FIX extension is available. */
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@ -36,8 +36,8 @@ extern void mn10300_print_reg_list (FILE *, int);
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extern int mn10300_get_live_callee_saved_regs (void);
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extern void mn10300_gen_multiple_store (int);
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extern void notice_update_cc (rtx, rtx);
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extern enum reg_class secondary_reload_class (enum reg_class,
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enum machine_mode, rtx);
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extern enum reg_class mn10300_secondary_reload_class (enum reg_class,
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enum machine_mode, rtx);
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extern const char *output_tst (rtx, rtx);
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extern int store_multiple_operation (rtx, enum machine_mode);
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extern int symbolic_operand (rtx, enum machine_mode);
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@ -1337,7 +1337,8 @@ store_multiple_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
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We might be able to simplify this. */
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enum reg_class
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secondary_reload_class (enum reg_class class, enum machine_mode mode, rtx in)
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mn10300_secondary_reload_class (enum reg_class class, enum machine_mode mode,
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rtx in)
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{
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/* Memory loads less than a full word wide can't have an
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address or stack pointer destination. They must use
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@ -425,7 +425,7 @@ enum reg_class {
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(!TARGET_AM33 && (MODE == QImode || MODE == HImode) ? DATA_REGS : CLASS)
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#define SECONDARY_RELOAD_CLASS(CLASS,MODE,IN) \
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secondary_reload_class(CLASS,MODE,IN)
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mn10300_secondary_reload_class(CLASS,MODE,IN)
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/* Return the maximum number of consecutive registers
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needed to represent mode MODE in a register of class CLASS. */
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@ -106,8 +106,8 @@ extern int emit_move_sequence (rtx *, enum machine_mode, rtx);
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extern int emit_hpdiv_const (rtx *, int);
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extern int is_function_label_plus_const (rtx);
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extern int jump_in_call_delay (rtx);
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extern enum reg_class secondary_reload_class (enum reg_class,
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enum machine_mode, rtx);
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extern enum reg_class pa_secondary_reload_class (enum reg_class,
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enum machine_mode, rtx);
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extern int hppa_fpstore_bypass_p (rtx, rtx);
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extern int attr_length_millicode_call (rtx);
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extern int attr_length_call (rtx, int);
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@ -5576,7 +5576,7 @@ output_arg_descriptor (rtx call_insn)
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It might be worthwhile to try and make this a leaf function too. */
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enum reg_class
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secondary_reload_class (enum reg_class class, enum machine_mode mode, rtx in)
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pa_secondary_reload_class (enum reg_class class, enum machine_mode mode, rtx in)
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{
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int regno, is_symbolic;
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@ -5589,7 +5589,7 @@ secondary_reload_class (enum reg_class class, enum machine_mode mode, rtx in)
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return R1_REGS;
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/* Profiling showed the PA port spends about 1.3% of its compilation
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time in true_regnum from calls inside secondary_reload_class. */
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time in true_regnum from calls inside pa_secondary_reload_class. */
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if (GET_CODE (in) == REG)
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{
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@ -5628,7 +5628,7 @@ secondary_reload_class (enum reg_class class, enum machine_mode mode, rtx in)
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in = XEXP (in, 0);
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/* Profiling has showed GCC spends about 2.6% of its compilation
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time in symbolic_operand from calls inside secondary_reload_class.
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time in symbolic_operand from calls inside pa_secondary_reload_class.
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We use an inline copy and only compute its return value once to avoid
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useless work. */
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@ -535,7 +535,7 @@ extern struct rtx_def *hppa_pic_save_rtx (void);
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#define SECONDARY_RELOAD_CLASS(CLASS,MODE,IN) \
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((CLASS == BASE_REG_CLASS && GET_CODE (IN) == REG \
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&& REGNO (IN) < FIRST_PSEUDO_REGISTER) \
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? NO_REGS : secondary_reload_class (CLASS, MODE, IN))
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? NO_REGS : pa_secondary_reload_class (CLASS, MODE, IN))
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#define MAYBE_FP_REG_CLASS_P(CLASS) \
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reg_classes_intersect_p ((CLASS), FP_REGS)
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@ -64,8 +64,8 @@ extern int insvdi_rshift_rlwimi_p (rtx, rtx, rtx);
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extern int registers_ok_for_quad_peep (rtx, rtx);
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extern int mems_ok_for_quad_peep (rtx, rtx);
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extern bool gpr_or_gpr_p (rtx, rtx);
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extern enum reg_class secondary_reload_class (enum reg_class,
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enum machine_mode, rtx);
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extern enum reg_class rs6000_secondary_reload_class (enum reg_class,
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enum machine_mode, rtx);
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extern int ccr_bit (rtx, int);
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extern int extract_MB (rtx);
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extern int extract_ME (rtx);
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NO_REGS is returned. */
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enum reg_class
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secondary_reload_class (enum reg_class class,
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enum machine_mode mode ATTRIBUTE_UNUSED,
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rtx in)
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rs6000_secondary_reload_class (enum reg_class class,
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enum machine_mode mode ATTRIBUTE_UNUSED,
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rtx in)
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{
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int regno;
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@ -1187,7 +1187,7 @@ enum reg_class
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NO_REGS is returned. */
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#define SECONDARY_RELOAD_CLASS(CLASS,MODE,IN) \
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secondary_reload_class (CLASS, MODE, IN)
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rs6000_secondary_reload_class (CLASS, MODE, IN)
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/* If we are copying between FP or AltiVec registers and anything
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else, we need a memory location. */
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