re PR tree-optimization/69848 (poor vectorization of a loop from SPEC2006 464.h264ref)
PR tree-optimization/69848 * config/aarch64/aarch64-simd.md (vcond<mode><mode>): Invert NE and swtich operands to avoid additional NOT instruction. (vcond<v_cmp_mixed><mode>): Ditto. (vcondu<mode><mode>, vcondu<mode><v_cmp_mixed>): Ditto. gcc/testsuite * gcc.target/aarch64/simd/vcond-ne-bit.c: New test. From-SVN: r239502
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@ -1,3 +1,11 @@
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2016-08-16 Bin Cheng <bin.cheng@arm.com>
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PR tree-optimization/69848
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* config/aarch64/aarch64-simd.md (vcond<mode><mode>): Invert NE
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and swtich operands to avoid additional NOT instruction.
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(vcond<v_cmp_mixed><mode>): Ditto.
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(vcondu<mode><mode>, vcondu<mode><v_cmp_mixed>): Ditto.
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2016-08-16 Eric Botcazou <ebotcazou@adacore.com>
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* doc/install.texi (*-*-solaris2*): Adjust latest change.
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@ -2573,7 +2573,17 @@
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"TARGET_SIMD"
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{
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rtx mask = gen_reg_rtx (<V_cmp_result>mode);
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enum rtx_code code = GET_CODE (operands[3]);
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/* NE is handled as !EQ in vec_cmp patterns, we can explicitly invert
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it as well as switch operands 1/2 in order to avoid the additional
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NOT instruction. */
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if (code == NE)
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{
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operands[3] = gen_rtx_fmt_ee (EQ, GET_MODE (operands[3]),
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operands[4], operands[5]);
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std::swap (operands[1], operands[2]);
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}
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emit_insn (gen_vec_cmp<mode><v_cmp_result> (mask, operands[3],
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operands[4], operands[5]));
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emit_insn (gen_vcond_mask_<mode><v_cmp_result> (operands[0], operands[1],
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@ -2593,7 +2603,17 @@
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"TARGET_SIMD"
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{
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rtx mask = gen_reg_rtx (<V_cmp_result>mode);
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enum rtx_code code = GET_CODE (operands[3]);
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/* NE is handled as !EQ in vec_cmp patterns, we can explicitly invert
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it as well as switch operands 1/2 in order to avoid the additional
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NOT instruction. */
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if (code == NE)
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{
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operands[3] = gen_rtx_fmt_ee (EQ, GET_MODE (operands[3]),
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operands[4], operands[5]);
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std::swap (operands[1], operands[2]);
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}
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emit_insn (gen_vec_cmp<mode><v_cmp_result> (mask, operands[3],
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operands[4], operands[5]));
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emit_insn (gen_vcond_mask_<v_cmp_mixed><v_cmp_result> (
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@ -2614,7 +2634,17 @@
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"TARGET_SIMD"
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{
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rtx mask = gen_reg_rtx (<MODE>mode);
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enum rtx_code code = GET_CODE (operands[3]);
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/* NE is handled as !EQ in vec_cmp patterns, we can explicitly invert
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it as well as switch operands 1/2 in order to avoid the additional
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NOT instruction. */
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if (code == NE)
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{
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operands[3] = gen_rtx_fmt_ee (EQ, GET_MODE (operands[3]),
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operands[4], operands[5]);
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std::swap (operands[1], operands[2]);
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}
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emit_insn (gen_vec_cmp<mode><mode> (mask, operands[3],
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operands[4], operands[5]));
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emit_insn (gen_vcond_mask_<mode><v_cmp_result> (operands[0], operands[1],
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@ -2633,7 +2663,17 @@
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"TARGET_SIMD"
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{
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rtx mask = gen_reg_rtx (<V_cmp_result>mode);
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enum rtx_code code = GET_CODE (operands[3]);
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/* NE is handled as !EQ in vec_cmp patterns, we can explicitly invert
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it as well as switch operands 1/2 in order to avoid the additional
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NOT instruction. */
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if (code == NE)
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{
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operands[3] = gen_rtx_fmt_ee (EQ, GET_MODE (operands[3]),
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operands[4], operands[5]);
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std::swap (operands[1], operands[2]);
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}
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emit_insn (gen_vec_cmp<v_cmp_mixed><v_cmp_mixed> (
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mask, operands[3],
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operands[4], operands[5]));
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@ -1,3 +1,8 @@
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2016-08-16 Bin Cheng <bin.cheng@arm.com>
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PR tree-optimization/69848
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* gcc.target/aarch64/simd/vcond-ne-bit.c: New test.
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2016-08-16 Martin Liska <mliska@suse.cz>
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* gcc.dg/tree-prof/val-prof-7.c (int main): Change size
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@ -0,0 +1,32 @@
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/* { dg-do run } */
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/* { dg-options "-save-temps" } */
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/* { dg-require-effective-target vect_int } */
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/* { dg-require-effective-target vect_condition } */
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#include <stdlib.h>
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int fn1 (int) __attribute__ ((noinline));
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int a[128];
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int fn1(int d) {
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int b, c = 1;
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for (b = 0; b < 128; b++)
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if (a[b])
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c = 0;
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return c;
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}
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int
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main (void)
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{
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int i;
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for (i = 0; i < 128; i++)
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a[i] = 0;
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if (fn1(10) != 1)
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abort ();
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a[3] = 2;
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a[24] = 1;
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if (fn1(10) != 0)
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abort ();
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return 0;
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}
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/* { dg-final { scan-assembler-not "\[ \t\]not\[ \t\]" } } */
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