[AARCH64] Use STLUR for atomic_store
Use the STLUR instruction introduced in Armv8.4-a.
This instruction has the store-release semantic like STLR but can take a
9-bit unscaled signed immediate offset.
Example test case:
```
void
foo ()
{
int32_t *atomic_vals = calloc (4, sizeof (int32_t));
atomic_store_explicit (atomic_vals + 1, 2, memory_order_release);
}
```
Before patch generates
```
foo:
stp x29, x30, [sp, -16]!
mov x1, 4
mov x0, x1
mov x29, sp
bl calloc
mov w1, 2
add x0, x0, 4
stlr w1, [x0]
ldp x29, x30, [sp], 16
ret
```
After patch generates
```
foo:
stp x29, x30, [sp, -16]!
mov x1, 4
mov x0, x1
mov x29, sp
bl calloc
mov w1, 2
stlur w1, [x0, 4]
ldp x29, x30, [sp], 16
ret
```
We introduce a new feature flag to indicate the presence of this instruction.
The feature flag is called AARCH64_ISA_RCPC8_4 and is included when targeting
armv8.4 architecture.
We also introduce an "arch" attribute to be checked called "rcpc8_4" after this
feature flag.
gcc/
2018-09-19 Matthew Malcomson <matthew.malcomson@arm.com>
* config/aarch64/aarch64-protos.h
(aarch64_offset_9bit_signed_unscaled_p): New declaration.
* config/aarch64/aarch64.md (arches): New "rcpc8_4" attribute value.
(arch_enabled): Add check for "rcpc8_4" attribute value of "arch".
* config/aarch64/aarch64.h (AARCH64_FL_RCPC8_4): New bitfield.
(AARCH64_FL_FOR_ARCH8_4): Include AARCH64_FL_RCPC8_4.
(AARCH64_FL_PROFILE): Move index so flags are ordered.
(AARCH64_ISA_RCPC8_4): New flag.
* config/aarch64/aarch64.c (offset_9bit_signed_unscaled_p): Renamed
to aarch64_offset_9bit_signed_unscaled_p.
* config/aarch64/atomics.md (atomic_store<mode>): Allow offset
and use stlur.
* config/aarch64/constraints.md (Ust): New constraint.
* config/aarch64/predicates.md.
(aarch64_9bit_offset_memory_operand): New predicate.
(aarch64_rcpc_memory_operand): New predicate.
gcc/testsuite/
2018-09-19 Matthew Malcomson <matthew.malcomson@arm.com>
* gcc.target/aarch64/atomic-store.c: New.
From-SVN: r264421
This commit is contained in:
Matthew Malcomson
Matthew Malcomson
parent
574f5885f7
commit
3c5af60836
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@ -1,3 +1,22 @@
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2018-09-19 Matthew Malcomson <matthew.malcomson@arm.com>
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* config/aarch64/aarch64-protos.h
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(aarch64_offset_9bit_signed_unscaled_p): New declaration.
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* config/aarch64/aarch64.md (arches): New "rcpc8_4" attribute value.
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(arch_enabled): Add check for "rcpc8_4" attribute value of "arch".
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* config/aarch64/aarch64.h (AARCH64_FL_RCPC8_4): New bitfield.
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(AARCH64_FL_FOR_ARCH8_4): Include AARCH64_FL_RCPC8_4.
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(AARCH64_FL_PROFILE): Move index so flags are ordered.
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(AARCH64_ISA_RCPC8_4): New flag.
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* config/aarch64/aarch64.c (offset_9bit_signed_unscaled_p): Renamed
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to aarch64_offset_9bit_signed_unscaled_p.
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* config/aarch64/atomics.md (atomic_store<mode>): Allow offset
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and use stlur.
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* config/aarch64/constraints.md (Ust): New constraint.
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* config/aarch64/predicates.md.
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(aarch64_9bit_offset_memory_operand): New predicate.
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(aarch64_rcpc_memory_operand): New predicate.
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2018-09-19 Eric Botcazou <ebotcazou@adacore.com>
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PR rtl-optimization/87361
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@ -436,6 +436,7 @@ void aarch64_split_add_offset (scalar_int_mode, rtx, rtx, rtx, rtx, rtx);
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bool aarch64_mov_operand_p (rtx, machine_mode);
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rtx aarch64_reverse_mask (machine_mode, unsigned int);
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bool aarch64_offset_7bit_signed_scaled_p (machine_mode, poly_int64);
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bool aarch64_offset_9bit_signed_unscaled_p (machine_mode, poly_int64);
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char *aarch64_output_sve_cnt_immediate (const char *, const char *, rtx);
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char *aarch64_output_sve_addvl_addpl (rtx, rtx, rtx);
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char *aarch64_output_sve_inc_dec_immediate (const char *, rtx);
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@ -4452,9 +4452,9 @@ aarch64_offset_7bit_signed_scaled_p (machine_mode mode, poly_int64 offset)
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/* Return true if OFFSET is a signed 9-bit value. */
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static inline bool
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offset_9bit_signed_unscaled_p (machine_mode mode ATTRIBUTE_UNUSED,
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poly_int64 offset)
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bool
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aarch64_offset_9bit_signed_unscaled_p (machine_mode mode ATTRIBUTE_UNUSED,
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poly_int64 offset)
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{
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HOST_WIDE_INT const_offset;
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return (offset.is_constant (&const_offset)
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@ -5721,7 +5721,7 @@ aarch64_classify_address (struct aarch64_address_info *info,
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instruction memory accesses. */
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if (mode == TImode || mode == TFmode)
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return (aarch64_offset_7bit_signed_scaled_p (DImode, offset)
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&& (offset_9bit_signed_unscaled_p (mode, offset)
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&& (aarch64_offset_9bit_signed_unscaled_p (mode, offset)
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|| offset_12bit_unsigned_scaled_p (mode, offset)));
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/* A 7bit offset check because OImode will emit a ldp/stp
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@ -5735,7 +5735,8 @@ aarch64_classify_address (struct aarch64_address_info *info,
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ldr/str instructions (only big endian will get here). */
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if (mode == CImode)
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return (aarch64_offset_7bit_signed_scaled_p (TImode, offset)
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&& (offset_9bit_signed_unscaled_p (V16QImode, offset + 32)
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&& (aarch64_offset_9bit_signed_unscaled_p (V16QImode,
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offset + 32)
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|| offset_12bit_unsigned_scaled_p (V16QImode,
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offset + 32)));
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@ -5775,7 +5776,7 @@ aarch64_classify_address (struct aarch64_address_info *info,
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|| known_eq (GET_MODE_SIZE (mode), 16))
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&& aarch64_offset_7bit_signed_scaled_p (mode, offset));
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else
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return (offset_9bit_signed_unscaled_p (mode, offset)
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return (aarch64_offset_9bit_signed_unscaled_p (mode, offset)
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|| offset_12bit_unsigned_scaled_p (mode, offset));
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}
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@ -5828,7 +5829,7 @@ aarch64_classify_address (struct aarch64_address_info *info,
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*/
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if (mode == TImode || mode == TFmode)
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return (aarch64_offset_7bit_signed_scaled_p (mode, offset)
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&& offset_9bit_signed_unscaled_p (mode, offset));
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&& aarch64_offset_9bit_signed_unscaled_p (mode, offset));
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if (load_store_pair_p)
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return ((known_eq (GET_MODE_SIZE (mode), 4)
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@ -5836,7 +5837,7 @@ aarch64_classify_address (struct aarch64_address_info *info,
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|| known_eq (GET_MODE_SIZE (mode), 16))
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&& aarch64_offset_7bit_signed_scaled_p (mode, offset));
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else
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return offset_9bit_signed_unscaled_p (mode, offset);
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return aarch64_offset_9bit_signed_unscaled_p (mode, offset);
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}
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return false;
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@ -157,9 +157,10 @@ extern unsigned aarch64_architecture_version;
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#define AARCH64_FL_SM4 (1 << 17) /* Has ARMv8.4-A SM3 and SM4. */
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#define AARCH64_FL_SHA3 (1 << 18) /* Has ARMv8.4-a SHA3 and SHA512. */
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#define AARCH64_FL_F16FML (1 << 19) /* Has ARMv8.4-a FP16 extensions. */
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#define AARCH64_FL_RCPC8_4 (1 << 20) /* Has ARMv8.4-a RCPC extensions. */
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/* Statistical Profiling extensions. */
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#define AARCH64_FL_PROFILE (1 << 20)
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#define AARCH64_FL_PROFILE (1 << 21)
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/* Has FP and SIMD. */
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#define AARCH64_FL_FPSIMD (AARCH64_FL_FP | AARCH64_FL_SIMD)
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@ -178,7 +179,7 @@ extern unsigned aarch64_architecture_version;
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(AARCH64_FL_FOR_ARCH8_2 | AARCH64_FL_V8_3)
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#define AARCH64_FL_FOR_ARCH8_4 \
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(AARCH64_FL_FOR_ARCH8_3 | AARCH64_FL_V8_4 | AARCH64_FL_F16FML \
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| AARCH64_FL_DOTPROD)
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| AARCH64_FL_DOTPROD | AARCH64_FL_RCPC8_4)
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/* Macros to test ISA flags. */
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@ -199,6 +200,7 @@ extern unsigned aarch64_architecture_version;
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#define AARCH64_ISA_SM4 (aarch64_isa_flags & AARCH64_FL_SM4)
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#define AARCH64_ISA_SHA3 (aarch64_isa_flags & AARCH64_FL_SHA3)
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#define AARCH64_ISA_F16FML (aarch64_isa_flags & AARCH64_FL_F16FML)
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#define AARCH64_ISA_RCPC8_4 (aarch64_isa_flags & AARCH64_FL_RCPC8_4)
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/* Crypto is an optional extension to AdvSIMD. */
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#define TARGET_CRYPTO (TARGET_SIMD && AARCH64_ISA_CRYPTO)
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@ -263,7 +263,7 @@
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;; alternative). This attribute is used to compute attribute "enabled", use type
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;; "any" to enable an alternative in all cases.
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(define_enum "arches" [ any fp simd sve fp16])
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(define_enum "arches" [ any rcpc8_4 fp simd sve fp16])
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(define_enum_attr "arch" "arches" (const_string "any"))
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@ -285,6 +285,9 @@
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(ior
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(eq_attr "arch" "any")
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(and (eq_attr "arch" "rcpc8_4")
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(match_test "AARCH64_ISA_RCPC8_4"))
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(and (eq_attr "arch" "fp")
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(match_test "TARGET_FLOAT"))
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@ -481,9 +481,9 @@
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)
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(define_insn "atomic_store<mode>"
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[(set (match_operand:ALLI 0 "aarch64_sync_memory_operand" "=Q")
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[(set (match_operand:ALLI 0 "aarch64_rcpc_memory_operand" "=Q,Ust")
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(unspec_volatile:ALLI
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[(match_operand:ALLI 1 "general_operand" "rZ")
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[(match_operand:ALLI 1 "general_operand" "rZ,rZ")
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(match_operand:SI 2 "const_int_operand")] ;; model
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UNSPECV_STL))]
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""
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@ -491,9 +491,12 @@
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enum memmodel model = memmodel_from_int (INTVAL (operands[2]));
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if (is_mm_relaxed (model) || is_mm_consume (model) || is_mm_acquire (model))
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return "str<atomic_sfx>\t%<w>1, %0";
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else
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else if (which_alternative == 0)
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return "stlr<atomic_sfx>\t%<w>1, %0";
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else
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return "stlur<atomic_sfx>\t%<w>1, %0";
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}
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[(set_attr "arch" "*,rcpc8_4")]
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)
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(define_insn "@aarch64_load_exclusive<mode>"
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@ -225,6 +225,11 @@
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(and (match_code "mem")
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(match_test "REG_P (XEXP (op, 0))")))
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(define_memory_constraint "Ust"
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"@internal
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A memory address with 9bit unscaled offset."
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(match_operand 0 "aarch64_9bit_offset_memory_operand"))
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(define_memory_constraint "Ump"
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"@internal
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A memory address suitable for a load/store pair operation."
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@ -359,6 +359,36 @@
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(and (match_operand 0 "memory_operand")
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(match_code "reg" "0")))
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(define_predicate "aarch64_9bit_offset_memory_operand"
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(and (match_operand 0 "memory_operand")
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(ior (match_code "reg" "0")
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(and (match_code "plus" "0")
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(match_code "reg" "00")
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(match_code "const_int" "01"))))
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{
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rtx mem_op = XEXP (op, 0);
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if (REG_P (mem_op))
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return GET_MODE (mem_op) == DImode;
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rtx plus_op0 = XEXP (mem_op, 0);
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rtx plus_op1 = XEXP (mem_op, 1);
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if (GET_MODE (plus_op0) != DImode)
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return false;
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poly_int64 offset;
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if (!poly_int_rtx_p (plus_op1, &offset))
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gcc_unreachable ();
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return aarch64_offset_9bit_signed_unscaled_p (mode, offset);
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})
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(define_predicate "aarch64_rcpc_memory_operand"
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(if_then_else (match_test "AARCH64_ISA_RCPC8_4")
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(match_operand 0 "aarch64_9bit_offset_memory_operand")
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(match_operand 0 "aarch64_sync_memory_operand")))
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;; Predicates for parallel expanders based on mode.
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(define_special_predicate "vect_par_cnst_hi_half"
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(match_code "parallel")
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@ -1,3 +1,7 @@
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2018-09-19 Matthew Malcomson <matthew.malcomson@arm.com>
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* gcc.target/aarch64/atomic-store.c: New.
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2018-09-19 Richard Biener <rguenther@suse.de>
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PR tree-optimization/87349
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@ -0,0 +1,75 @@
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/* { dg-do compile } */
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/* { dg-options "-march=armv8.4-a -O2" } */
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#include <stdatomic.h>
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typedef __INT8_TYPE__ int8_t;
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typedef __INT16_TYPE__ int16_t;
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typedef __INT32_TYPE__ int32_t;
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typedef __INT64_TYPE__ int64_t;
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#define STORE_TESTS(size) \
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void \
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foo##size (int##size##_t *atomic_vals) \
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{ \
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atomic_store_explicit (atomic_vals, 2, memory_order_relaxed); \
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atomic_store_explicit (atomic_vals, 2, memory_order_release); \
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atomic_store_explicit ((atomic_vals + 1), 2, memory_order_release); \
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atomic_store ((atomic_vals + 2), 2); \
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atomic_store_explicit ((atomic_vals + 3), 2, memory_order_relaxed); \
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}
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STORE_TESTS (8);
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/* { dg-final { scan-assembler-times "strb\tw\[0-9\]+, \\\[x\[0-9\]+\\\]" 1 } } */
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/* { dg-final { scan-assembler-times "stlrb\tw\[0-9\]+, \\\[x\[0-9\]+\\\]" 1 { target { ! ilp32 } } } } */
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/* { dg-final { scan-assembler-times "stlrb\tw\[0-9\]+, \\\[x\[0-9\]+\\\]" 2 { target { ilp32 } } } } */
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/* { dg-final { scan-assembler-times "stlurb\tw\[0-9\]+, \\\[x\[0-9\]+, 1\\\]" 1 } } */
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/* { dg-final { scan-assembler-times "stlurb\tw\[0-9\]+, \\\[x\[0-9\]+, 2\\\]" 1 } } */
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/* { dg-final { scan-assembler-times "strb\tw\[0-9\]+, \\\[x\[0-9\]+, 3\\\]" 1 } } */
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STORE_TESTS (16);
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/* { dg-final { scan-assembler-times "strh\tw\[0-9\]+, \\\[x\[0-9\]+\\\]" 1 } } */
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/* { dg-final { scan-assembler-times "stlrh\tw\[0-9\]+, \\\[x\[0-9\]+\\\]" 1 } } */
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/* { dg-final { scan-assembler-times "stlurh\tw\[0-9\]+, \\\[x\[0-9\]+, 2\\\]" 1 } } */
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/* { dg-final { scan-assembler-times "stlurh\tw\[0-9\]+, \\\[x\[0-9\]+, 4\\\]" 1 } } */
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/* { dg-final { scan-assembler-times "strh\tw\[0-9\]+, \\\[x\[0-9\]+, 6\\\]" 1 } } */
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STORE_TESTS (32);
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/* { dg-final { scan-assembler-times "str\tw\[0-9\]+, \\\[x\[0-9\]+\\\]" 1 } } */
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/* { dg-final { scan-assembler-times "stlr\tw\[0-9\]+, \\\[x\[0-9\]+\\\]" 1 } } */
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/* { dg-final { scan-assembler-times "stlur\tw\[0-9\]+, \\\[x\[0-9\]+, 4\\\]" 1 } } */
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/* { dg-final { scan-assembler-times "stlur\tw\[0-9\]+, \\\[x\[0-9\]+, 8\\\]" 1 } } */
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/* { dg-final { scan-assembler-times "str\tw\[0-9\]+, \\\[x\[0-9\]+, 12\\\]" 1 } } */
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STORE_TESTS (64);
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/* { dg-final { scan-assembler-times "str\tx\[0-9\]+, \\\[x\[0-9\]+\\\]" 1 } } */
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/* { dg-final { scan-assembler-times "stlur\tx\[0-9\]+, \\\[x\[0-9\]+, 8\\\]" 1 } } */
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/* { dg-final { scan-assembler-times "stlur\tx\[0-9\]+, \\\[x\[0-9\]+, 16\\\]" 1 } } */
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/* { dg-final { scan-assembler-times "str\tx\[0-9\]+, \\\[x\[0-9\]+, 24\\\]" 1 } } */
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void
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foo_toolarge_offset (int64_t *atomic_vals)
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{
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/* 9bit signed unscaled immediate =>
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largest representable value +255.
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smallest representable value -256. */
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atomic_store_explicit (atomic_vals + 32, 2, memory_order_release);
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atomic_store_explicit (atomic_vals - 33, 2, memory_order_release);
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}
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void
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foo_negative (int8_t *atomic_vals)
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{
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atomic_store_explicit (atomic_vals - 2, 2, memory_order_release);
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}
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/* { dg-final { scan-assembler-times "stlurb\tw\[0-9\]+, \\\[x\[0-9\]+, -2\\\]" 1 { target { ! ilp32 } } } } */
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#pragma GCC target ("arch=armv8.3-a")
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void
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foo_older_arch (int64_t *atomic_vals)
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{
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atomic_store_explicit (atomic_vals + 2, 2, memory_order_release);
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}
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/* Three times, one for each of the three above functions. */
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/* { dg-final { scan-assembler-times "stlr\tx\[0-9\]+, \\\[x\[0-9\]+\\\]" 4 } } */
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Loading…
Reference in New Issue